Improve debug information on mtcrf test case

diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py
index ce934609b23be8199a010d9eb51ac3c2564ce8be..710fc6c0fcee9aa87a8df801dab2f180c70484dc 100644 (file)
--- a/src/openpower/decoder/isa/test_caller.py
+++ b/src/openpower/decoder/isa/test_caller.py
@@ -314,7 +314,7 @@ class DecoderTestCase(FHDLTestCase):
             print("cr", sim.cr)
             expected = (7-i)
             # check CR[0]/1/2/3 as well
-            print("cr%d", sim.crl[i])
+            print("cr%d" % i, sim.crl[i].asint(True))
             self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
             # check CR itself
             self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 64))