This obsoletes the R600LowerInstruction and SIPropagateImmReads passes.
// R600 Passes
FunctionPass* createR600KernelParametersPass(const TargetData* TD);
FunctionPass *createR600CodeEmitterPass(formatted_raw_ostream &OS);
-FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm);
// SI Passes
FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
-FunctionPass *createSIPropagateImmReadsPass(TargetMachine &tm);
FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
// Passes common to R600 and SI
bool AMDGPUPassConfig::addPreRegAlloc() {
const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
- if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
- PM->add(createR600LowerInstructionsPass(*TM));
- } else {
+ if (ST.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
PM->add(createSIAssignInterpRegsPass(*TM));
}
PM->add(createAMDGPULowerInstructionsPass(*TM));
}
bool AMDGPUPassConfig::addPreEmitPass() {
- const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
PM->add(createAMDILCFGPreparationPass(*TM));
PM->add(createAMDILCFGStructurizerPass(*TM));
- if (ST.device()->getGeneration() == AMDILDeviceInfo::HD7XXX) {
- PM->add(createSIPropagateImmReadsPass(*TM));
- }
return false;
}
//===----------------------------------------------------------------------===//
// TargetLowering Implementation Help Functions End
//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// Instruction generation functions
-//===----------------------------------------------------------------------===//
-MachineOperand
-AMDILTargetLowering::convertToReg(MachineOperand op) const
-{
- if (op.isReg()) {
- return op;
- } else if (op.isImm()) {
- uint32_t loadReg
- = genVReg(op.getParent()->getDesc().OpInfo[0].RegClass);
- generateMachineInst(AMDIL::LOADCONST_i32, loadReg)
- .addImm(op.getImm());
- op.ChangeToRegister(loadReg, false);
- } else if (op.isFPImm()) {
- uint32_t loadReg
- = genVReg(op.getParent()->getDesc().OpInfo[0].RegClass);
- generateMachineInst(AMDIL::LOADCONST_f32, loadReg)
- .addFPImm(op.getFPImm());
- op.ChangeToRegister(loadReg, false);
- } else if (op.isMBB()) {
- op.ChangeToRegister(0, false);
- } else if (op.isFI()) {
- op.ChangeToRegister(0, false);
- } else if (op.isCPI()) {
- op.ChangeToRegister(0, false);
- } else if (op.isJTI()) {
- op.ChangeToRegister(0, false);
- } else if (op.isGlobal()) {
- op.ChangeToRegister(0, false);
- } else if (op.isSymbol()) {
- op.ChangeToRegister(0, false);
- }/* else if (op.isMetadata()) {
- op.ChangeToRegister(0, false);
- }*/
- return op;
-}
//===----------------------------------------------------------------------===//
// TargetLowering Class Implementation Begins
// Instructions support
//===--------------------------------------------------------------------===//
include "AMDILInstructions.td"
-
-//===--------------------------------------------------------------------===//
-// Instruction Pattern support - This Must be the last include in the file
-// as it requires items defined in other files
-//===--------------------------------------------------------------------===//
-include "AMDILInstrPatterns.td"
-
+++ /dev/null
-//===- AMDILInstrPatterns.td - AMDIL Target ------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//==-----------------------------------------------------------------------===//
-//===--------------------------------------------------------------------===//
-// This file holds all the custom patterns that are used by the amdil backend
-//
-//===--------------------------------------------------------------------===//
-//===--------------------------------------------------------------------===//
-// Custom patterns for conversion operations
-//===--------------------------------------------------------------------===////
-// float ==> long patterns
-// unsigned: f32 -> i64
-def FTOUL : Pat<(i64 (fp_to_uint GPRF32:$src)),
- (LCREATE (FTOU GPRF32:$src), (LOADCONST_i32 0))>;
-// unsigned: i64 -> f32
-def ULTOF : Pat<(f32 (uint_to_fp GPRI64:$src)),
- (UTOF (LLO GPRI64:$src))>;
-
-// LLVM isn't lowering this correctly, so writing a pattern that
-// matches it isntead.
-def : Pat<(build_vector (i32 imm:$src)),
- (VCREATE_v4i32 (LOADCONST_i32 imm:$src))>;
-
-// Calls:
-def : Pat<(IL_call tglobaladdr:$dst),
- (CALL tglobaladdr:$dst)>;
-def : Pat<(IL_call texternalsym:$dst),
- (CALL texternalsym:$dst)>;
-def : Pat<(IL_call tconstpool:$dst),
- (CALL tconstpool:$dst)>;
// Operations in this file are generic to all data types
// This opcode has custom swizzle pattern encoded in Swizzle Encoder
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
- defm LOADCONST : ILConstant<"mov $dst, $val">;
defm MOVE : UnaryOpMC<IL_OP_MOV, IL_mov>;
defm PHIMOVE : UnaryOpMC<IL_OP_MOV, IL_phimov>;
}
int SPAdj,
RegScavenger *RS) const
{
- assert(SPAdj == 0 && "Unexpected");
- MachineInstr &MI = *II;
- MachineFunction &MF = *MI.getParent()->getParent();
- MachineFrameInfo *MFI = MF.getFrameInfo();
- unsigned int y = MI.getNumOperands();
- for (unsigned int x = 0; x < y; ++x) {
- if (!MI.getOperand(x).isFI()) {
- continue;
- }
- const AMDILInstrInfo * AMDILII =
- static_cast<const AMDILInstrInfo *>(TM.getInstrInfo());
- bool def = AMDILII->isStoreInst(&MI);
- int FrameIndex = MI.getOperand(x).getIndex();
- int64_t Offset = MFI->getObjectOffset(FrameIndex);
- //int64_t Size = MF.getFrameInfo()->getObjectSize(FrameIndex);
- // An optimization is to only use the offsets if the size
- // is larger than 4, which means we are storing an array
- // instead of just a pointer. If we are size 4 then we can
- // just do register copies since we don't need to worry about
- // indexing dynamically
- MachineInstr *nMI = MF.CreateMachineInstr(
- TII.get(AMDIL::LOADCONST_i32), MI.getDebugLoc());
- nMI->addOperand(MachineOperand::CreateReg(AMDIL::DFP, true));
- nMI->addOperand(
- MachineOperand::CreateImm(Offset));
- MI.getParent()->insert(II, nMI);
- nMI = MF.CreateMachineInstr(
- TII.get(AMDIL::ADD_INT), MI.getDebugLoc());
- nMI->addOperand(MachineOperand::CreateReg(AMDIL::DFP, true));
- nMI->addOperand(MachineOperand::CreateReg(AMDIL::DFP, false));
- nMI->addOperand(MachineOperand::CreateReg(AMDIL::FP, false));
-
- MI.getParent()->insert(II, nMI);
- if (MI.getOperand(x).isReg() == false) {
- MI.getOperand(x).ChangeToRegister(
- nMI->getOperand(0).getReg(), def);
- } else {
- MI.getOperand(x).setReg(
- nMI->getOperand(0).getReg());
- }
- }
+ assert(!"Implement");
}
void
R600ISelLowering.cpp \
R600InstrInfo.cpp \
R600KernelParameters.cpp \
- R600LowerInstructions.cpp \
R600MachineFunctionInfo.cpp \
R600RegisterInfo.cpp \
SIAssignInterpRegs.cpp \
SIInstrInfo.cpp \
SIISelLowering.cpp \
SIMachineFunctionInfo.cpp \
- SIPropagateImmReads.cpp \
SIRegisterInfo.cpp \
MCTargetDesc/AMDILMCAsmInfo.cpp \
MCTargetDesc/AMDILMCTargetDesc.cpp \
def MOV : R600_1OP <0x19, "MOV", []>;
+class MOV_IMM <ValueType vt, Operand immType> : InstR600 <0x19,
+ (outs R600_Reg32:$dst),
+ (ins R600_Reg32:$alu_literal, immType:$imm),
+ "MOV_IMM $dst, $imm",
+ [], AnyALU
+>;
+
+def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
+def : Pat <
+ (imm:$val),
+ (MOV_IMM_I32 (i32 ALU_LITERAL_X), imm:$val)
+>;
+
+def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
+def : Pat <
+ (fpimm:$val),
+ (MOV_IMM_F32 (i32 ALU_LITERAL_X), fpimm:$val)
+>;
+
def KILLGT : R600_2OP <
0x2D, "KILLGT",
[]
class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
(intr R600_Reg32:$src),
- (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
+ (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
>;
def MULADD_eg : MULADD_Common<0x14>;
+++ /dev/null
-//===-- R600LowerInstructions.cpp - Lower unsupported AMDIL instructions --===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This pass lowers AMDIL MachineInstrs that aren't supported by the R600
-// target to either supported AMDIL MachineInstrs or R600 MachineInstrs.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPU.h"
-#include "AMDGPUInstrInfo.h"
-#include "AMDGPUUtil.h"
-#include "AMDIL.h"
-#include "AMDILRegisterInfo.h"
-#include "R600InstrInfo.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Constants.h"
-#include "llvm/Target/TargetInstrInfo.h"
-
-#include <stdio.h>
-
-using namespace llvm;
-
-namespace {
- class R600LowerInstructionsPass : public MachineFunctionPass {
-
- private:
- static char ID;
- const R600InstrInfo * TII;
-
- public:
- R600LowerInstructionsPass(TargetMachine &tm) :
- MachineFunctionPass(ID),
- TII(static_cast<const R600InstrInfo*>(tm.getInstrInfo()))
- { }
-
- const char *getPassName() const { return "R600 Lower Instructions"; }
- virtual bool runOnMachineFunction(MachineFunction &MF);
-
- };
-} /* End anonymous namespace */
-
-char R600LowerInstructionsPass::ID = 0;
-
-FunctionPass *llvm::createR600LowerInstructionsPass(TargetMachine &tm) {
- return new R600LowerInstructionsPass(tm);
-}
-
-bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
-{
- for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
- BB != BB_E; ++BB) {
- MachineBasicBlock &MBB = *BB;
- for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
- I != MBB.end(); I = Next, Next = llvm::next(I) ) {
-
- MachineInstr &MI = *I;
- switch(MI.getOpcode()) {
- case AMDIL::LOADCONST_f32:
- case AMDIL::LOADCONST_i32:
- {
- bool canInline = false;
- unsigned inlineReg;
- MachineOperand & dstOp = MI.getOperand(0);
- MachineOperand & immOp = MI.getOperand(1);
- if (immOp.isFPImm()) {
- const ConstantFP * cfp = immOp.getFPImm();
- if (cfp->isZero()) {
- canInline = true;
- inlineReg = AMDIL::ZERO;
- } else if (cfp->isExactlyValue(1.0f)) {
- canInline = true;
- inlineReg = AMDIL::ONE;
- } else if (cfp->isExactlyValue(0.5f)) {
- canInline = true;
- inlineReg = AMDIL::HALF;
- }
- }
-
- if (canInline) {
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::COPY))
- .addOperand(dstOp)
- .addReg(inlineReg);
- } else {
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::MOV))
- .addOperand(dstOp)
- .addReg(AMDIL::ALU_LITERAL_X)
- .addOperand(immOp);
- }
- break;
- }
- default:
- continue;
- }
- MI.eraseFromParent();
- }
- }
- return false;
-}
MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
int64_t Imm) const
{
- MachineInstr * MI = MF->CreateMachineInstr(get(AMDIL::V_MOV_IMM), DebugLoc());
+ MachineInstr * MI = MF->CreateMachineInstr(get(AMDIL::V_MOV_IMM_I32), DebugLoc());
MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
MachineInstrBuilder(MI).addImm(Imm);
//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
-def V_MOV_IMM : VOP1 <
+class V_MOV_IMM <Operand immType, SDNode immNode> : VOP1 <
0x1,
(outs VReg_32:$dst),
- (ins f32imm:$src0),
+ (ins immType:$src0),
"V_MOV_IMM",
- []
+ [(set VReg_32:$dst, (immNode:$src0))]
>;
+def V_MOV_IMM_I32 : V_MOV_IMM<i32imm, imm>;
+def V_MOV_IMM_F32 : V_MOV_IMM<f32imm, fpimm>;
+
def S_MOV_IMM_I32 : SOP1 <
0x3,
(outs SReg_32:$dst),
(ins i32Literal:$src0),
- "S_MOV_IMM",
- [] > {
- let neverHasSideEffects = 1;
-}
+ "S_MOV_IMM_I32",
+ [(set SReg_32:$dst, (imm:$src0))]
+>;
+
let isCodeGenOnly = 1, isPseudo = 1 in {
+++ /dev/null
-//===-- SIPropagateImmReads.cpp - Lower Immediate Reads Pass --------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// We can't do this in the ConvertToISA pass, because later passes might
-// create LOADCONST_* instructions that we would miss. This is why we need
-// a separate pass for this.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPU.h"
-#include "AMDGPUUtil.h"
-#include "SIInstrInfo.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-
-using namespace llvm;
-
-namespace {
-
-class SIPropagateImmReadsPass : public MachineFunctionPass {
-
-private:
- static char ID;
- TargetMachine &TM;
-
-public:
- SIPropagateImmReadsPass(TargetMachine &tm) :
- MachineFunctionPass(ID), TM(tm) { }
-
- virtual bool runOnMachineFunction(MachineFunction &MF);
-};
-
-} // End anonymous namespace
-
-char SIPropagateImmReadsPass::ID = 0;
-
-FunctionPass *llvm::createSIPropagateImmReadsPass(TargetMachine &tm) {
- return new SIPropagateImmReadsPass(tm);
-}
-
-bool SIPropagateImmReadsPass::runOnMachineFunction(MachineFunction &MF)
-{
- const SIInstrInfo * TII = static_cast<const SIInstrInfo*>(TM.getInstrInfo());
-
- for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
- BB != BB_E; ++BB) {
- MachineBasicBlock &MBB = *BB;
- for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
- I != MBB.end(); I = Next, Next = llvm::next(I)) {
- MachineInstr &MI = *I;
-
- switch (MI.getOpcode()) {
- case AMDIL::LOADCONST_f32:
- case AMDIL::LOADCONST_i32:
- case AMDIL::LOADCONST_i64:
- break;
- default:
- continue;
- }
-
- // XXX: Create and use S_MOV_IMM for SREGs
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::V_MOV_IMM))
- .addOperand(MI.getOperand(0))
- .addOperand(MI.getOperand(1));
-
- MI.eraseFromParent();
- }
- }
- return false;
-}
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