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diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 8a40cceacb9b74d106ada1acfee2cf4a36c51cce..1acf572e346615466a9561d5a6565776b75416c5 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -65,8 +65,11 @@ hot-loops.
 
 The other reason for not adding an SVP64-Prefixed instruction without
 also having it as a Scalar un-prefixed instruction is that if the
-32-bit encoding is ever allocated to a completely unrelated operation
+32-bit encoding is ever allocated in a future revision
+of the Power ISA
+to a completely unrelated operation
 then how can a Vectorised version of that new instruction ever be added?
+The uniformity and RISC Abstraction is irreparably damaged.
 Bottom line here is that the fundamental RISC Principle is strictly adhered
 to, even though these are Advanced 64-bit Vector instructions.
 Advocates of the RISC Principle will appreciate the uniformity of