type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
boot_loader_mem=system.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.nvmem system.physmem
midr_regval=890224640
+num_work_ids=16
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
[system.vncserver]
type=VncServer
+frame_capture=false
number=0
port=5900
+Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simout
+Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:32:34
-gem5 started Nov 22 2011 02:00:14
-gem5 executing on u200540-lin
+gem5 compiled Jan 8 2012 22:12:58
+gem5 started Jan 9 2012 03:33:38
+gem5 executing on zizzer
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2582494395500 because m5_exit instruction encountered
sim_seconds 2.582494 # Number of seconds simulated
sim_ticks 2582494395500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86259 # Simulator instruction rate (inst/s)
-host_tick_rate 2789337609 # Simulator tick rate (ticks/s)
-host_mem_usage 380504 # Number of bytes of host memory used
-host_seconds 925.85 # Real time elapsed on the host
+host_inst_rate 65512 # Simulator instruction rate (inst/s)
+host_tick_rate 2118472138 # Simulator tick rate (ticks/s)
+host_mem_usage 384260 # Number of bytes of host memory used
+host_seconds 1219.04 # Real time elapsed on the host
sim_insts 79862069 # Number of instructions simulated
system.l2c.replacements 132200 # number of replacements
system.l2c.tagsinuse 27582.989225 # Cycle average of tags in use
system.cpu0.rename.IQFullEvents 580883 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 3149232 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 205 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 54779836 # Number of destination operands rename has renamed
+system.cpu0.rename.RenamedOperands 54779837 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 247536349 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 247487579 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 48770 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 41441157 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 13338678 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.UndoneMaps 13338679 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 828868 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 763855 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 8500592 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedStores 7686805 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1443183 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1570137 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 50961906 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1297751 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 80276175 # Number of instructions issued
+system.cpu0.iq.iqInstsAdded 50961905 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1297752 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 80276174 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 137636 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 9888896 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 22816025 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 253323 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.iqSquashedNonSpecRemoved 253324 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 109741052 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.731505 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.440076 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 10111373 9.21% 82.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 4133530 3.77% 85.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 3177611 2.90% 88.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 9954077 9.07% 97.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1265280 1.15% 99.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 9954078 9.07% 97.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1265279 1.15% 99.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 670333 0.61% 99.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 224189 0.20% 99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 78860 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 88461 0.11% 0.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 29731482 37.04% 37.15% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 29731481 37.04% 37.15% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 62351 0.08% 37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.22% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 7257159 9.04% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 80276175 # Type of FU issued
+system.cpu0.iq.FU_type_0::total 80276174 # Type of FU issued
system.cpu0.iq.rate 0.227757 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 8028360 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.100009 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 278513866 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_reads 278513864 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 62161443 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 46668616 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.int_inst_queue_wakeup_accesses 46668615 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 11568 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 6980 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5172 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 88210043 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 88210042 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6031 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 399886 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.iewDispSquashedInsts 243567 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 11770384 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 7686805 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 865739 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispNonSpecInsts 865740 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 62160 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 5553 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 20554 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 507509 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 136100 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 643609 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 79551296 # Number of executed instructions
+system.cpu0.iew.iewExecutedInsts 79551295 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 42843907 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 724879 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_branches 6433542 # Number of branches executed
system.cpu0.iew.exec_stores 7167520 # Number of stores executed
system.cpu0.iew.exec_rate 0.225700 # Inst execution rate
-system.cpu0.iew.wb_sent 79133798 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 46673788 # cumulative count of insts written-back
+system.cpu0.iew.wb_sent 79133797 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 46673787 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 24793926 # num instructions producing a value
system.cpu0.iew.wb_consumers 46078393 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.cpi_total 8.431852 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.118598 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.118598 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 354175082 # number of integer regfile reads
-system.cpu0.int_regfile_writes 46137252 # number of integer regfile writes
+system.cpu0.int_regfile_reads 354175079 # number of integer regfile reads
+system.cpu0.int_regfile_writes 46137251 # number of integer regfile writes
system.cpu0.fp_regfile_reads 4205 # number of floating regfile reads
system.cpu0.fp_regfile_writes 1348 # number of floating regfile writes
system.cpu0.misc_regfile_reads 65629786 # number of misc regfile reads
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
boot_loader_mem=system.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.nvmem system.physmem
midr_regval=890224640
+num_work_ids=16
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
[system.vncserver]
type=VncServer
+frame_capture=false
number=0
port=5900
+Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout
+Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:32:34
-gem5 started Nov 22 2011 02:00:08
-gem5 executing on u200540-lin
+gem5 compiled Jan 8 2012 22:12:58
+gem5 started Jan 9 2012 03:32:35
+gem5 executing on zizzer
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2503566110500 because m5_exit instruction encountered
sim_seconds 2.503566 # Number of seconds simulated
sim_ticks 2503566110500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 84156 # Simulator instruction rate (inst/s)
-host_tick_rate 2743719152 # Simulator tick rate (ticks/s)
-host_mem_usage 380536 # Number of bytes of host memory used
-host_seconds 912.47 # Real time elapsed on the host
+host_inst_rate 72389 # Simulator instruction rate (inst/s)
+host_tick_rate 2360079964 # Simulator tick rate (ticks/s)
+host_mem_usage 384076 # Number of bytes of host memory used
+host_seconds 1060.80 # Real time elapsed on the host
sim_insts 76790007 # Number of instructions simulated
system.l2c.replacements 119509 # number of replacements
system.l2c.tagsinuse 25929.897253 # Cycle average of tags in use
system.cpu.rename.IQFullEvents 914485 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3979731 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 42252 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 118358542 # Number of destination operands rename has renamed
+system.cpu.rename.RenamedOperands 118358543 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 523323093 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 523225639 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 97454 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 77492718 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 40865823 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 40865824 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1204637 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1098724 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12304657 # count of insts added to the skid buffer
system.cpu.memDep0.insertedStores 14168730 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1896802 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2281380 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 102860212 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1874615 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 126873317 # Number of instructions issued
+system.cpu.iq.iqInstsAdded 102860211 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1874616 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 126873316 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 252471 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 26973483 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 72956952 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 374922 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedNonSpecRemoved 374923 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 155542524 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.815683 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.505358 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 15115277 9.72% 79.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 7538109 4.85% 84.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6517896 4.19% 88.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12766128 8.21% 96.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2735747 1.76% 98.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12766129 8.21% 96.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2735746 1.76% 98.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1395145 0.90% 99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 422031 0.27% 99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 132475 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 60069483 47.35% 47.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 60069482 47.35% 47.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 96615 0.08% 47.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 12655733 9.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 126873317 # Type of FU issued
+system.cpu.iq.FU_type_0::total 126873316 # Type of FU issued
system.cpu.iq.rate 0.305048 # Inst issue rate
system.cpu.iq.fu_busy_cnt 8900311 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.070151 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 418533130 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 418533128 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 131726191 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87292109 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_wakeup_accesses 87292108 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 24017 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13690 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10446 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 135654306 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 135654305 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 12792 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 614767 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.iewDispSquashedInsts 473979 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 21982315 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 14168730 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1228030 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispNonSpecInsts 1228031 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 85187 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 7556 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 32657 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 850397 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 257130 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1107527 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 123429780 # Number of executed instructions
+system.cpu.iew.iewExecutedInsts 123429779 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 52914304 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3443537 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_branches 11705842 # Number of branches executed
system.cpu.iew.exec_stores 12487221 # Number of stores executed
system.cpu.iew.exec_rate 0.296769 # Inst execution rate
-system.cpu.iew.wb_sent 121771134 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 87302555 # cumulative count of insts written-back
+system.cpu.iew.wb_sent 121771133 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 87302554 # cumulative count of insts written-back
system.cpu.iew.wb_producers 47043389 # num instructions producing a value
system.cpu.iew.wb_consumers 86638668 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.cpi_total 5.416227 # CPI: Total CPI of All Threads
system.cpu.ipc 0.184630 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.184630 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 559625789 # number of integer regfile reads
-system.cpu.int_regfile_writes 89694790 # number of integer regfile writes
+system.cpu.int_regfile_reads 559625786 # number of integer regfile reads
+system.cpu.int_regfile_writes 89694789 # number of integer regfile writes
system.cpu.fp_regfile_reads 8322 # number of floating regfile reads
system.cpu.fp_regfile_writes 2832 # number of floating regfile writes
system.cpu.misc_regfile_reads 137256850 # number of misc regfile reads
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
+Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 17:44:50
-gem5 executing on u200540-lin
+gem5 compiled Jan 8 2012 22:11:51
+gem5 started Jan 9 2012 02:13:40
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_seconds 0.274199 # Number of seconds simulated
sim_ticks 274198757500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 124379 # Simulator instruction rate (inst/s)
-host_tick_rate 59483814 # Simulator tick rate (ticks/s)
-host_mem_usage 219308 # Number of bytes of host memory used
-host_seconds 4609.64 # Real time elapsed on the host
+host_inst_rate 102660 # Simulator instruction rate (inst/s)
+host_tick_rate 49096980 # Simulator tick rate (ticks/s)
+host_mem_usage 223104 # Number of bytes of host memory used
+host_seconds 5584.84 # Real time elapsed on the host
sim_insts 573341162 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.l2cache.sampled_refs 239478 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.545236 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 204357736000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 7517.812526 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 13543.303660 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.229425 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.413309 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 7517.825600 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 13543.290586 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.229426 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.413308 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 760340 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1079462 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 116 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_misses 108226 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 238282 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 238282 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 4448635000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 4448633000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3706374500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 8155009500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 8155009500 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency 8155007500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 8155007500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 890396 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1079462 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 149 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_miss_rate 0.317627 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.193548 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.193548 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34205.534539 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34205.519161 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 2060.606061 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34246.618188 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34224.194442 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34224.194442 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34224.186048 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34224.186048 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_mshr_misses 238263 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 238263 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4037689500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4037687500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1023000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3355622000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 7393311500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 7393311500 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 7393309500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 7393309500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146044 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.221477 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317627 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.193532 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.193532 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.312603 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.297223 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.691793 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.036137 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.036137 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
projects / gem5.git / commitdiff