config/i386/constraints.md has
(define_register_constraint "Yd"
"TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
Comments for "Yd" should mention AVX512DQ, not AVX512BW.
* config/i386/constraints.md (Yd): Replace AVX512BW with AVX512DQ
in comments
From-SVN: r268759
+2019-02-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/constraints.md (Yd): Replace AVX512BW with AVX512DQ
+ in comments
+
2019-02-10 Chung-Ju Wu <jasonwucj@gmail.com>
* config.gcc (with_nds32_lib): Set default --with-nds32-lib correctly.
;; We use the Y prefix to denote any number of conditional register sets:
;; z First SSE register.
-;; d any EVEX encodable SSE register for AVX512BW target or
+;; d any EVEX encodable SSE register for AVX512DQ target or
;; any SSE register for SSE4_1 target.
;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled
;; a Integer register when zero extensions with AND are disabled