fmuls test showing rounding error against qemu

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index 5e745ef49f17481412ab98704c61e273731ea816..a5e16b6baa13f54162ccb78d8038674265743a2f 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -211,6 +211,21 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
             self.assertEqual(sim.fpr(3), SelectableInt(0xc051266640000000, 64))
 
+    def test_fp_muls2(self):
+        """>>> lst = ["fmuls 3, 1, 2",
+                     ]
+        """
+        lst = ["fmuls 3, 1, 2", # 
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0xbfc4e9d700000000
+        fprs[2] = 0xbdc5000000000000
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            self.assertEqual(sim.fpr(3), SelectableInt(0x3d9b72ea40000000, 64))
+
     def test_fp_mul(self):
         """>>> lst = ["fmul 3, 1, 2",
                      ]