+2011-03-23 Robin Getz <robin.getz@analog.com>
+
+ * bfin-sim.c (decode_dsp32alu_0): Drop the src0/src1 check for
+ BYTEOP1P, BYTEOP2P, and BYTEOP3P insns.
+
2011-03-23 Mike Frysinger <vapier@gentoo.org>
* machs.c (bf50x_dev, bf512_dev, bf516_dev, bf522_dev, bf526_dev,
src0 + 1, src0, src1 + 1, src1, opts[HL + (aop << 1)],
s ? ", r" : "");
- if (src0 == src1)
- illegal_instruction_combination (cpu);
-
s0L = DREG (src0);
s0H = DREG (src0 + 1);
s1L = DREG (src1);
src0 + 1, src0, src1 + 1, src1, HL ? "HI" : "LO",
s ? ", R" : "");
- if (src0 == src1)
- illegal_instruction_combination (cpu);
-
s0L = DREG (src0);
s0H = DREG (src0 + 1);
s1L = DREG (src1);
TRACE_INSN (cpu, "R%i = BYTEOP1P (R%i:%i, R%i:%i)%s;", dst0,
src0 + 1, src0, src1 + 1, src1, opts[s + (aop << 1)]);
- if (src0 == src1)
- illegal_instruction_combination (cpu);
-
s0L = DREG (src0);
s0H = DREG (src0 + 1);
s1L = DREG (src1);