add state information section

diff --git a/isa_conflict_resolution/mvendor_march_warl.mdwn b/isa_conflict_resolution/mvendor_march_warl.mdwn
index 0d75b2c0b573b03d1727d69dcb0abadc616a8555..2cb1ea348b070feaae5afb2d68173b4aaa226a4a 100644 (file)
--- a/isa_conflict_resolution/mvendor_march_warl.mdwn
+++ b/isa_conflict_resolution/mvendor_march_warl.mdwn
@@ -66,6 +66,10 @@ needs discussion, as it would be unfortunate and undesirable for a hybrid
 processor capable of executing more than one hardware-level ISA support
 to not be permitted to receive RISC-V Certification Compliance.
 
+How such foreign architectures would switch back to RISC-V when the foreign
+architecture does not support the concept of mvendorid-marchid is out of
+scope and left to implementors.
+
 ## Implementation
 
 The redirection of meaning of certain binary encodings to multiple