Added module->avail_parameters (for advanced techmap features)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 66b670c7a23e3899f77181f5e4a4a3ab5064d5d8..f7e7b852cc7afa16ac2193ca1dd6506fd3a37517 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -805,7 +805,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
        case AST_TASK:
        case AST_FUNCTION:
        case AST_AUTOWIRE:
-       case AST_PARAMETER:
        case AST_LOCALPARAM:
        case AST_DEFPARAM:
        case AST_GENVAR:
@@ -814,6 +813,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
        case AST_GENIF:
                break;
 
+       // remember the parameter, needed for example in techmap
+       case AST_PARAMETER:
+               current_module->avail_parameters.insert(str);
+               break;
+
        // create an RTLIL::Wire for an AST_WIRE node
        case AST_WIRE: {
                        if (current_module->wires.count(str) != 0)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 4b790cbde1d270ae10b5cfe6ed601870da9e90e9..5873c3694fd6c5f63d8c1b832bd2d33706bfef9a 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -257,6 +257,7 @@ struct RTLIL::Design {
 
 struct RTLIL::Module {
        RTLIL::IdString name;
+       std::set<RTLIL::IdString> avail_parameters;
        std::map<RTLIL::IdString, RTLIL::Wire*> wires;
        std::map<RTLIL::IdString, RTLIL::Memory*> memories;
        std::map<RTLIL::IdString, RTLIL::Cell*> cells;

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 0bef2b62f9f263936ff8a6e15f27f98610306762..bd3d223b60832c814570f2917b4c0b49e80be593 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -223,7 +223,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
                                                continue;
                                        if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
                                                continue;
-                                       if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0)
+                                       if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
                                                goto next_tpl;
                                        parameters[conn.first] = conn.second.as_const();
                                }
@@ -232,6 +232,9 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
                next_tpl:
                                        continue;
                                }
+
+                               if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
+                                       parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
                        }
 
                        std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
@@ -475,7 +478,10 @@ struct TechmapPass : public Pass {
                std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
                for (auto &it : map->modules) {
                        if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").str.empty()) {
-                               celltypeMap[RTLIL::escape_id(it.second->attributes.at("\\techmap_celltype").str)].insert(it.first);
+                               char *p = strdup(it.second->attributes.at("\\techmap_celltype").str.c_str());
+                               for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
+                                       celltypeMap[RTLIL::escape_id(q)].insert(it.first);
+                               free(p);
                        } else
                                celltypeMap[it.first].insert(it.first);
                }