testsuite: aarch64: Add tests for vmull_high intrinsics

Add tests for vmull_high_* Neon intrinsics. Since these intrinsics
are only supported for AArch64, these tests are restricted to only
run on AArch64 targets.

gcc/testsuite/ChangeLog:

2021-01-29  Jonathan Wright  <jonathan.wright@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/vmull_high.c:
	New test.
	* gcc.target/aarch64/advsimd-intrinsics/vmull_high_lane.c:
	New test.
	* gcc.target/aarch64/advsimd-intrinsics/vmull_high_laneq.c:
	New test.
	* gcc.target/aarch64/advsimd-intrinsics/vmull_high_n.c:
	New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high.c
new file mode 100644 (file)
index 0000000..36094fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high.c
@@ -0,0 +1,78 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x40, 0x31,0x24, 0x19,
+                                          0x10, 0x9, 0x4, 0x1 };
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0x90, 0x79, 0x64, 0x51 };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0xc4, 0xa9 };
+VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0xf040, 0xf231, 0xf424, 0xf619,
+                                           0xf810, 0xfa09, 0xfc04, 0xfe01 };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0xffe80090, 0xffea0079,
+                                           0xffec0064, 0xffee0051 };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0xffffffe4000000c4,
+                                           0xffffffe6000000a9 };
+VECT_VAR_DECL(expected, poly, 16, 8) [] = { 0x5540, 0x5541, 0x5544, 0x5545,
+                                           0x5550, 0x5551, 0x5554, 0x5555 };
+
+#define TEST_MSG "VMULL_HIGH"
+void exec_vmull_high (void)
+{
+  /* Basic test: y = vmull_high(x, x), then store the result.  */
+#define TEST_VMULL_HIGH(T1, T2, W1, W2, N1, N2)                                 \
+  VECT_VAR(vector_res, T1, W2, N1) =                                    \
+    vmull_high_##T2##W1(VECT_VAR(vector, T1, W1, N2),                   \
+                       VECT_VAR(vector, T1, W1, N2));                   \
+  vst1q_##T2##W2(VECT_VAR(result, T1, W2, N1),                          \
+                VECT_VAR(vector_res, T1, W2, N1))
+
+  DECL_VARIABLE(vector, int, 8, 16);
+  DECL_VARIABLE(vector, int, 16, 8);
+  DECL_VARIABLE(vector, int, 32, 4);
+  DECL_VARIABLE(vector, uint, 8, 16);
+  DECL_VARIABLE(vector, uint, 16, 8);
+  DECL_VARIABLE(vector, uint, 32, 4);
+  DECL_VARIABLE(vector, poly, 8, 16);
+  DECL_VARIABLE(vector_res, int, 16, 8);
+  DECL_VARIABLE(vector_res, int, 32, 4);
+  DECL_VARIABLE(vector_res, int, 64, 2);
+  DECL_VARIABLE(vector_res, uint, 16, 8);
+  DECL_VARIABLE(vector_res, uint, 32, 4);
+  DECL_VARIABLE(vector_res, uint, 64, 2);
+  DECL_VARIABLE(vector_res, poly, 16, 8);
+
+  clean_results ();
+
+  VLOAD(vector, buffer, q, int, s, 8, 16);
+  VLOAD(vector, buffer, q, int, s, 16, 8);
+  VLOAD(vector, buffer, q, int, s, 32, 4);
+  VLOAD(vector, buffer, q, uint, u, 8, 16);
+  VLOAD(vector, buffer, q, uint, u, 16, 8);
+  VLOAD(vector, buffer, q, uint, u, 32, 4);
+  VLOAD(vector, buffer, q, poly, p, 8, 16);
+
+  TEST_VMULL_HIGH(int, s, 8, 16, 8, 16);
+  TEST_VMULL_HIGH(int, s, 16, 32, 4, 8);
+  TEST_VMULL_HIGH(int, s, 32, 64, 2, 4);
+  TEST_VMULL_HIGH(uint, u, 8, 16, 8, 16);
+  TEST_VMULL_HIGH(uint, u, 16, 32, 4, 8);
+  TEST_VMULL_HIGH(uint, u, 32, 64, 2, 4);
+  TEST_VMULL_HIGH(poly, p, 8, 16, 8, 16);
+
+  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+  CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+  CHECK_POLY(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
+}
+
+int main (void)
+{
+  exec_vmull_high ();
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_lane.c
new file mode 100644 (file)
index 0000000..30bc954
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_lane.c
@@ -0,0 +1,69 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0x4000, 0x4000, 0x4000, 0x4000 };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0x2000, 0x2000 };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0x4000, 0x4000, 0x4000, 0x4000 };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0x2000, 0x2000 };
+
+#define TEST_MSG "VMULL_HIGH_LANE"
+void exec_vmull_high_lane (void)
+{
+  /* vector_res = vmull_high_lane(vector, vector2, lane), store the result. */
+#define TEST_VMULL_HIGH_LANE(T1, T2, W1, W2, N1, N2, L)                          \
+  VECT_VAR(vector_res, T1, W2, N2) =                                     \
+    vmull_high_lane_##T2##W1(VECT_VAR(vector, T1, W1, N1),               \
+                            VECT_VAR(vector2, T1, W1, N2),               \
+                            L);                                          \
+  vst1q_##T2##W2(VECT_VAR(result, T1, W2, N2),                           \
+                VECT_VAR(vector_res, T1, W2, N2))
+
+  DECL_VARIABLE(vector, int, 16, 8);
+  DECL_VARIABLE(vector, int, 32, 4);
+  DECL_VARIABLE(vector, uint, 16, 8);
+  DECL_VARIABLE(vector, uint, 32, 4);
+  DECL_VARIABLE(vector2, int, 16, 4);
+  DECL_VARIABLE(vector2, int, 32, 2);
+  DECL_VARIABLE(vector2, uint, 16, 4);
+  DECL_VARIABLE(vector2, uint, 32, 2);
+
+  DECL_VARIABLE(vector_res, int, 32, 4);
+  DECL_VARIABLE(vector_res, int, 64, 2);
+  DECL_VARIABLE(vector_res, uint, 32, 4);
+  DECL_VARIABLE(vector_res, uint, 64, 2);
+
+  clean_results ();
+
+  /* Initialize vector.  */
+  VDUP(vector, q, int, s, 16, 8, 0x1000);
+  VDUP(vector, q, int, s, 32, 4, 0x1000);
+  VDUP(vector, q, uint, u, 16, 8, 0x1000);
+  VDUP(vector, q, uint, u, 32, 4, 0x1000);
+
+  /* Initialize vector2.  */
+  VDUP(vector2, , int, s, 16, 4, 0x4);
+  VDUP(vector2, , int, s, 32, 2, 0x2);
+  VDUP(vector2, , uint, u, 16, 4, 0x4);
+  VDUP(vector2, , uint, u, 32, 2, 0x2);
+
+  /* Choose lane arbitrarily.  */
+  TEST_VMULL_HIGH_LANE(int, s, 16, 32, 8, 4, 2);
+  TEST_VMULL_HIGH_LANE(int, s, 32, 64, 4, 2, 1);
+  TEST_VMULL_HIGH_LANE(uint, u, 16, 32, 8, 4, 2);
+  TEST_VMULL_HIGH_LANE(uint, u, 32, 64, 4, 2, 1);
+
+  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+  CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+  exec_vmull_high_lane ();
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_laneq.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_laneq.c
new file mode 100644 (file)
index 0000000..191ade5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_laneq.c
@@ -0,0 +1,69 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0x4000, 0x4000, 0x4000, 0x4000 };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0x2000, 0x2000 };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0x4000, 0x4000, 0x4000, 0x4000 };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0x2000, 0x2000 };
+
+#define TEST_MSG "VMULL_HIGH_LANEQ"
+void exec_vmull_high_laneq (void)
+{
+  /* vector_res = vmull_high_laneq(vector, vector2, lane), store the result. */
+#define TEST_VMULL_HIGH_LANEQ(T1, T2, W1, W2, N1, N2, L)                 \
+  VECT_VAR(vector_res, T1, W2, N2) =                                     \
+    vmull_high_laneq_##T2##W1(VECT_VAR(vector, T1, W1, N1),              \
+                             VECT_VAR(vector2, T1, W1, N1),              \
+                             L);                                         \
+  vst1q_##T2##W2(VECT_VAR(result, T1, W2, N2),                           \
+                VECT_VAR(vector_res, T1, W2, N2))
+
+  DECL_VARIABLE(vector, int, 16, 8);
+  DECL_VARIABLE(vector, int, 32, 4);
+  DECL_VARIABLE(vector, uint, 16, 8);
+  DECL_VARIABLE(vector, uint, 32, 4);
+  DECL_VARIABLE(vector2, int, 16, 8);
+  DECL_VARIABLE(vector2, int, 32, 4);
+  DECL_VARIABLE(vector2, uint, 16, 8);
+  DECL_VARIABLE(vector2, uint, 32, 4);
+
+  DECL_VARIABLE(vector_res, int, 32, 4);
+  DECL_VARIABLE(vector_res, int, 64, 2);
+  DECL_VARIABLE(vector_res, uint, 32, 4);
+  DECL_VARIABLE(vector_res, uint, 64, 2);
+
+  clean_results ();
+
+  /* Initialize vector.  */
+  VDUP(vector, q, int, s, 16, 8, 0x1000);
+  VDUP(vector, q, int, s, 32, 4, 0x1000);
+  VDUP(vector, q, uint, u, 16, 8, 0x1000);
+  VDUP(vector, q, uint, u, 32, 4, 0x1000);
+
+  /* Initialize vector2.  */
+  VDUP(vector2, q, int, s, 16, 8, 0x4);
+  VDUP(vector2, q, int, s, 32, 4, 0x2);
+  VDUP(vector2, q, uint, u, 16, 8, 0x4);
+  VDUP(vector2, q, uint, u, 32, 4, 0x2);
+
+  /* Choose lane arbitrarily.  */
+  TEST_VMULL_HIGH_LANEQ(int, s, 16, 32, 8, 4, 5);
+  TEST_VMULL_HIGH_LANEQ(int, s, 32, 64, 4, 2, 1);
+  TEST_VMULL_HIGH_LANEQ(uint, u, 16, 32, 8, 4, 7);
+  TEST_VMULL_HIGH_LANEQ(uint, u, 32, 64, 4, 2, 3);
+
+  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+  CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+  exec_vmull_high_laneq ();
+  return 0;
+}

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_n.c
new file mode 100644 (file)
index 0000000..892cca1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_n.c
@@ -0,0 +1,61 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0x11000, 0x11000,
+                                          0x11000, 0x11000 };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0x22000, 0x22000 };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0x33000, 0x33000,
+                                           0x33000, 0x33000 };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0x44000, 0x44000 };
+
+#define TEST_MSG "VMULL_HIGH_N"
+void exec_vmull_high_n (void)
+{
+  int i;
+
+  /* vector_res = vmull_high_n(vector, val), then store the result.  */
+#define TEST_VMULL_HIGH_N(T1, T2, W1, W2, N1, N2, L)                     \
+  VECT_VAR(vector_res, T1, W2, N2) =                                     \
+    vmull_high_n_##T2##W1(VECT_VAR(vector, T1, W1, N1), L);              \
+  vst1q_##T2##W2(VECT_VAR(result, T1, W2, N2),                           \
+                VECT_VAR(vector_res, T1, W2, N2))
+
+  DECL_VARIABLE(vector, int, 16, 8);
+  DECL_VARIABLE(vector, int, 32, 4);
+  DECL_VARIABLE(vector, uint, 16, 8);
+  DECL_VARIABLE(vector, uint, 32, 4);
+
+  DECL_VARIABLE(vector_res, int, 32, 4);
+  DECL_VARIABLE(vector_res, int, 64, 2);
+  DECL_VARIABLE(vector_res, uint, 32, 4);
+  DECL_VARIABLE(vector_res, uint, 64, 2);
+
+  clean_results ();
+
+  /* Initialize vector.  */
+  VDUP(vector, q, int, s, 16, 8, 0x1000);
+  VDUP(vector, q, int, s, 32, 4, 0x1000);
+  VDUP(vector, q, uint, u, 16, 8, 0x1000);
+  VDUP(vector, q, uint, u, 32, 4, 0x1000);
+
+  /* Choose multiplier arbitrarily.  */
+  TEST_VMULL_HIGH_N(int, s, 16, 32, 8, 4, 0x11);
+  TEST_VMULL_HIGH_N(int, s, 32, 64, 4, 2, 0x22);
+  TEST_VMULL_HIGH_N(uint, u, 16, 32, 8, 4, 0x33);
+  TEST_VMULL_HIGH_N(uint, u, 32, 64, 4, 2, 0x44);
+
+  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+  CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+  exec_vmull_high_n ();
+  return 0;
+}