Fix mul2dsp signedness

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index d195996202c6df5cdfa78925e631c696acbf8343..7344bc5fefe1f2017c3e90cc91dfc0c608c46a4d 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -34,49 +34,45 @@ module \$mul (A, B, Y);
        output [Y_WIDTH-1:0] Y;\r
 \r
        generate\r
-        localparam add_sign_A = `DSP_A_SIGNEDONLY && !A_SIGNED;\r
-        localparam add_sign_B = `DSP_B_SIGNEDONLY && !B_SIGNED;\r
-        if (add_sign_A || add_sign_B) begin\r
-            if (add_sign_A && add_sign_B)\r
-                wire [1:0] dummy;\r
-            else\r
-                wire dummy;\r
-                       \$mul #(\r
-                               .A_SIGNED(1),\r
-                               .B_SIGNED(1),\r
-                               .A_WIDTH(A_WIDTH + (add_sign_A ? 1 : 0)),\r
-                               .B_WIDTH(B_WIDTH + (add_sign_B ? 1 : 0)),\r
-                               .Y_WIDTH(Y_WIDTH + (add_sign_A ? 1 : 0) + (add_sign_B ? 1 : 0))\r
-                       ) _TECHMAP_REPLACE_ (\r
-                               .A(add_sign_A ? {1'b0, A} : A),\r
-                               .B(add_sign_B ? {1'b0, B} : B),\r
-                               .Y({dummy, Y})\r
-                       );\r
+        if (`DSP_A_SIGNEDONLY && `DSP_B_SIGNEDONLY && !A_SIGNED) begin\r
+               wire [1:0] dummy;\r
+               \$mul #(\r
+                       .A_SIGNED(1),\r
+                       .B_SIGNED(1),\r
+                       .A_WIDTH(A_WIDTH + 1),\r
+                       .B_WIDTH(B_WIDTH + 1),\r
+                       .Y_WIDTH(Y_WIDTH + 2)\r
+               ) _TECHMAP_REPLACE_ (\r
+                       .A({1'b0, A}),\r
+                       .B({1'b0, B}),\r
+                       .Y({dummy, Y})\r
+               );\r
         end\r
-               else if (A_WIDTH >= B_WIDTH)\r
-                       \$__mul_gen #(\r
-                               .A_SIGNED(A_SIGNED),\r
-                               .B_SIGNED(B_SIGNED),\r
-                               .A_WIDTH(A_WIDTH),\r
-                               .B_WIDTH(B_WIDTH),\r
-                               .Y_WIDTH(Y_WIDTH)\r
-                       ) _TECHMAP_REPLACE_ (\r
-                               .A(A),\r
-                               .B(B),\r
-                               .Y(Y)\r
-                       );\r
-               else\r
-                       \$__mul_gen #(\r
-                               .A_SIGNED(B_SIGNED),\r
-                               .B_SIGNED(A_SIGNED),\r
-                               .A_WIDTH(B_WIDTH),\r
-                               .B_WIDTH(A_WIDTH),\r
-                               .Y_WIDTH(Y_WIDTH)\r
-                       ) _TECHMAP_REPLACE_ (\r
-                               .A(B),\r
-                               .B(A),\r
-                               .Y(Y)\r
-                       );\r
+       // NB: A_SIGNED == B_SIGNED == 0 from here\r
+       else if (A_WIDTH >= B_WIDTH)\r
+               \$__mul_gen #(\r
+                       .A_SIGNED(A_SIGNED),\r
+                       .B_SIGNED(B_SIGNED),\r
+                       .A_WIDTH(A_WIDTH),\r
+                       .B_WIDTH(B_WIDTH),\r
+                       .Y_WIDTH(Y_WIDTH)\r
+               ) _TECHMAP_REPLACE_ (\r
+                       .A(A),\r
+                       .B(B),\r
+                       .Y(Y)\r
+               );\r
+       else\r
+               \$__mul_gen #(\r
+                       .A_SIGNED(B_SIGNED),\r
+                       .B_SIGNED(A_SIGNED),\r
+                       .A_WIDTH(B_WIDTH),\r
+                       .B_WIDTH(A_WIDTH),\r
+                       .Y_WIDTH(Y_WIDTH)\r
+               ) _TECHMAP_REPLACE_ (\r
+                       .A(B),\r
+                       .B(A),\r
+                       .Y(Y)\r
+               );\r
        endgenerate\r
 endmodule\r
 \r