self.slave = dfi.Interface(a, ba, d, nphases)
self.master = dfi.Interface(a, ba, d, nphases)
- self._control = CSRStorage(2) # sel, cke
+ self._control = CSRStorage(4) # sel, cke, odt, reset_n
for n, phase in enumerate(inti.phases):
setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
inti.connect(self.master)
)
self.comb += [phase.cke.eq(self._control.storage[1]) for phase in inti.phases]
+ self.comb += [phase.odt.eq(self._control.storage[2]) for phase in inti.phases if hasattr(phase, "odt")]
+ self.comb += [phase.reset_n.eq(self._control.storage[3]) for phase in inti.phases if hasattr(phase, "reset_n")]
#define UART_EV_TX 0x1
#define UART_EV_RX 0x2
-#define DFII_CONTROL_SEL 0x01
-#define DFII_CONTROL_CKE 0x02
+#define DFII_CONTROL_SEL 0x01
+#define DFII_CONTROL_CKE 0x02
+#define DFII_CONTROL_ODT 0x04
+#define DFII_CONTROL_RESET_N 0x08
#define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02