# use this inside the HDL (where everything is little-endian)
MSR = _ConstLE("MSR", names=MSRb, msb=63)
+# default MSR value for unit tests, since 0 isn't a good default
+DEFAULT_MSR = sum(1 << i for i in (
+ MSR.SF, MSR.HV, MSR.FP, MSR.FE0, MSR.FE1, MSR.RI, MSR.LE))
# Listed in V3.0B Book III 7.5.9 "Program Interrupt"
if __name__ == '__main__':
- print ("EXTRA2 pack", EXTRA2.PACK_en, EXTRA2.PACK_en.value)
+ print("EXTRA2 pack", EXTRA2.PACK_en, EXTRA2.PACK_en.value)
+ for field in MSR:
+ if DEFAULT_MSR & (1 << field.value):
+ print(field)
from openpower.decoder.power_enums import XER_bits, CryIn, spr_dict
from openpower.util import LogKind, log, \
fast_reg_to_spr, slow_reg_to_spr # HACK!
-from openpower.consts import XERRegsEnum
+from openpower.consts import XERRegsEnum, DEFAULT_MSR
# TODO: make this a util routine (somewhere)
self.__subtest_args = old_subtest_args
def add_case(self, prog, initial_regs=None, initial_sprs=None,
- initial_cr=0, initial_msr=0,
+ initial_cr=0, initial_msr=DEFAULT_MSR,
initial_mem=None,
initial_svstate=0,
expected=None,