Add "write_edif -attrprop"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 5f9ec54fdb4e0c52f299f2699874bc5b26f687bb..d4e56a9eb07c43abfb3ef9b1b0ac1d77343ce344 100644 (file)
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -106,6 +106,9 @@ struct EdifBackend : public Backend {
                log("        if the design contains constant nets. use \"hilomap\" to map to custom\n");
                log("        constant drivers first)\n");
                log("\n");
+               log("    -attrprop\n");
+               log("        create EDIF properties for cell attributes\n");
+               log("\n");
                log("    -pvector {par|bra|ang}\n");
                log("        sets the delimiting character for module port rename clauses to\n");
                log("        parentheses, square brackets, or angle brackets.\n");
@@ -121,6 +124,7 @@ struct EdifBackend : public Backend {
                log_header(design, "Executing EDIF backend.\n");
                std::string top_module_name;
                bool port_rename = false;
+               bool attr_properties = false;
                std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
                bool nogndvcc = false;
                CellTypes ct(design);
@@ -137,6 +141,10 @@ struct EdifBackend : public Backend {
                                nogndvcc = true;
                                continue;
                        }
+                       if (args[argidx] == "-attrprop") {
+                               attr_properties = true;
+                               continue;
+                       }
                        if (args[argidx] == "-pvector" && argidx+1 < args.size()) {
                                std::string parray;
                                port_rename = true;
@@ -332,24 +340,33 @@ struct EdifBackend : public Backend {
                                *f << stringf("          (instance %s\n", EDIF_DEF(cell->name));
                                *f << stringf("            (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
                                                lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
-                               for (auto &p : cell->parameters)
-                                       if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
-                                               *f << stringf("\n            (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
-                                       else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
-                                               *f << stringf("\n            (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
+
+                               auto add_prop = [&](IdString name, Const val) {
+                                       if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
+                                               *f << stringf("\n            (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
+                                       else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
+                                               *f << stringf("\n            (property %s (integer %u))", EDIF_DEF(name), val.as_int());
                                        else {
                                                std::string hex_string = "";
-                                               for (size_t i = 0; i < p.second.bits.size(); i += 4) {
+                                               for (size_t i = 0; i < val.bits.size(); i += 4) {
                                                        int digit_value = 0;
-                                                       if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
-                                                       if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
-                                                       if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
-                                                       if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
+                                                       if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
+                                                       if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
+                                                       if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
+                                                       if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
                                                        char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
                                                        hex_string = std::string(digit_str) + hex_string;
                                                }
-                                               *f << stringf("\n            (property %s (string \"%d'h%s\"))", EDIF_DEF(p.first), GetSize(p.second.bits), hex_string.c_str());
+                                               *f << stringf("\n            (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
                                        }
+                               };
+
+                               for (auto &p : cell->parameters)
+                                       add_prop(p.first, p.second);
+                               if (attr_properties)
+                                       for (auto &p : cell->attributes)
+                                               add_prop(p.first, p.second);
+
                                *f << stringf(")\n");
                                for (auto &p : cell->connections()) {
                                        RTLIL::SigSpec sig = sigmap(p.second);