(no commit message)

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 2d834fe478d49303ab7c6931a8e0a129395f2109..5096baad83c9b6cd276c38182826cde2ee85dd62 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -79,7 +79,7 @@ The principle of SV is as follows:
   bit format (single instruction option) or a variable
  length VLIW-like prefix (multi or "grouped" option).
 * The prefix(es) indicate which registers are "tagged" as
-  "vectorised". Predicates can also be added.
+  "vectorised". Predicates can also be added, and element widths overridden on any src or dest register.
 * A "Vector Length" CSR is set, indicating the span of any future
   "parallel" operations.
 * If any operation (a **scalar** standard RV opcode) uses a register