Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions, vis...

	PR 22179
opcodes	* riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
	names for the fmv.x.s and fmv.s.x instructions respectively.

gas	* testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the
	renamed fmv.x.s and fmv.s.x instructions.
	* testsuite/gas/riscv/fmv.x.d: New file: Test driver.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8554dd5c86bc09a4d5e93adfa98a56645b980d10..acf75a9b4961f91b010f192715942c1c969ba5ed 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2017-09-27  Nick Clifton  <nickc@redhat.com>
+
+       PR 22179
+       * testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the
+       renamed fmv.x.s and fmv.s.x instructions.
+       * testsuite/gas/riscv/fmv.x.d: New file: Test driver.
+
 2017-09-21  Maciej W. Rozycki  <macro@imgtec.com>
 
        * testsuite/gas/mips/elf_mach_5900.d: New test.

diff --git a/gas/testsuite/gas/riscv/fmv.x.d b/gas/testsuite/gas/riscv/fmv.x.d
new file mode 100644 (file)
index 0000000..7392e0c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fmv.x.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[      ]+0:[   ]+e00b8653[     ]+fmv.x.w[      ]+a2,fs7
+[      ]+4:[   ]+e00b8653[     ]+fmv.x.w[      ]+a2,fs7
+[      ]+8:[   ]+f00800d3[     ]+fmv.w.x[      ]+ft1,a6
+[      ]+c:[   ]+f00800d3[     ]+fmv.w.x[      ]+ft1,a6

diff --git a/gas/testsuite/gas/riscv/fmv.x.s b/gas/testsuite/gas/riscv/fmv.x.s
new file mode 100644 (file)
index 0000000..a16feda
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fmv.x.s
@@ -0,0 +1,4 @@
+fmv.x.w a2, fs7
+fmv.x.s a2, fs7
+fmv.w.x ft1, a6
+fmv.s.x ft1, a6

diff --git a/gas/testsuite/gas/riscv/riscv.exp b/gas/testsuite/gas/riscv/riscv.exp
index 6922318ac0fcaf9204173a1b8237a5fb3233f8ee..005238f9a3868f774995f5c6aaedbf5d3eb730ff 100644 (file)
--- a/gas/testsuite/gas/riscv/riscv.exp
+++ b/gas/testsuite/gas/riscv/riscv.exp
@@ -20,4 +20,5 @@
 
 if [istarget riscv*-*-*] {
     run_dump_test "t_insns"
+    run_dump_test "fmv.x"
 }

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e8061b34353d1622465775315976c2c057318c15..9280b2ce846f0ae9b0eff2635ea0bfe0f8073150 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2017-09-27  Nick Clifton  <nickc@redhat.com>
+
+       PR 22179
+       * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
+       names for the fmv.x.s and fmv.s.x instructions respectively.
+
 2017-09-26  do  <do@nerilex.org>
 
        PR 22123

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 70a362859ccc4bff28dd76148d2404e2e105bf85..27b4b9fb513c8e642971fe6252bee9285a41d7d3 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -435,8 +435,13 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fsw",       "32C", "CD,Ck(Cs)",  MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS },
 {"fsw",       "F",   "T,q(s)",  MATCH_FSW, MASK_FSW, match_opcode, 0 },
 {"fsw",       "F",   "T,A,s",  0, (int) M_FSW, match_never, INSN_MACRO },
+
+{"fmv.x.w",   "F",   "d,S",  MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
+{"fmv.w.x",   "F",   "D,s",  MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
+
 {"fmv.x.s",   "F",   "d,S",  MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
 {"fmv.s.x",   "F",   "D,s",  MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
+
 {"fmv.s",     "F",   "D,U",  MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
 {"fneg.s",    "F",   "D,U",  MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
 {"fabs.s",    "F",   "D,U",  MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },