gallium/radeon: add barrier_flags to r600_common_screen
authorNicolai Hähnle <nicolai.haehnle@amd.com>
Thu, 15 Sep 2016 14:24:17 +0000 (16:24 +0200)
committerNicolai Hähnle <nicolai.haehnle@amd.com>
Thu, 29 Sep 2016 09:14:11 +0000 (11:14 +0200)
There are driver-specific context flags for barriers that are not covered
by the Gallium barrier interfaces.

The R600 settings of these flags may not be optimal, but we're not going
to use them yet anyway.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/radeon/r600_pipe_common.h
src/gallium/drivers/radeonsi/si_pipe.c

index 271b7e1089e1dde7c1611c963c10d095be7f8fc8..635b76fd380a853593b9c4939b1a95708c065b60 100644 (file)
@@ -680,6 +680,12 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
        rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
                              !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 
+       rscreen->b.barrier_flags.cp_to_L2 =
+               R600_CONTEXT_INV_VERTEX_CACHE |
+               R600_CONTEXT_INV_TEX_CACHE |
+               R600_CONTEXT_INV_CONST_CACHE;
+       rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_PS_PARTIAL_FLUSH;
+
        rscreen->global_pool = compute_memory_pool_new(rscreen);
 
        /* Create the auxiliary context. This must be done last. */
index d9f22e49889a1da5695a5b649e527765288c3190..dd33eabcbff04f5307a9610423e2a67e1ded0bc8 100644 (file)
@@ -415,6 +415,18 @@ struct r600_common_screen {
         */
        unsigned                        dirty_tex_descriptor_counter;
 
+       struct {
+               /* Context flags to set so that all writes from earlier jobs
+                * in the CP are seen by L2 clients.
+                */
+               unsigned cp_to_L2;
+
+               /* Context flags to set so that all writes from earlier
+                * compute jobs are seen by L2 clients.
+                */
+               unsigned compute_to_L2;
+       } barrier_flags;
+
        void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
                                      struct r600_texture *rtex,
                                      struct radeon_bo_metadata *md);
index 8f9e6f5caa2409e64bde4b3cb8b13e625c7462f1..730be9d55da2a4fcf967b7cce452f13b45fdd1a8 100644 (file)
@@ -818,6 +818,11 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
                HAVE_LLVM < 0x0308 ||
                (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 
+       sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
+                                           SI_CONTEXT_INV_VMEM_L1 |
+                                           SI_CONTEXT_INV_GLOBAL_L2;
+       sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
+
        if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
                sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;