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diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 13faceb48bfb0b1e456b109a72cff6e62c45a2d6..ccb40ffb67b2103e489b8b24d9d9a83b0739c54d 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -99,7 +99,7 @@ Some examples on different operation widths:
 
 Mode types:
 
-* **sz dz predicate zeroing**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.
+* **sz dz predicate zeroing**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
 * **ffirst** or data-dependent fail-on-first: see separate section.
 * **sat mode** or saturation: clamps the result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping.
 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero.  When Rc=1 the CR element (CR0) however is still stored in the CR regfile.  This scheme does not apply to crops (crand, cror).