static bool
insn_validate (const struct powerpc_opcode *op)
{
- const unsigned char *o;
+ const ppc_opindex_t *o;
uint64_t omask = op->mask;
/* The mask had better not trim off opcode bits. */
unsigned int i;
/* An index into powerpc_operands is stored in struct fix
- fx_pcrel_adjust which is 8 bits wide. */
- gas_assert (num_powerpc_operands < 256);
+ fx_pcrel_adjust which is a 16 bit field. */
+ gas_assert (num_powerpc_operands <= PPC_OPINDEX_MAX + 1);
/* Check operand masks. Code here and in the disassembler assumes
all the 1's in the mask are contiguous. */
char *s;
const struct powerpc_opcode *opcode;
uint64_t insn;
- const unsigned char *opindex_ptr;
+ const ppc_opindex_t *opindex_ptr;
int need_paren;
int next_opindex;
struct ppc_fixup fixups[MAX_INSN_FIXUPS];
{
if (num_optional_operands == 0)
{
- const unsigned char *optr;
+ const ppc_opindex_t *optr;
int total = 0;
int provided = 0;
int omitted;
if (fixP->fx_pcrel_adjust != 0)
{
/* This is a fixup on an instruction. */
- int opindex = fixP->fx_pcrel_adjust & 0xff;
+ ppc_opindex_t opindex = fixP->fx_pcrel_adjust & PPC_OPINDEX_MAX;
operand = &powerpc_operands[opindex];
#ifdef OBJ_XCOFF
/* These small fields are grouped together for compactness of
this structure, and efficiency of access on some architectures. */
+ /* pc-relative offset adjust (only used by some CPU specific code).
+ A 4-bit field would be sufficient for most uses, except for ppc
+ which pokes an operand table index here. Bits may be stolen
+ from here should that be necessary, provided PPC_OPINDEX_MAX is
+ adjusted suitably. */
+ int fx_pcrel_adjust : 16;
+
+ /* How many bytes are involved? */
+ unsigned fx_size : 8;
+
/* Is this a pc-relative relocation? */
unsigned fx_pcrel : 1;
unsigned fx_tcbit2 : 1;
/* Spare bits. */
- unsigned fx_unused : 10;
-
- /* pc-relative offset adjust (only used by some CPU specific code) */
- int fx_pcrel_adjust : 8;
-
- /* How many bytes are involved? */
- unsigned fx_size : 8;
+ unsigned fx_unused : 2;
bfd_reloc_code_real_type fx_r_type;
#endif
typedef uint64_t ppc_cpu_t;
+typedef uint16_t ppc_opindex_t;
+
+/* Smaller of ppc_opindex_t and fx_pcrel_adjust maximum. Note that
+ values extracted from fx_pcrel_adjust are masked with this constant,
+ effectively making the field unsigned. */
+#define PPC_OPINDEX_MAX 0xffff
/* The opcode table is an array of struct powerpc_opcode. */
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
- unsigned char operands[8];
+ ppc_opindex_t operands[8];
};
/* The table itself is sorted by major opcode number, and is otherwise
/* Determine whether the optional operand(s) should be printed. */
static bool
-skip_optional_operands (const unsigned char *opindex,
+skip_optional_operands (const ppc_opindex_t *opindex,
uint64_t insn, ppc_cpu_t dialect, bool *is_pcrel)
{
const struct powerpc_operand *operand;
opcode < opcode_end;
++opcode)
{
- const unsigned char *opindex;
+ const ppc_opindex_t *opindex;
const struct powerpc_operand *operand;
int invalid;
opcode < opcode_end;
++opcode)
{
- const unsigned char *opindex;
+ const ppc_opindex_t *opindex;
const struct powerpc_operand *operand;
int invalid;
uint64_t table_mask = opcode->mask;
bool table_op_is_short = PPC_OP_SE_VLE(table_mask);
uint64_t insn2;
- const unsigned char *opindex;
+ const ppc_opindex_t *opindex;
const struct powerpc_operand *operand;
int invalid;
uint64_t table_opcd = opcode->opcode;
uint64_t table_mask = opcode->mask;
uint64_t insn2;
- const unsigned char *opindex;
+ const ppc_opindex_t *opindex;
const struct powerpc_operand *operand;
int invalid;
if (opcode != NULL)
{
- const unsigned char *opindex;
+ const ppc_opindex_t *opindex;
const struct powerpc_operand *operand;
enum {
need_comma = 0,