+2018-02-16 Carl Love <cel@us.ibm.com>
+
+ * config/rs6000/altivec.h: Remove vec_vextract4b and vec_vinsert4b.
+ * config/rs6000/rs6000-builtin.def: Remove macro expansion for
+ VEXTRACT4B, VINSERT4B, VINSERT4B_DI and VEXTRACT4B.
+ * config/rs6000/rs6000.c: Remove case statements for
+ P9V_BUILTIN_VEXTRACT4B, P9V_BUILTIN_VEC_VEXTRACT4B,
+ P9V_BUILTIN_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
+ and P9V_BUILTIN_VEC_VINSERT4B.
+ * config/rs6000/rs6000-c.c (altivec_expand_builtin): Remove entries for
+ P9V_BUILTIN_VEC_VEXTRACT4B and P9V_BUILTIN_VEC_VINSERT4B.
+ * config/rs6000/vsx.md:
+ * doc/extend.texi: Remove vec_vextract4b, non ABI definitions for
+ vec_insert4b.
+
2018-02-16 Carl Love <cel@us.ibm.com>
* config/rs6000/altivec.h: Add builtin names vec_extract4b
#define vec_vctzd __builtin_vec_vctzd
#define vec_vctzh __builtin_vec_vctzh
#define vec_vctzw __builtin_vec_vctzw
-#define vec_vextract4b __builtin_vec_vextract4b
-#define vec_vinsert4b __builtin_vec_vinsert4b
#define vec_extract4b __builtin_vec_extract4b
#define vec_insert4b __builtin_vec_insert4b
#define vec_vprtyb __builtin_vec_vprtyb
BU_P9V_AV_2 (VEXTUWRX, "vextuwrx", CONST, vextuwrx)
/* Insert/extract 4 byte word into a vector. */
-BU_P9V_VSX_2 (VEXTRACT4B, "vextract4b", CONST, vextract4b)
-BU_P9V_VSX_3 (VINSERT4B, "vinsert4b", CONST, vinsert4b)
-BU_P9V_VSX_3 (VINSERT4B_DI, "vinsert4b_di", CONST, vinsert4b_di)
BU_P9V_VSX_3 (INSERT4B, "insert4b", CONST, insert4b)
BU_P9V_VSX_2 (EXTRACT4B, "extract4b", CONST, extract4b)
BU_P9V_OVERLOAD_2 (XL_LEN_R, "xl_len_r")
BU_P9V_OVERLOAD_2 (VEXTULX, "vextulx")
BU_P9V_OVERLOAD_2 (VEXTURX, "vexturx")
-BU_P9V_OVERLOAD_2 (VEXTRACT4B, "vextract4b")
BU_P9V_OVERLOAD_2 (EXTRACT4B, "extract4b")
/* ISA 3.0 Vector scalar overloaded 3 argument functions */
BU_P9V_OVERLOAD_3 (STXVL, "stxvl")
BU_P9V_OVERLOAD_3 (XST_LEN_R, "xst_len_r")
-BU_P9V_OVERLOAD_3 (VINSERT4B, "vinsert4b")
BU_P9V_OVERLOAD_3 (INSERT4B, "insert4b")
/* Overloaded CMPNE support was implemented prior to Power 9,
{ P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI,
RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 },
- { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B,
- RS6000_BTI_INTDI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
- { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B,
- RS6000_BTI_INTDI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI, 0 },
{ P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
{ P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI },
- { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
- RS6000_BTI_V16QI, RS6000_BTI_V4SI,
- RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
- { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
- RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI,
- RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
- { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
- { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
- RS6000_BTI_V16QI, RS6000_BTI_INTDI,
- RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
- { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
- RS6000_BTI_V16QI, RS6000_BTI_UINTDI,
- RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
- { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTDI,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
- { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI,
- RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
{ P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
case VSX_BUILTIN_VEC_EXT_V1TI:
return altivec_expand_vec_ext_builtin (exp, target);
- case P9V_BUILTIN_VEXTRACT4B:
- case P9V_BUILTIN_VEC_VEXTRACT4B:
case P9V_BUILTIN_VEC_EXTRACT4B:
arg1 = CALL_EXPR_ARG (exp, 1);
STRIP_NOPS (arg1);
}
break;
- case P9V_BUILTIN_VINSERT4B:
- case P9V_BUILTIN_VINSERT4B_DI:
- case P9V_BUILTIN_VEC_VINSERT4B:
case P9V_BUILTIN_VEC_INSERT4B:
arg2 = CALL_EXPR_ARG (exp, 2);
STRIP_NOPS (arg2);
"xxinsertw %x0,%x1,%3"
[(set_attr "type" "vecperm")])
-(define_expand "vextract4b"
- [(set (match_operand:DI 0 "gpc_reg_operand")
- (unspec:DI [(match_operand:V16QI 1 "vsx_register_operand")
- (match_operand:QI 2 "const_0_to_12_operand")]
- UNSPEC_XXEXTRACTUW))]
- "TARGET_P9_VECTOR"
-{
- if (!VECTOR_ELT_ORDER_BIG)
- operands[2] = GEN_INT (12 - INTVAL (operands[2]));
-})
-
-(define_insn_and_split "*vextract4b_internal"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=wj,r")
- (unspec:DI [(match_operand:V16QI 1 "vsx_register_operand" "wa,v")
- (match_operand:QI 2 "const_0_to_12_operand" "n,n")]
- UNSPEC_XXEXTRACTUW))]
- "TARGET_P9_VECTOR"
- "@
- xxextractuw %x0,%x1,%2
- #"
- "&& reload_completed && int_reg_operand (operands[0], DImode)"
- [(const_int 0)]
-{
- rtx op0 = operands[0];
- rtx op1 = operands[1];
- rtx op2 = operands[2];
- rtx op0_si = gen_rtx_REG (SImode, REGNO (op0));
- rtx op1_v4si = gen_rtx_REG (V4SImode, REGNO (op1));
-
- emit_move_insn (op0, op2);
- if (VECTOR_ELT_ORDER_BIG)
- emit_insn (gen_vextuwlx (op0_si, op0_si, op1_v4si));
- else
- emit_insn (gen_vextuwrx (op0_si, op0_si, op1_v4si));
- DONE;
-}
- [(set_attr "type" "vecperm")])
-
-(define_expand "vinsert4b"
- [(set (match_operand:V16QI 0 "vsx_register_operand")
- (unspec:V16QI [(match_operand:V4SI 1 "vsx_register_operand")
- (match_operand:V16QI 2 "vsx_register_operand")
- (match_operand:QI 3 "const_0_to_12_operand")]
- UNSPEC_XXINSERTW))]
- "TARGET_P9_VECTOR"
-{
- if (!VECTOR_ELT_ORDER_BIG)
- {
- rtx op1 = operands[1];
- rtx v4si_tmp = gen_reg_rtx (V4SImode);
- emit_insn (gen_vsx_xxpermdi_v4si_be (v4si_tmp, op1, op1, const1_rtx));
- operands[1] = v4si_tmp;
- operands[3] = GEN_INT (12 - INTVAL (operands[3]));
- }
-})
-
-(define_insn "*vinsert4b_internal"
- [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
- (unspec:V16QI [(match_operand:V4SI 1 "vsx_register_operand" "wa")
- (match_operand:V16QI 2 "vsx_register_operand" "0")
- (match_operand:QI 3 "const_0_to_12_operand" "n")]
- UNSPEC_XXINSERTW))]
- "TARGET_P9_VECTOR"
- "xxinsertw %x0,%x1,%3"
- [(set_attr "type" "vecperm")])
-
-(define_expand "vinsert4b_di"
- [(set (match_operand:V16QI 0 "vsx_register_operand")
- (unspec:V16QI [(match_operand:DI 1 "vsx_register_operand")
- (match_operand:V16QI 2 "vsx_register_operand")
- (match_operand:QI 3 "const_0_to_12_operand")]
- UNSPEC_XXINSERTW))]
- "TARGET_P9_VECTOR"
-{
- if (!VECTOR_ELT_ORDER_BIG)
- operands[3] = GEN_INT (12 - INTVAL (operands[3]));
-})
-
-(define_insn "*vinsert4b_di_internal"
- [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
- (unspec:V16QI [(match_operand:DI 1 "vsx_register_operand" "wj")
- (match_operand:V16QI 2 "vsx_register_operand" "0")
- (match_operand:QI 3 "const_0_to_12_operand" "n")]
- UNSPEC_XXINSERTW))]
- "TARGET_P9_VECTOR"
- "xxinsertw %x0,%x1,%3"
- [(set_attr "type" "vecperm")])
;; Generate vector extract four float 32 values from left four elements
;; of eight element vector of float 16 values.
vector int vec_vctzw (vector int);
vector unsigned int vec_vctzw (vector int);
-long long vec_vextract4b (const vector signed char, const int);
-vector unsigned long long vec_extract4b (vector unsigned char,
- const int);
-long long vec_extract4b (const vector signed char, const int);
-long long vec_vextract4b (const vector unsigned char, const int);
+vector unsigned long long vec_extract4b (vector unsigned char, const int);
vector unsigned char vec_insert4b (vector signed int, vector unsigned char,
const int);
vector unsigned char vec_insert4b (vector unsigned int, vector unsigned char,
const int);
-vector signed char vec_insert4b (vector int, vector signed char, const int);
-vector unsigned char vec_insert4b (vector unsigned int, vector unsigned char,
- const int);
-vector signed char vec_insert4b (long long, vector signed char, const int);
-vector unsigned char vec_insert4b (long long, vector unsigned char, const int);
vector unsigned int vec_parity_lsbb (vector signed int);
vector unsigned int vec_parity_lsbb (vector unsigned int);
+2018-02-16 Carl Love <cel@us.ibm.com>
+
+ * gcc.target/powerpc/p9-vinsert4b-1.c: Remove test file for non-ABI
+ tests.
+ * gcc.target/powerpc/p9-vinsert4b-2.c: Remove test file for non-ABI
+ tests.
+
2018-02-16 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-7-p9-runnable.c: New runnable test file
+++ /dev/null
-/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2" } */
-
-#include <altivec.h>
-
-vector signed char
-vins_v4si (vector int *vi, vector signed char *vc)
-{
- return vec_vinsert4b (*vi, *vc, 1);
-}
-
-vector unsigned char
-vins_di (long di, vector unsigned char *vc)
-{
- return vec_vinsert4b (di, *vc, 2);
-}
-
-vector char
-vins_di2 (long *p_di, vector char *vc)
-{
- return vec_vinsert4b (*p_di, *vc, 3);
-}
-
-vector unsigned char
-vins_di0 (vector unsigned char *vc)
-{
- return vec_vinsert4b (0, *vc, 4);
-}
-
-long
-vext (vector signed char *vc)
-{
- return vec_vextract4b (*vc, 5);
-}
-
-/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */
-/* { dg-final { scan-assembler "xxinsertw" } } */
+++ /dev/null
-/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2" } */
-
-#include <altivec.h>
-
-vector signed char
-ins_v4si (vector int vi, vector signed char vc)
-{
- return vec_vinsert4b (vi, vc, 13); /* { dg-error "vec_vinsert4b" } */
-}
-
-vector unsigned char
-ins_di (long di, vector unsigned char vc, long n)
-{
- return vec_vinsert4b (di, vc, n); /* { dg-error "vec_vinsert4b" } */
-}
-
-long
-vext1 (vector signed char vc)
-{
- return vec_vextract4b (vc, 13); /* { dg-error "vec_vextract4b" } */
-}
-
-long
-vextn (vector unsigned char vc, long n)
-{
- return vec_vextract4b (vc, n); /* { dg-error "vec_vextract4b" } */
-}
projects / gcc.git / commitdiff