update svremap instruction to correctly store immediate args in SPR

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 7a7d255bcec0ed5db19849c954d3ce1037ba2c98..667d1dad6c0254616f046013e10de6e4c44dbaa6 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -38,6 +38,26 @@ Special Registers Altered:
 
     CR0                     (if Rc=1)
 
+# svremap
+
+SVRM-Form
+
+* svremap SVme, mi0, mi1, mi2, mo0, mo1
+
+Pseudo-code:
+
+    # place into SVREMAP SPR
+    SVREMAP[10:14] <- SVme
+    SVREMAP[0:1] <- mi0
+    SVREMAP[2:3] <- mi1
+    SVREMAP[4:5] <- mi2
+    SVREMAP[6:7] <- mo0
+    SVREMAP[8:9] <- mo1
+
+Special Registers Altered:
+
+    None
+
 # svshape
 
 SVM-Form

diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index ec9ed008e82c37d2d07986f4a97aa52f03d2025d..511e91c792e5d2e7d570ea56a3f7eedc556dc149 100644 (file)
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -280,7 +280,7 @@
    | PO   |  SVxd   |   SVyd | SVzd | SVRM |   XO |  / |
 
 # 1.6.34 SVRM-FORM
-   |0     |6     |10  |12   |14   |16   |18   |20    |26     |31 |
+   |0     |6     |11  |13   |15   |17   |19   |21    |26     |31 |
    | PO   | SVme |mi0 | mi1 | mi2 | mo0 | mo1 | rsvd | XO    | / |
 
 # 1.6.28 Instruction Fields
@@ -588,19 +588,19 @@
         Section 3.3.14, 'Fixed-Point Rotate and Shift
         Instructions' on page 101.
         Formats: M
-    mi0 (10:11)
+    mi0 (11:12)
         Field used in REMAP to select the SVSHAPE for 1st input register
         Formats: SVRM
-    mi1 (12:13)
+    mi1 (13:14)
         Field used in REMAP to select the SVSHAPE for 2nd input register
         Formats: SVRM
-    mi2 (14:15)
+    mi2 (15:16)
         Field used in REMAP to select the SVSHAPE for 3rd input register
         Formats: SVRM
-    mo0 (16:17)
+    mo0 (17:18)
         Field used in REMAP to select the SVSHAPE for 1st output register
         Formats: SVRM
-    mo1 (18:19)
+    mo1 (19:20)
         Field used in REMAP to select the SVSHAPE for 2nd output register
         Formats: SVRM
     MO (6:10)

diff --git a/src/openpower/decoder/isa/svremap.py b/src/openpower/decoder/isa/svremap.py
index f769719461f460f57997f78f5cb8e777db453069..7f65267d7c79359879cc18c30fb2dec6e63caccc 100644 (file)
--- a/src/openpower/decoder/isa/svremap.py
+++ b/src/openpower/decoder/isa/svremap.py
@@ -21,13 +21,12 @@ class SVREMAP(SelectableInt):
             fs = tuple(range(offs, end))
             v = FieldSelectableInt(self, fs)
             self.fsi[field] = v
-            #log("SVREMAP setup field", field, offs, end)
+            log("SVREMAP setup field", field, offs, end)
             offs = end
 
     @property
     def mi0(self):
-        mi0 = self.fsi['mi0'].asint(msb0=True)
-        return SVP64REMAP.mi0(mi0)
+        return self.fsi['mi0'].asint(msb0=True)
 
     @mi0.setter
     def mi0(self, value):
@@ -35,8 +34,7 @@ class SVREMAP(SelectableInt):
 
     @property
     def mi1(self):
-        mi1 = self.fsi['mi1'].asint(msb0=True)
-        return SVP64REMAP.mi1(mi1)
+        return self.fsi['mi1'].asint(msb0=True)
 
     @mi1.setter
     def mi1(self, value):
@@ -44,8 +42,7 @@ class SVREMAP(SelectableInt):
 
     @property
     def mi2(self):
-        mi2 = self.fsi['mi2'].asint(msb0=True)
-        return SVP64REMAP.mi2(mi2)
+        return self.fsi['mi2'].asint(msb0=True)
 
     @mi2.setter
     def mi2(self, value):
@@ -53,8 +50,7 @@ class SVREMAP(SelectableInt):
 
     @property
     def mo0(self):
-        mo0 = self.fsi['mo0'].asint(msb0=True)
-        return SVP64REMAP.mo0(mo0)
+        return self.fsi['mo0'].asint(msb0=True)
 
     @mo0.setter
     def mo0(self, value):
@@ -62,8 +58,7 @@ class SVREMAP(SelectableInt):
 
     @property
     def mo1(self):
-        mo1 = self.fsi['mo1'].asint(msb0=True)
-        return SVP64REMAP.mo1(mo1)
+        return self.fsi['mo1'].asint(msb0=True)
 
     @mo1.setter
     def mo1(self, value):
@@ -71,8 +66,7 @@ class SVREMAP(SelectableInt):
 
     @property
     def men(self):
-        men = self.fsi['men'].asint(msb0=True)
-        return SVP64REMAP.men(men)
+        return self.fsi['men'].asint(msb0=True)
 
     @men.setter
     def men(self, value):

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index c080ee026bc0e119f29e30db2d67b16c1706a820..4216bed70c09d6e313d764dc7de63c7dc8897b3a 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -211,6 +211,22 @@ class SVP64Asm:
             yield ".long 0x%x" % insn
             return
 
+        # and svremap
+        if opcode == 'svremap':
+            insn = 22 << (31-5)          # opcode 22, bits 0-5
+            fields = list(map(int, fields))
+            insn |= fields[0] << (31-10) # SVme       , bits 6-10
+            insn |= fields[1] << (31-12) # mi0        , bits 11-12
+            insn |= fields[2] << (31-14) # mi1        , bits 13-14
+            insn |= fields[3] << (31-16) # mi2        , bits 15-16
+            insn |= fields[4] << (31-18) # m00        , bits 17-18
+            insn |= fields[5] << (31-20) # m01        , bits 19-20
+            insn |= 0b00010   << (31-30) # XO       , bits 26..30
+            #insn &= ((1<<32)-1)
+            log ("svremap", bin(insn))
+            yield ".long 0x%x" % insn
+            return
+
         # identify if is a svp64 mnemonic
         if not opcode.startswith('sv.'):
             yield insn  # unaltered
@@ -981,9 +997,10 @@ if __name__ == '__main__':
              'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
     ]
     lst = [
-             'sv.fmadds 0.v, 8.v, 16.v, 4.v',
-             'svshape 8, 1, 1, 1',
-             'sv.ffadds 0.v, 8.v, 4.v',
+             #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
+             #'svshape 8, 1, 1, 1',
+             #'sv.ffadds 0.v, 8.v, 4.v',
+             'svremap 11, 0, 1, 2, 3, 2',
             ]
     isa = SVP64Asm(lst, macros=macros)
     print ("list", list(isa))