VkDeviceSize stride,
VkQueryResultFlags flags)
{
+ RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
char *data = pData;
VkResult result = VK_SUCCESS;
char *src = pool->ptr + query * pool->stride;
uint32_t available;
- if (flags & VK_QUERY_RESULT_WAIT_BIT) {
- while(!*(volatile uint32_t*)(pool->ptr + pool->availability_offset + 4 * query))
- ;
- }
+ switch (pool->type) {
+ case VK_QUERY_TYPE_TIMESTAMP: {
+ if (flags & VK_QUERY_RESULT_WAIT_BIT) {
+ while(!*(volatile uint32_t*)(pool->ptr + pool->availability_offset + 4 * query))
+ ;
+ }
- if (!*(uint32_t*)(pool->ptr + pool->availability_offset + 4 * query) &&
- !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
- if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)
- *(uint32_t*)dest = 0;
- result = VK_NOT_READY;
- continue;
+ available = *(uint32_t*)(pool->ptr + pool->availability_offset + 4 * query);
+ if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
+ result = VK_NOT_READY;
+ break;
- }
+ }
- available = *(uint32_t*)(pool->ptr + pool->availability_offset + 4 * query);
- switch (pool->type) {
- case VK_QUERY_TYPE_TIMESTAMP:
if (flags & VK_QUERY_RESULT_64_BIT) {
*(uint64_t*)dest = *(uint64_t*)src;
dest += 8;
dest += 4;
}
break;
+ }
case VK_QUERY_TYPE_OCCLUSION: {
- uint64_t result = *(uint64_t*)(src + pool->stride - 16);
+ volatile uint64_t const *src64 = (volatile uint64_t const *)src;
+ uint64_t result = 0;
+ int db_count = get_max_db(device);
+ available = 1;
+
+ for (int i = 0; i < db_count; ++i) {
+ uint64_t start, end;
+ do {
+ start = src64[2 * i];
+ end = src64[2 * i + 1];
+ } while ((!(start & (1ull << 63)) || !(end & (1ull << 63))) && (flags & VK_QUERY_RESULT_WAIT_BIT));
+
+ if (!(start & (1ull << 63)) || !(end & (1ull << 63)))
+ available = 0;
+ else {
+ result += end - start;
+ }
+ }
+
+ if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
+ result = VK_NOT_READY;
+ break;
+
+ }
if (flags & VK_QUERY_RESULT_64_BIT) {
*(uint64_t*)dest = result;
radeon_emit(cs, va + 8);
radeon_emit(cs, (va + 8) >> 32);
- radeon_emit(cs, PKT3(PKT3_OCCLUSION_QUERY, 3, 0));
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
- radeon_emit(cs, va + pool->stride - 16);
- radeon_emit(cs, (va + pool->stride - 16) >> 32);
+ /* hangs for VK_COMMAND_BUFFER_LEVEL_SECONDARY. */
+ if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
+ radeon_emit(cs, PKT3(PKT3_OCCLUSION_QUERY, 3, 0));
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+ radeon_emit(cs, va + pool->stride - 16);
+ radeon_emit(cs, (va + pool->stride - 16) >> 32);
+ }
break;
default: