* ppc-opc.c (ISA_V2): Define and use for relevant BO field tests.

	(valid_bo_pre_v2, valid_bo_post_v2): New functions, extracted from..
	(valid_bo): ..here.  When disassembling, accept either 'y' or 'at'
	type encoding on second pass.
	(powerpc_opcodes): Use ISA_V2 to enable branch insns rather than
	POWER4.
	* ppc-dis.c (print_insn_powerpc): Delete dialect_orig.  Instead
	ignore deprecated on second pass.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2c835d517bc786a5a9a17a5ae243baae4df8b882..ffe1002e33028db77f6962b64ddd297347d5a799 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,9 +1,20 @@
+2011-12-13  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (ISA_V2): Define and use for relevant BO field tests.
+       (valid_bo_pre_v2, valid_bo_post_v2): New functions, extracted from..
+       (valid_bo): ..here.  When disassembling, accept either 'y' or 'at'
+       type encoding on second pass.
+       (powerpc_opcodes): Use ISA_V2 to enable branch insns rather than
+       POWER4.
+       * ppc-dis.c (print_insn_powerpc): Delete dialect_orig.  Instead
+       ignore deprecated on second pass.
+
 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 
        * mips-opc.c (mips_builtin_opcodes): Add "pause".
 
 2011-12-08  Andrew Pinski  <apinski@cavium.com>
-            Adam Nemet  <anemet@caviumnetworks.com>
+           Adam Nemet  <anemet@caviumnetworks.com>
 
        * mips-dis.c (mips_arch_choices): Add Octeon2.
        For "octeon+", just include OcteonP for the insn.
@@ -64,7 +75,7 @@
 
 2011-10-27  Peter Bergner  <bergner@vnet.ibm.com>
 
-        * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
+       * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
        dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
        diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
        instructions.
@@ -189,7 +200,7 @@
        * Makefile.in: Regenerate.
 
 2011-08-09  Chao-ying Fu  <fu@mips.com>
-            Maciej W. Rozycki  <macro@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
 
        * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
        and "mips64r2".
@@ -241,7 +252,7 @@
        * i386-tbl.h: Regenerated.
 
 2011-07-24  Chao-ying Fu  <fu@mips.com>
-            Maciej W. Rozycki  <macro@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
 
        * micromips-opc.c: New file.
        * mips-dis.c (micromips_to_32_reg_b_map): New array.

diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 8771f95b15b6f89e109064238ec19c988d307fba..e0113923c3c9c982ba7467c4540cfca237de11a4 100644 (file)
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -347,7 +347,6 @@ print_insn_powerpc (bfd_vma memaddr,
   const struct powerpc_opcode *opcode;
   const struct powerpc_opcode *opcode_end;
   unsigned long op;
-  ppc_cpu_t dialect_orig = dialect;
 
   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
   if (status != 0)
@@ -386,7 +385,8 @@ print_insn_powerpc (bfd_vma memaddr,
 
       if ((insn & opcode->mask) != opcode->opcode
          || (opcode->flags & dialect) == 0
-         || (opcode->deprecated & dialect_orig) != 0)
+         || (dialect != ~(ppc_cpu_t) PPC_OPCODE_ANY
+             && (opcode->deprecated & dialect) != 0))
        continue;
 
       /* Make two passes over the operands.  First see if any of them

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 950a5afb4fba4e2ed6984e1655d65602067812c5..f5c46167317e149f1d8627022eb2bb7ce9e6996c 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -748,13 +748,15 @@ extract_bba (unsigned long insn,
    extract_bdp always occur in pairs.  One or the other will always
    be valid.  */
 
+#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
+
 static unsigned long
 insert_bdm (unsigned long insn,
            long value,
            ppc_cpu_t dialect,
            const char **errmsg ATTRIBUTE_UNUSED)
 {
-  if ((dialect & PPC_OPCODE_POWER4) == 0)
+  if ((dialect & ISA_V2) == 0)
     {
       if ((value & 0x8000) != 0)
        insn |= 1 << 21;
@@ -774,7 +776,7 @@ extract_bdm (unsigned long insn,
             ppc_cpu_t dialect,
             int *invalid)
 {
-  if ((dialect & PPC_OPCODE_POWER4) == 0)
+  if ((dialect & ISA_V2) == 0)
     {
       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
        *invalid = 1;
@@ -799,7 +801,7 @@ insert_bdp (unsigned long insn,
            ppc_cpu_t dialect,
            const char **errmsg ATTRIBUTE_UNUSED)
 {
-  if ((dialect & PPC_OPCODE_POWER4) == 0)
+  if ((dialect & ISA_V2) == 0)
     {
       if ((value & 0x8000) == 0)
        insn |= 1 << 21;
@@ -819,7 +821,7 @@ extract_bdp (unsigned long insn,
             ppc_cpu_t dialect,
             int *invalid)
 {
-  if ((dialect & PPC_OPCODE_POWER4) == 0)
+  if ((dialect & ISA_V2) == 0)
     {
       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
        *invalid = 1;
@@ -834,52 +836,41 @@ extract_bdp (unsigned long insn,
   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 }
 
-/* Check for legal values of a BO field.  */
-
-static int
-valid_bo (long value, ppc_cpu_t dialect, int extract)
+static inline int
+valid_bo_pre_v2 (long value)
 {
-  if ((dialect & PPC_OPCODE_POWER4) == 0)
-    {
-      int valid;
-      /* Certain encodings have bits that are required to be zero.
-        These are (z must be zero, y may be anything):
-            001zy
-            011zy
-            1z00y
-            1z01y
-            1z1zz
-      */
-      switch (value & 0x14)
-       {
-       default:
-       case 0:
-         valid = 1;
-         break;
-       case 0x4:
-         valid = (value & 0x2) == 0;
-         break;
-       case 0x10:
-         valid = (value & 0x8) == 0;
-         break;
-       case 0x14:
-         valid = value == 0x14;
-         break;
-       }
-      /* When disassembling with -Many, accept power4 encodings too.  */
-      if (valid
-         || (dialect & PPC_OPCODE_ANY) == 0
-         || !extract)
-       return valid;
-    }
+  /* Certain encodings have bits that are required to be zero.
+     These are (z must be zero, y may be anything):
+        0000y 
+        0001y 
+        001zy
+        0100y 
+        0101y 
+        011zy
+        1z00y
+        1z01y
+        1z1zz
+  */
+  if ((value & 0x14) == 0)
+    return 1;
+  else if ((value & 0x14) == 0x4)
+    return (value & 0x2) == 0;
+  else if ((value & 0x14) == 0x10)
+    return (value & 0x8) == 0;
+  else
+    return value == 0x14;
+}
 
+static inline int
+valid_bo_post_v2 (long value)
+{
   /* Certain encodings have bits that are required to be zero.
      These are (z must be zero, a & t may be anything):
         0000z
         0001z
+        001at
         0100z
         0101z
-        001at
         011at
         1a00t
         1a01t
@@ -893,6 +884,24 @@ valid_bo (long value, ppc_cpu_t dialect, int extract)
     return 1;
 }
 
+/* Check for legal values of a BO field.  */
+
+static int
+valid_bo (long value, ppc_cpu_t dialect, int extract)
+{
+  int valid_y = valid_bo_pre_v2 (value);
+  int valid_at = valid_bo_post_v2 (value);
+
+  /* When disassembling with -Many, accept either encoding on the
+     second pass through opcodes.  */
+  if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
+    return valid_y || valid_at;
+  if ((dialect & ISA_V2) == 0)
+    return valid_y;
+  else
+    return valid_at;
+}
+
 /* The BO field in a B form instruction.  Warn about attempts to set
    the field to an illegal value.  */
 
@@ -2019,13 +2028,14 @@ extract_dm (unsigned long insn,
 
    The format of the opcode table is:
 
-   NAME                OPCODE          MASK         FLAGS      {OPERANDS}
+   NAME                OPCODE          MASK         FLAGS      ANTI            {OPERANDS}
 
    NAME is the name of the instruction.
    OPCODE is the instruction opcode.
    MASK is the opcode mask; this is used to tell the disassembler
      which bits in the actual opcode must match OPCODE.
-   FLAGS are flags indicated what processors support the instruction.
+   FLAGS are flags indicating which processors support the instruction.
+   ANTI indicates which processors don't support the instruction.
    OPERANDS is the list of operands.
 
    The disassembler reads the table in order and prints the first
@@ -2892,29 +2902,29 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"bunla+",   BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
 {"bunla",    BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
 
-{"bdnzf-",   BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
-{"bdnzf+",   BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
+{"bdnzf-",   BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
+{"bdnzf+",   BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
 {"bdnzf",    BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdnzfl-",  BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
-{"bdnzfl+",  BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
+{"bdnzfl-",  BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
+{"bdnzfl+",  BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
 {"bdnzfl",   BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdnzfa-",  BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
-{"bdnzfa+",  BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
+{"bdnzfa-",  BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
+{"bdnzfa+",  BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
 {"bdnzfa",   BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdnzfla-", BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
-{"bdnzfla+", BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
+{"bdnzfla-", BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
+{"bdnzfla+", BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
 {"bdnzfla",  BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdzf-",    BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
-{"bdzf+",    BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
+{"bdzf-",    BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
+{"bdzf+",    BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
 {"bdzf",     BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdzfl-",   BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
-{"bdzfl+",   BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
+{"bdzfl-",   BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
+{"bdzfl+",   BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
 {"bdzfl",    BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdzfa-",   BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
-{"bdzfa+",   BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
+{"bdzfa-",   BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
+{"bdzfa+",   BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
 {"bdzfa",    BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdzfla-",  BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
-{"bdzfla+",  BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
+{"bdzfla-",  BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
+{"bdzfla+",  BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
 {"bdzfla",   BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
 
 {"bf-",      BBO(16,BOF,0,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
@@ -2934,29 +2944,29 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"bfla",     BBO(16,BOF,1,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
 {"bbfla",    BBO(16,BOF,1,1),          BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
 
-{"bdnzt-",   BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
-{"bdnzt+",   BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
+{"bdnzt-",   BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
+{"bdnzt+",   BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
 {"bdnzt",    BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdnztl-",  BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
-{"bdnztl+",  BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
+{"bdnztl-",  BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
+{"bdnztl+",  BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
 {"bdnztl",   BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdnzta-",  BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
-{"bdnzta+",  BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
+{"bdnzta-",  BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
+{"bdnzta+",  BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
 {"bdnzta",   BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdnztla-", BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
-{"bdnztla+", BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
+{"bdnztla-", BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
+{"bdnztla+", BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
 {"bdnztla",  BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdzt-",    BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
-{"bdzt+",    BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
+{"bdzt-",    BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
+{"bdzt+",    BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
 {"bdzt",     BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdztl-",   BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
-{"bdztl+",   BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
+{"bdztl-",   BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
+{"bdztl+",   BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
 {"bdztl",    BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdzta-",   BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
-{"bdzta+",   BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
+{"bdzta-",   BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
+{"bdzta+",   BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
 {"bdzta",    BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdztla-",  BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
-{"bdztla+",  BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
+{"bdztla-",  BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
+{"bdztla+",  BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
 {"bdztla",   BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
 
 {"bt-",      BBO(16,BOT,0,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
@@ -3003,219 +3013,219 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM,        PPCNONE,        {BF, BFA}},
 
 {"bdnzlr",   XLO(19,BODNZ,16,0),       XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
-{"bdnzlr-",  XLO(19,BODNZ,16,0),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
+{"bdnzlr-",  XLO(19,BODNZ,16,0),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
 {"bdnzlrl",  XLO(19,BODNZ,16,1),       XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
-{"bdnzlrl-", XLO(19,BODNZ,16,1),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
-{"bdnzlr+",  XLO(19,BODNZP,16,0),      XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
-{"bdnzlrl+", XLO(19,BODNZP,16,1),      XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
+{"bdnzlrl-", XLO(19,BODNZ,16,1),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
+{"bdnzlr+",  XLO(19,BODNZP,16,0),      XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
+{"bdnzlrl+", XLO(19,BODNZP,16,1),      XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
 {"bdzlr",    XLO(19,BODZ,16,0),                XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
-{"bdzlr-",   XLO(19,BODZ,16,0),                XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
+{"bdzlr-",   XLO(19,BODZ,16,0),                XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
 {"bdzlrl",   XLO(19,BODZ,16,1),                XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
-{"bdzlrl-",  XLO(19,BODZ,16,1),                XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
-{"bdzlr+",   XLO(19,BODZP,16,0),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
-{"bdzlrl+",  XLO(19,BODZP,16,1),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
+{"bdzlrl-",  XLO(19,BODZ,16,1),                XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
+{"bdzlr+",   XLO(19,BODZP,16,0),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
+{"bdzlrl+",  XLO(19,BODZP,16,1),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
 {"blr",      XLO(19,BOU,16,0),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
 {"br",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
 {"blrl",     XLO(19,BOU,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
 {"brl",      XLO(19,BOU,16,1),         XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
-{"bdnzlr-",  XLO(19,BODNZM4,16,0),     XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
-{"bdnzlrl-", XLO(19,BODNZM4,16,1),     XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
-{"bdnzlr+",  XLO(19,BODNZP4,16,0),     XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
-{"bdnzlrl+", XLO(19,BODNZP4,16,1),     XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
-{"bdzlr-",   XLO(19,BODZM4,16,0),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
-{"bdzlrl-",  XLO(19,BODZM4,16,1),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
-{"bdzlr+",   XLO(19,BODZP4,16,0),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
-{"bdzlrl+",  XLO(19,BODZP4,16,1),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
+{"bdnzlr-",  XLO(19,BODNZM4,16,0),     XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
+{"bdnzlrl-", XLO(19,BODNZM4,16,1),     XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
+{"bdnzlr+",  XLO(19,BODNZP4,16,0),     XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
+{"bdnzlrl+", XLO(19,BODNZP4,16,1),     XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
+{"bdzlr-",   XLO(19,BODZM4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
+{"bdzlrl-",  XLO(19,BODZM4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
+{"bdzlr+",   XLO(19,BODZP4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
+{"bdzlrl+",  XLO(19,BODZP4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
 
 {"bgelr",    XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgelr-",   XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bgelr-",   XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bger",     XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bnllr",    XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnllr-",   XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnllr-",   XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnlr",     XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bgelrl",   XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bgerl",    XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bnllrl",   XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnlrl",    XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"blelr",    XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"blelr-",   XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"blelr-",   XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bler",     XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bnglr",    XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnglr-",   XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnglr-",   XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bngr",     XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"blelrl",   XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"blelrl-",  XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"blelrl-",  XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"blerl",    XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bnglrl",   XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bngrl",    XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bnelr",    XLOCB(19,BOF,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bner",     XLOCB(19,BOF,CBEQ,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnerl",    XLOCB(19,BOF,CBEQ,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bnslr",    XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnslr-",   XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnslr-",   XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnsr",     XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bnulr",    XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnulr-",   XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnulr-",   XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnslrl",   XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnsrl",    XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bnulrl",   XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bgelr+",   XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnllr+",   XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"blelr+",   XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnglr+",   XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"blelrl+",  XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnslr+",   XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnulr+",   XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"blelr-",   XLOCB(19,BOFM4,CBGT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"blelr+",   XLOCB(19,BOFP4,CBGT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
+{"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bgelr+",   XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnllr+",   XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"blelr+",   XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnglr+",   XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"blelrl+",  XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnslr+",   XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnulr+",   XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"blelr-",   XLOCB(19,BOFM4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"blelr+",   XLOCB(19,BOFP4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
 {"bltlr",    XLOCB(19,BOT,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bltlr-",   XLOCB(19,BOT,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bltlr-",   XLOCB(19,BOT,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bltr",     XLOCB(19,BOT,CBLT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bltlrl",   XLOCB(19,BOT,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bltrl",    XLOCB(19,BOT,CBLT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bgtlr",    XLOCB(19,BOT,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bgtr",     XLOCB(19,BOT,CBGT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bgtrl",    XLOCB(19,BOT,CBGT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"beqlr",    XLOCB(19,BOT,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"beqr",     XLOCB(19,BOT,CBEQ,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"beqrl",    XLOCB(19,BOT,CBEQ,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bsolr",    XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bsolr-",   XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bsolr-",   XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bsor",     XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bunlr",    XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bunlr-",   XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bunlr-",   XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bsolrl",   XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bsorl",    XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
 {"bunlrl",   XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bltlr+",   XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bsolr+",   XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bunlr+",   XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
+{"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bltlr+",   XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bsolr+",   XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bunlr+",   XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
 
 {"bdnzflr",  XLO(19,BODNZF,16,0),      XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdnzflr-", XLO(19,BODNZF,16,0),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bdnzflr-", XLO(19,BODNZF,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bdnzflrl", XLO(19,BODNZF,16,1),      XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdnzflrl-",XLO(19,BODNZF,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bdnzflr+", XLO(19,BODNZFP,16,0),     XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bdnzflrl+",XLO(19,BODNZFP,16,1),     XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bdnzflrl-",XLO(19,BODNZF,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bdnzflr+", XLO(19,BODNZFP,16,0),     XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bdnzflrl+",XLO(19,BODNZFP,16,1),     XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bdzflr",   XLO(19,BODZF,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdzflr-",  XLO(19,BODZF,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bdzflr-",  XLO(19,BODZF,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bdzflrl",  XLO(19,BODZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdzflrl-", XLO(19,BODZF,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bdzflr+",  XLO(19,BODZFP,16,0),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bdzflrl+", XLO(19,BODZFP,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bdzflrl-", XLO(19,BODZF,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bdzflr+",  XLO(19,BODZFP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bdzflrl+", XLO(19,BODZFP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bflr",     XLO(19,BOF,16,0),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bflr-",    XLO(19,BOF,16,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bflr-",    XLO(19,BOF,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bbfr",     XLO(19,BOF,16,0),         XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
 {"bflrl",    XLO(19,BOF,16,1),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bflrl-",   XLO(19,BOF,16,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bflrl-",   XLO(19,BOF,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bbfrl",    XLO(19,BOF,16,1),         XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
-{"bflr+",    XLO(19,BOFP,16,0),                XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bflrl+",   XLO(19,BOFP,16,1),                XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bflr-",    XLO(19,BOFM4,16,0),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"bflrl-",   XLO(19,BOFM4,16,1),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"bflr+",    XLO(19,BOFP4,16,0),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"bflrl+",   XLO(19,BOFP4,16,1),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
+{"bflr+",    XLO(19,BOFP,16,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bflrl+",   XLO(19,BOFP,16,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bflr-",    XLO(19,BOFM4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"bflrl-",   XLO(19,BOFM4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"bflr+",    XLO(19,BOFP4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"bflrl+",   XLO(19,BOFP4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
 {"bdnztlr",  XLO(19,BODNZT,16,0),      XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdnztlr-", XLO(19,BODNZT,16,0),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bdnztlr-", XLO(19,BODNZT,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bdnztlrl", XLO(19,BODNZT,16,1),      XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdnztlrl-",XLO(19,BODNZT,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bdnztlr+", XLO(19,BODNZTP,16,0),     XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bdnztlrl+",XLO(19,BODNZTP,16,1),     XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bdnztlrl-",XLO(19,BODNZT,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bdnztlr+", XLO(19,BODNZTP,16,0),     XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bdnztlrl+",XLO(19,BODNZTP,16,1),     XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bdztlr",   XLO(19,BODZT,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdztlr-",  XLO(19,BODZT,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bdztlr-",  XLO(19,BODZT,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bdztlrl",  XLO(19,BODZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdztlrl-", XLO(19,BODZT,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bdztlr+",  XLO(19,BODZTP,16,0),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bdztlrl+", XLO(19,BODZTP,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bdztlrl-", XLO(19,BODZT,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bdztlr+",  XLO(19,BODZTP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bdztlrl+", XLO(19,BODZTP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"btlr",     XLO(19,BOT,16,0),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"btlr-",    XLO(19,BOT,16,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"btlr-",    XLO(19,BOT,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bbtr",     XLO(19,BOT,16,0),         XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
 {"btlrl",    XLO(19,BOT,16,1),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"btlrl-",   XLO(19,BOT,16,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"btlrl-",   XLO(19,BOT,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bbtrl",    XLO(19,BOT,16,1),         XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
-{"btlr+",    XLO(19,BOTP,16,0),                XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"btlrl+",   XLO(19,BOTP,16,1),                XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"btlr-",    XLO(19,BOTM4,16,0),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"btlrl-",   XLO(19,BOTM4,16,1),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"btlr+",    XLO(19,BOTP4,16,0),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"btlrl+",   XLO(19,BOTP4,16,1),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
+{"btlr+",    XLO(19,BOTP,16,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"btlrl+",   XLO(19,BOTP,16,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"btlr-",    XLO(19,BOTM4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"btlrl-",   XLO(19,BOTM4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"btlr+",    XLO(19,BOTP4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"btlrl+",   XLO(19,BOTP4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
 
 {"bclr-",    XLYLK(19,16,0,0),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
 {"bclrl-",   XLYLK(19,16,0,1),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
@@ -3275,146 +3285,146 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"bctrl",   XLO(19,BOU,528,1),         XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
 
 {"bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"blectr-", XLOCB(19,BOFM4,CBGT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"blectr+", XLOCB(19,BOFP4,CBGT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
+{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"blectr-", XLOCB(19,BOFM4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"blectr+", XLOCB(19,BOFP4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
 {"bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
+{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
 {"bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
-{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
-{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1),        XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
+{"bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
+{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
+{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
 
 {"bfctr",   XLO(19,BOF,528,0),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bfctr-",  XLO(19,BOF,528,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"bfctr-",  XLO(19,BOF,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"bfctrl",  XLO(19,BOF,528,1),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bfctrl-", XLO(19,BOF,528,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bfctr+",  XLO(19,BOFP,528,0),                XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bfctrl+", XLO(19,BOFP,528,1),                XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"bfctr-",  XLO(19,BOFM4,528,0),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"bfctrl-", XLO(19,BOFM4,528,1),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"bfctr+",  XLO(19,BOFP4,528,0),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"bfctrl+", XLO(19,BOFP4,528,1),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
+{"bfctrl-", XLO(19,BOF,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bfctr+",  XLO(19,BOFP,528,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bfctrl+", XLO(19,BOFP,528,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"bfctr-",  XLO(19,BOFM4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"bfctrl-", XLO(19,BOFM4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"bfctr+",  XLO(19,BOFP4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"bfctrl+", XLO(19,BOFP4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
 {"btctr",   XLO(19,BOT,528,0),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"btctr-",  XLO(19,BOT,528,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
+{"btctr-",  XLO(19,BOT,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
 {"btctrl",  XLO(19,BOT,528,1),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"btctrl-", XLO(19,BOT,528,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"btctr+",  XLO(19,BOTP,528,0),                XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"btctrl+", XLO(19,BOTP,528,1),                XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
-{"btctr-",  XLO(19,BOTM4,528,0),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"btctrl-", XLO(19,BOTM4,528,1),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"btctr+",  XLO(19,BOTP4,528,0),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
-{"btctrl+", XLO(19,BOTP4,528,1),       XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
+{"btctrl-", XLO(19,BOT,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"btctr+",  XLO(19,BOTP,528,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"btctrl+", XLO(19,BOTP,528,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
+{"btctr-",  XLO(19,BOTM4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"btctrl-", XLO(19,BOTM4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"btctr+",  XLO(19,BOTP4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
+{"btctrl+", XLO(19,BOTP4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
 
 {"bcctr-",  XLYLK(19,528,0,0),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
 {"bcctrl-", XLYLK(19,528,0,1),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},