SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.

diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh
index 28e3ec259cdc79279667a48d85c9c1dd878aacec..68c73cac0fadc21d743d102af06b2a77d9eacd59 100644 (file)
--- a/src/arch/sparc/mmapped_ipr.hh
+++ b/src/arch/sparc/mmapped_ipr.hh
@@ -48,21 +48,13 @@ namespace SparcISA
 inline Tick
 handleIprRead(ThreadContext *xc, Packet *pkt)
 {
-#if FULL_SYSTEM
     return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
-#else
-    panic("Shouldn't have a memory mapped register in SE\n");
-#endif
 }
 
 inline Tick
 handleIprWrite(ThreadContext *xc, Packet *pkt)
 {
-#if FULL_SYSTEM
     return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
-#else
-    panic("Shouldn't have a memory mapped register in SE\n");
-#endif
 }
 
 

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index ddc37cf3bf6e05be62935afe0a626b79569c4c6b..6e390143bf50e3ca4f8899029c20b1010470408b 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -840,8 +840,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
-#if FULL_SYSTEM
-
 Tick
 TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
@@ -1280,8 +1278,6 @@ doMmuWriteError:
     return tc->getCpuPtr()->ticks(1);
 }
 
-#endif
-
 void
 TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
 {

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 76ef23b649b83f7bc0c1391a4a27f866f6c9a958..7d33f7044a3f67fec60452f69d30ae1f995f4bc6 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -167,10 +167,8 @@ class TLB : public BaseTLB
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
     void translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);
-#if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
 
     // Checkpointing