add "reverse-gear" mode to mapreduce in SVP64

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index 961929a85e674ec1e3e366486c8eb10a16f0908c..3cc9e08a45fb3359c8fc3b4a4003025c870e9292 100644 (file)
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -227,8 +227,10 @@ class SVP64MODEb:
     SZ = 4  # for source
     # reduce mode
     REDUCE = 2  # 0=normal predication 1=reduce mode
+    PARALLEL = 3 # 1=parallel reduce, 0=scalar reduce
     SVM = 3  # subvector reduce mode 0=independent 1=horizontal
     CRM = 4  # CR mode on reduce (Rc=1) 0=some 1=all
+    RG = 4   # Reverse-gear on reduce
     # saturation mode
     N = 2  # saturation signed mode 0=signed 1=unsigned
     # ffirst and predicate result modes