arch-riscv: Initialize interrupt mask

This patch initializes RISCV interrupt mask to 0.

Change-Id: I56289d9f3f319e239e305befea006a0ad4d86b75
Reviewed-on: https://gem5-review.googlesource.com/c/16162
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index 406fe4ffa54af79276e0de708ae7b577237b4d98..ed946879b3391120ae1a6ec9fbcb93b7ed697a70 100644 (file)
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -74,7 +74,7 @@ class Interrupts : public SimObject
     std::bitset<NumInterruptTypes>
     globalMask(ThreadContext *tc) const
     {
-        INTERRUPT mask;
+        INTERRUPT mask = 0;
         STATUS status = tc->readMiscReg(MISCREG_STATUS);
         if (status.mie)
             mask.mei = mask.mti = mask.msi = 1;