split out instructions from openpower/isa/svfixedarith.mdwn

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 6ce79fb69925bef2faef666c0a251e860ec3e3b0..3a74609b0a7c9fdb08486b4b9f3e204a16d9c57d 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -1,117 +1,9 @@
-# [DRAFT] Multiply and Add Extended Doubleword Unsigned
+[[!inline pagenames="openpower/isa/svfixedarith/maddedu" raw="yes"]]
 
-VA-Form
+[[!inline pagenames="openpower/isa/svfixedarith/maddedus" raw="yes"]]
 
-* maddedu RT,RA,RB,RC
+[[!inline pagenames="openpower/isa/svfixedarith/divmod2du" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/svfixedarith/dsld" raw="yes"]]
 
-    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
-    prod[0:2*XLEN-1] <- (RA) * (RB)
-    sum[0:2*XLEN-1] <- ([0] * XLEN || (RC)) + prod
-    RT <- sum[XLEN:2*XLEN-1]
-    RS <- sum[0:XLEN-1]
-
-Special Registers Altered:
-
-    None
-
-# [DRAFT] Multiply and Add Extended Doubleword Unsigned Signed
-
-VA-Form
-
-* maddedus RT,RA,RB,RC
-
-Pseudo-code:
-
-    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
-    <!-- no MULUS, so do it manually -->
-    prod[0:XLEN*2-1] <- [0] * (XLEN * 2)
-    if (RB)[0] != 0 then
-        prod[0:XLEN*2-1] <- -((RA) * -(RB))
-    else
-        prod[0:XLEN*2-1] <- (RA) * (RB)
-    <!-- no EXTS2XL, so do it manually -->
-    sum[0:XLEN*2-1] <- prod + (EXTSXL((RC)[0], 1) || (RC))
-    RT <- sum[XLEN:2*XLEN-1]
-    RS <- sum[0:XLEN-1]
-
-Special Registers Altered:
-
-    None
-
-# [DRAFT] Divide/Modulo Double-width Doubleword Unsigned
-
-VA-Form
-
-* divmod2du   RT,RA,RB,RC
-
-Pseudo-code:
-
-    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
-    if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
-        dividend[0:(XLEN*2)-1] <- (RC) || (RA)
-        divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
-        result <- dividend / divisor
-        modulo <- dividend % divisor
-        RT <- result[XLEN:(XLEN*2)-1]
-        RS <- modulo[XLEN:(XLEN*2)-1]
-        overflow <- 0
-    else
-        overflow <- 1
-        RT <- [1]*XLEN
-        RS <- [0]*XLEN
-
-Special Registers Altered:
-
-    XER.OV
-
-# [DRAFT] Double-width Shift Left Doubleword
-
-VA2-Form
-
-* dsld    RT,RA,RB,RC  (Rc=0)
-* dsld.   RT,RA,RB,RC  (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)[58:63]
-    v <- ROTL64((RA), n)
-    mask <- MASK(0, 63-n)
-    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
-    RS <- v[0:63] & ¬mask
-    overflow <- 0             # relevant only when Rc=1
-    if RS != [0]*64 then
-        overflow <- 1         # relevant only when Rc=1
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
-
-# [DRAFT] Double-width Shift Right Doubleword
-
-VA2-Form
-
-* dsrd    RT,RA,RB,RC  (Rc=0)
-* dsrd.   RT,RA,RB,RC  (Rc=1)
-
-Pseudo-code:
-
-    n <- (RB)[58:63]
-    v <- ROTL64((RA), 64-n)
-    mask <- MASK(n, 63)
-    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
-    RS <- v[0:63] & ¬mask
-    overflow <- 0             # relevant only when Rc=1
-    if RS != [0]*64 then
-        overflow <- 1         # relevant only when Rc=1
-
-Special Registers Altered:
-
-    CR0                    (if Rc=1)
+[[!inline pagenames="openpower/isa/svfixedarith/dsrd" raw="yes"]]

diff --git a/openpower/isa/svfixedarith/divmod2du.mdwn b/openpower/isa/svfixedarith/divmod2du.mdwn
new file mode 100644 (file)
index 0000000..5cef347
--- /dev/null
+++ b/openpower/isa/svfixedarith/divmod2du.mdwn
@@ -0,0 +1,13 @@
+# [DRAFT] Divide/Modulo Double-width Doubleword Unsigned
+
+VA-Form
+
+* divmod2du   RT,RA,RB,RC
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfixedarith/divmod2du_code" raw="yes"]]
+
+Special Registers Altered:
+
+    XER.OV

diff --git a/openpower/isa/svfixedarith/divmod2du_code.mdwn b/openpower/isa/svfixedarith/divmod2du_code.mdwn
new file mode 100644 (file)
index 0000000..8bff5a2
--- /dev/null
+++ b/openpower/isa/svfixedarith/divmod2du_code.mdwn
@@ -0,0 +1,15 @@
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
+    if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
+        dividend[0:(XLEN*2)-1] <- (RC) || (RA)
+        divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
+        result <- dividend / divisor
+        modulo <- dividend % divisor
+        RT <- result[XLEN:(XLEN*2)-1]
+        RS <- modulo[XLEN:(XLEN*2)-1]
+        overflow <- 0
+    else
+        overflow <- 1
+        RT <- [1]*XLEN
+        RS <- [0]*XLEN

diff --git a/openpower/isa/svfixedarith/dsld.mdwn b/openpower/isa/svfixedarith/dsld.mdwn
new file mode 100644 (file)
index 0000000..b3a3c4e
--- /dev/null
+++ b/openpower/isa/svfixedarith/dsld.mdwn
@@ -0,0 +1,14 @@
+# [DRAFT] Double-width Shift Left Doubleword
+
+VA2-Form
+
+* dsld    RT,RA,RB,RC  (Rc=0)
+* dsld.   RT,RA,RB,RC  (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfixedarith/dsld_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/svfixedarith/dsld_code.mdwn b/openpower/isa/svfixedarith/dsld_code.mdwn
new file mode 100644 (file)
index 0000000..28d8c95
--- /dev/null
+++ b/openpower/isa/svfixedarith/dsld_code.mdwn
@@ -0,0 +1,8 @@
+    n <- (RB)[58:63]
+    v <- ROTL64((RA), n)
+    mask <- MASK(0, 63-n)
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
+    RS <- v[0:63] & ¬mask
+    overflow <- 0             # relevant only when Rc=1
+    if RS != [0]*64 then
+        overflow <- 1         # relevant only when Rc=1

diff --git a/openpower/isa/svfixedarith/dsrd.mdwn b/openpower/isa/svfixedarith/dsrd.mdwn
new file mode 100644 (file)
index 0000000..e5c8edb
--- /dev/null
+++ b/openpower/isa/svfixedarith/dsrd.mdwn
@@ -0,0 +1,14 @@
+# [DRAFT] Double-width Shift Right Doubleword
+
+VA2-Form
+
+* dsrd    RT,RA,RB,RC  (Rc=0)
+* dsrd.   RT,RA,RB,RC  (Rc=1)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfixedarith/dsrd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)

diff --git a/openpower/isa/svfixedarith/dsrd_code.mdwn b/openpower/isa/svfixedarith/dsrd_code.mdwn
new file mode 100644 (file)
index 0000000..e3ce20f
--- /dev/null
+++ b/openpower/isa/svfixedarith/dsrd_code.mdwn
@@ -0,0 +1,8 @@
+    n <- (RB)[58:63]
+    v <- ROTL64((RA), 64-n)
+    mask <- MASK(n, 63)
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
+    RS <- v[0:63] & ¬mask
+    overflow <- 0             # relevant only when Rc=1
+    if RS != [0]*64 then
+        overflow <- 1         # relevant only when Rc=1

diff --git a/openpower/isa/svfixedarith/maddedu.mdwn b/openpower/isa/svfixedarith/maddedu.mdwn
new file mode 100644 (file)
index 0000000..e612f16
--- /dev/null
+++ b/openpower/isa/svfixedarith/maddedu.mdwn
@@ -0,0 +1,13 @@
+# [DRAFT] Multiply and Add Extended Doubleword Unsigned
+
+VA-Form
+
+* maddedu RT,RA,RB,RC
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfixedarith/maddedu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/svfixedarith/maddedu_code.mdwn b/openpower/isa/svfixedarith/maddedu_code.mdwn
new file mode 100644 (file)
index 0000000..c35161b
--- /dev/null
+++ b/openpower/isa/svfixedarith/maddedu_code.mdwn
@@ -0,0 +1,7 @@
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
+    prod[0:2*XLEN-1] <- (RA) * (RB)
+    sum[0:2*XLEN-1] <- ([0] * XLEN || (RC)) + prod
+    RT <- sum[XLEN:2*XLEN-1]
+    RS <- sum[0:XLEN-1]

diff --git a/openpower/isa/svfixedarith/maddedus.mdwn b/openpower/isa/svfixedarith/maddedus.mdwn
new file mode 100644 (file)
index 0000000..f954961
--- /dev/null
+++ b/openpower/isa/svfixedarith/maddedus.mdwn
@@ -0,0 +1,13 @@
+# [DRAFT] Multiply and Add Extended Doubleword Unsigned Signed
+
+VA-Form
+
+* maddedus RT,RA,RB,RC
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/svfixedarith/maddedus_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/svfixedarith/maddedus_code.mdwn b/openpower/isa/svfixedarith/maddedus_code.mdwn
new file mode 100644 (file)
index 0000000..03f808a
--- /dev/null
+++ b/openpower/isa/svfixedarith/maddedus_code.mdwn
@@ -0,0 +1,13 @@
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
+    <!-- no MULUS, so do it manually -->
+    prod[0:XLEN*2-1] <- [0] * (XLEN * 2)
+    if (RB)[0] != 0 then
+        prod[0:XLEN*2-1] <- -((RA) * -(RB))
+    else
+        prod[0:XLEN*2-1] <- (RA) * (RB)
+    <!-- no EXTS2XL, so do it manually -->
+    sum[0:XLEN*2-1] <- prod + (EXTSXL((RC)[0], 1) || (RC))
+    RT <- sum[XLEN:2*XLEN-1]
+    RS <- sum[0:XLEN-1]