sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain.

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index 3e7365ed88c4d6d66e6b9d0efb5bb235a157b3ea..ea2b62c1fde93fd4892fb5c10c0f91e46131d49d 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -30,7 +30,7 @@ class _CRG(Module):
         self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200    = ClockDomain()
         self.clock_domains.cd_eth       = ClockDomain()
-        self.clock_domains.cd_sdcard    = ClockDomain()
+        self.clock_domains.cd_sd        = ClockDomain()
 
         # # #
 
@@ -42,7 +42,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_clk200,    200e6)
         pll.create_clkout(self.cd_eth,       50e6)
-        pll.create_clkout(self.cd_sdcard,    10e6)
+        pll.create_clkout(self.cd_sd,        10e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index f1e1f27489cc2cb66dcf751a8ff4f58dc3a3a6ae..70a58660cde2760d3a81f8cca4575d2495ddb109 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -30,7 +30,7 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200    = ClockDomain()
         self.clock_domains.cd_clk100    = ClockDomain()
-        self.clock_domains.cd_sdcard    = ClockDomain()
+        self.clock_domains.cd_sd        = ClockDomain()
 
         # # #
 
@@ -42,7 +42,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_clk200,    200e6)
         pll.create_clkout(self.cd_clk100,    100e6)
-        pll.create_clkout(self.cd_sdcard,    10e6)
+        pll.create_clkout(self.cd_sd,        10e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 8608aa2bca097f64990edbccd3fde411431732e2..915eab8e192885b1c6f11badce184125a4a04ee3 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -32,7 +32,7 @@ class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
-        self.clock_domains.cd_sdcard = ClockDomain()
+        self.clock_domains.cd_sd     = ClockDomain()
 
         # # #
 
@@ -46,9 +46,9 @@ class _CRG(Module):
         pll.register_clkin(clk25, 25e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
-        pll.create_clkout(self.cd_sdcard, 10e6)
-        self.specials += AsyncResetSynchronizer(self.cd_sys,    ~pll.locked | rst)
-        self.specials += AsyncResetSynchronizer(self.cd_sdcard, ~pll.locked | rst)
+        pll.create_clkout(self.cd_sd,     10e6)
+        self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
+        self.specials += AsyncResetSynchronizer(self.cd_sd,  ~pll.locked | rst)
 
         # USB PLL
         if with_usb_pll:

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 667040ba5afe247bde672557b3a3406110f689a3..15cb2b581e675da11d5c683fa111224fc098c0d1 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1291,4 +1291,4 @@ class LiteXSoC(SoC):
 
         # Timing constraints
         if not with_emulator:
-            self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.crg.cd_sdcard.clk)
+            self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.crg.cd_sd.clk)