}
static inline void
-gen6_3DSTATE_AA_LINE_PARAMETERS(struct ilo_builder *builder)
+gen6_3DSTATE_AA_LINE_PARAMETERS(struct ilo_builder *builder,
+ const struct ilo_state_raster *rs)
{
const uint8_t cmd_len = 3;
- const uint32_t dw[3] = {
- GEN6_RENDER_CMD(3D, 3DSTATE_AA_LINE_PARAMETERS) | (cmd_len - 2),
- 0 << GEN6_AA_LINE_DW1_BIAS__SHIFT | 0,
- 0 << GEN6_AA_LINE_DW2_CAP_BIAS__SHIFT | 0,
- };
+ uint32_t *dw;
ILO_DEV_ASSERT(builder->dev, 6, 8);
- ilo_builder_batch_write(builder, cmd_len, dw);
+ ilo_builder_batch_pointer(builder, cmd_len, &dw);
+
+ dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_AA_LINE_PARAMETERS) | (cmd_len - 2);
+ /* constant */
+ dw[1] = 0 << GEN6_AA_LINE_DW1_BIAS__SHIFT |
+ 0 << GEN6_AA_LINE_DW1_SLOPE__SHIFT;
+ dw[2] = 0 << GEN6_AA_LINE_DW2_CAP_BIAS__SHIFT |
+ 0 << GEN6_AA_LINE_DW2_CAP_SLOPE__SHIFT;
}
static inline void
ILO_STATE_RASTER_3DSTATE_SF |
ILO_STATE_RASTER_3DSTATE_MULTISAMPLE |
ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK |
- ILO_STATE_RASTER_3DSTATE_WM;
+ ILO_STATE_RASTER_3DSTATE_WM |
+ ILO_STATE_RASTER_3DSTATE_AA_LINE_PARAMETERS;
if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
delta->dirty |= ILO_STATE_RASTER_3DSTATE_RASTER |
ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK = (1 << 4),
ILO_STATE_RASTER_3DSTATE_WM = (1 << 5),
ILO_STATE_RASTER_3DSTATE_WM_HZ_OP = (1 << 6),
+ ILO_STATE_RASTER_3DSTATE_AA_LINE_PARAMETERS = (1 << 7),
};
enum ilo_state_raster_earlyz_op {
}
/* 3DSTATE_AA_LINE_PARAMETERS */
- if (DIRTY(RASTERIZER) && vec->rasterizer->state.line_smooth) {
+ if (session->rs_delta.dirty &
+ ILO_STATE_RASTER_3DSTATE_AA_LINE_PARAMETERS) {
if (ilo_dev_gen(r->dev) == ILO_GEN(6))
gen6_wa_pre_non_pipelined(r);
- gen6_3DSTATE_AA_LINE_PARAMETERS(r->builder);
+ gen6_3DSTATE_AA_LINE_PARAMETERS(r->builder, &vec->rasterizer->rs);
}
}