#define IMPL_ROCKET 1
-#define DEFAULT_MTVEC 0x100
+#define DEFAULT_RSTVEC 0x0
+#define DEFAULT_NMIVEC 0x4
+#define DEFAULT_MTVEC 0x8
// page table entry (PTE) fields
#define PTE_V 0x001 // Valid
#define CSR_MCAUSE 0x342
#define CSR_MBADADDR 0x343
#define CSR_MIP 0x344
+#define CSR_MIPI 0x345
#define CSR_MTIME 0x701
#define CSR_MCPUID 0xf00
#define CSR_MIMPID 0xf01
#define CSR_MTOHOST 0x780
#define CSR_MFROMHOST 0x781
#define CSR_MRESET 0x782
-#define CSR_MIPI 0x783
#define CSR_MIOBASE 0x784
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
DECLARE_CSR(mcause, CSR_MCAUSE)
DECLARE_CSR(mbadaddr, CSR_MBADADDR)
DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(mipi, CSR_MIPI)
DECLARE_CSR(mtime, CSR_MTIME)
DECLARE_CSR(mcpuid, CSR_MCPUID)
DECLARE_CSR(mimpid, CSR_MIMPID)
DECLARE_CSR(mtohost, CSR_MTOHOST)
DECLARE_CSR(mfromhost, CSR_MFROMHOST)
DECLARE_CSR(mreset, CSR_MRESET)
-DECLARE_CSR(mipi, CSR_MIPI)
DECLARE_CSR(miobase, CSR_MIOBASE)
DECLARE_CSR(cycleh, CSR_CYCLEH)
DECLARE_CSR(timeh, CSR_TIMEH)
{
memset(this, 0, sizeof(*this));
prv = PRV_M;
- pc = DEFAULT_MTVEC + 0x100;
+ pc = DEFAULT_RSTVEC;
load_reservation = -1;
}
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_S);
} else {
- state.pc = DEFAULT_MTVEC + 0x40 * state.prv;
+ state.pc = DEFAULT_MTVEC;
state.mcause = t.cause();
state.mepc = epc;
if (t.has_badaddr())