tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others...

LiteSPI is not mature enough to be integrated in LiteX sim directly. (will case trouble is things are refactored).

This could be re-introduced later when more mature. For now simulation with LiteX Sim
could be tested directly in LiteSPI with a custom simulation.

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index f777ea9d221aadb25f1e40e879acaad384a76b58..1efea94d3566339045618a4219836bdedc6cf91b 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -18,9 +18,6 @@ from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 from litex.soc.integration.soc import *
 
-from litespi import LiteSPI
-from litespi.phy.model import LiteSPIPHYModel
-
 from litedram import modules as litedram_modules
 from litedram.common import *
 from litedram.phy.model import SDRAMPHYModel
@@ -160,7 +157,6 @@ class SimSoC(SoCSDRAM):
 
     def __init__(self,
         with_sdram            = False,
-        with_spi_xip          = False,
         with_ethernet         = False,
         with_etherbone        = False,
         etherbone_mac_address = 0x10e2d5000001,
@@ -182,14 +178,6 @@ class SimSoC(SoCSDRAM):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"))
 
-        # SPI XIP ----------------------------------------------------------------------------------
-        if with_spi_xip:
-            spi_xip_size = kwargs["spi_xip_size"]
-            self.submodules.spiphy = LiteSPIPHYModel(spi_xip_size, init=kwargs["spi_xip_init"])
-            self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness)
-            spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None), size=spi_xip_size, cached=False)
-            self.bus.add_slave(name="spixip", slave=self.spictl.bus, region=spi_xip_region)
-
         # SDRAM ------------------------------------------------------------------------------------
         if with_sdram:
             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
@@ -292,8 +280,6 @@ def main():
     parser.add_argument("--threads",              default=1,               help="Set number of threads (default=1)")
     parser.add_argument("--rom-init",             default=None,            help="rom_init file")
     parser.add_argument("--ram-init",             default=None,            help="ram_init file")
-    parser.add_argument("--with-spi-xip",         action="store_true",     help="Enable SPI XIP support")
-    parser.add_argument("--spi-xip-init",         default=None,            help="spi_xip_init file")
     parser.add_argument("--with-sdram",           action="store_true",     help="Enable SDRAM support")
     parser.add_argument("--sdram-module",         default="MT48LC16M16",   help="Select SDRAM chip")
     parser.add_argument("--sdram-data-width",     default=32,              help="Set SDRAM chip data width")
@@ -326,9 +312,6 @@ def main():
     soc_kwargs["uart_name"] = "sim"
     if args.rom_init:
         soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
-    if args.with_spi_xip:
-        soc_kwargs["spi_xip_size"] = 8*1024*1024
-        soc_kwargs["spi_xip_init"] = get_mem_data(args.spi_xip_init, "big") if args.spi_xip_init is not None else None
     if not args.with_sdram:
         soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
         if args.ram_init is not None:
@@ -346,7 +329,6 @@ def main():
     # SoC ------------------------------------------------------------------------------------------
     soc = SimSoC(
         with_sdram     = args.with_sdram,
-        with_spi_xip   = args.with_spi_xip,
         with_ethernet  = args.with_ethernet,
         with_etherbone = args.with_etherbone,
         with_analyzer  = args.with_analyzer,