i965: Don't PIPE_CONTROL instruction cache flush.

This is a workaround for Ironlake errata.  The emit_mi_flush is used
for a few purposes:
1) Flushing write caches for RTT (including blit to texture)
2) Pipe fencing for sync objects
3) Spamming cache flushes to track down cache flush bugs

Spamming cache flushes seems less important than following the docs,
and we should probably do that with a different mechanism than the one
for render cache flushes.

diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index ca8e34483685dcf6992741371845ddaa23cffe48..de5134008f2672206d66a2c1e834981d03eb907b 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -278,7 +278,6 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
    if (intel->gen >= 4) {
       BEGIN_BATCH(4);
       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
-               PIPE_CONTROL_INSTRUCTION_FLUSH |
                PIPE_CONTROL_WRITE_FLUSH |
                PIPE_CONTROL_NO_WRITE);
       OUT_BATCH(0); /* write address */