Don't reset the core / peripherals on DRAM controller reset request

diff --git a/examples/ecp5_crg.py b/examples/ecp5_crg.py
index cda8a9932b34a75ed9426a1b0a24e1023a80aed1..931168e91eaa60bde81b0e1d016eafe04b990495 100644 (file)
--- a/examples/ecp5_crg.py
+++ b/examples/ecp5_crg.py
@@ -242,7 +242,7 @@ class ECP5CRG(Elaboratable):
         reset_ok = Signal(reset_less=True)
         m.d.comb += reset_ok.eq(~pll.locked|~pod_done)
         m.d.comb += ResetSignal("init").eq(reset_ok)
-        m.d.comb += ResetSignal("sync").eq(reset_ok|self.ddr_clk_reset)
+        m.d.comb += ResetSignal("sync").eq(reset_ok)
         m.d.comb += ResetSignal("dramsync").eq(reset_ok|self.ddr_clk_reset)
 
         # # Generating sync (100Mhz) from sync2x