litesata: pep8 (E203)

diff --git a/misoclib/mem/litesata/common.py b/misoclib/mem/litesata/common.py
index 4d2fa017011f77cbb3e70bf0283ea47a65a76528..6c28da749764df0fe5e71d9e63c1b06b9c6d40a3 100644 (file)
--- a/misoclib/mem/litesata/common.py
+++ b/misoclib/mem/litesata/common.py
@@ -14,33 +14,33 @@ from migen.actorlib.fifo import *
 from migen.actorlib.structuring import Pipeline, Converter
 
 bitrates = {
-    "sata_gen3"    :    6.0,
-    "sata_gen2"    :    3.0,
-    "sata_gen1"    :    1.5,
+    "sata_gen3": 6.0,
+    "sata_gen2": 3.0,
+    "sata_gen1": 1.5,
 }
 
 frequencies = {
-    "sata_gen3"    :    150.0,
-    "sata_gen2"    :    75.0,
-    "sata_gen1"    :    37.5,
+    "sata_gen3": 150.0,
+    "sata_gen2": 75.0,
+    "sata_gen1": 37.5,
 }
 
 # PHY / Link Layers
 primitives = {
-    "ALIGN"    :    0x7B4A4ABC,
-    "CONT"    :     0X9999AA7C,
-    "SYNC"    :    0xB5B5957C,
-    "R_RDY"    :    0x4A4A957C,
-    "R_OK"    :    0x3535B57C,
-    "R_ERR"    :    0x5656B57C,
-    "R_IP"    :    0X5555B57C,
-    "X_RDY"    :    0x5757B57C,
-    "CONT"    :    0x9999AA7C,
-    "WTRM"    :    0x5858B57C,
-    "SOF"    :    0x3737B57C,
-    "EOF"    :    0xD5D5B57C,
-    "HOLD"    :    0xD5D5AA7C,
-    "HOLDA"    :     0X9595AA7C
+    "ALIGN":  0x7B4A4ABC,
+    "CONT":   0X9999AA7C,
+    "SYNC":   0xB5B5957C,
+    "R_RDY":  0x4A4A957C,
+    "R_OK":   0x3535B57C,
+    "R_ERR":  0x5656B57C,
+    "R_IP":   0X5555B57C,
+    "X_RDY":  0x5757B57C,
+    "CONT":   0x9999AA7C,
+    "WTRM":   0x5858B57C,
+    "SOF":    0x3737B57C,
+    "EOF":    0xD5D5B57C,
+    "HOLD":   0xD5D5AA7C,
+    "HOLDA":  0X9595AA7C
 }
 
 
@@ -193,22 +193,22 @@ def transport_rx_description(dw):
 
 # Command Layer
 regs = {
-    "WRITE_DMA_EXT"            : 0x35,
-    "READ_DMA_EXT"            : 0x25,
-    "IDENTIFY_DEVICE"        : 0xEC
+    "WRITE_DMA_EXT":   0x35,
+    "READ_DMA_EXT":    0x25,
+    "IDENTIFY_DEVICE": 0xEC
 }
 
 reg_d2h_status = {
-    "bsy"    :    7,
-    "drdy"    :    6,
-    "df"    :    5,
-    "se"    :    5,
-    "dwe"    :    4,
-    "drq"    :    3,
-    "ae"    :    2,
-    "sns"    :    1,
-    "cc"    :     0,
-    "err"    :    0
+    "bsy":  7,
+    "drdy": 6,
+    "df":   5,
+    "se":   5,
+    "dwe":  4,
+    "drq":  3,
+    "ae":   2,
+    "sns":  1,
+    "cc":   0,
+    "err":  0
 }
 
 
@@ -277,9 +277,9 @@ class BufferizeEndpoints(ModuleTransformer):
         for name, endpoint in endpoints.items():
             if not self.names or name in self.names:
                 if isinstance(endpoint, Sink):
-                    sinks.update({name : endpoint})
+                    sinks.update({name: endpoint})
                 elif isinstance(endpoint, Source):
-                    sources.update({name : endpoint})
+                    sources.update({name: endpoint})
 
         # add buffer on sinks
         for name, sink in sinks.items():

diff --git a/misoclib/mem/litesata/example_designs/test/test_la.py b/misoclib/mem/litesata/example_designs/test/test_la.py
index a16085a20192676fd9df54286a5e0c214ddd1944..130959865de349f268f2467436e6c102630c71e8 100644 (file)
--- a/misoclib/mem/litesata/example_designs/test/test_la.py
+++ b/misoclib/mem/litesata/example_designs/test/test_la.py
@@ -22,27 +22,27 @@ def main(wb):
     conditions = {}
     conditions["now"] = {}
     conditions["id_cmd"] = {
-        "sata_command_tx_sink_stb"                : 1,
-        "sata_command_tx_sink_payload_identify"    : 1,
+        "sata_command_tx_sink_stb": 1,
+        "sata_command_tx_sink_payload_identify": 1,
     }
     conditions["id_resp"] = {
-        "source_source_payload_data" : primitives["X_RDY"],
+        "source_source_payload_data": primitives["X_RDY"],
     }
     conditions["wr_cmd"] = {
-        "sata_command_tx_sink_stb"            : 1,
-        "sata_command_tx_sink_payload_write"    : 1,
+        "sata_command_tx_sink_stb": 1,
+        "sata_command_tx_sink_payload_write": 1,
     }
     conditions["wr_resp"] = {
-        "sata_command_rx_source_stb"            : 1,
-        "sata_command_rx_source_payload_write"    : 1,
+        "sata_command_rx_source_stb": 1,
+        "sata_command_rx_source_payload_write": 1,
     }
     conditions["rd_cmd"] = {
-        "sata_command_tx_sink_stb"            : 1,
-        "sata_command_tx_sink_payload_read"    : 1,
+        "sata_command_tx_sink_stb": 1,
+        "sata_command_tx_sink_payload_read": 1,
     }
     conditions["rd_resp"] = {
-        "sata_command_rx_source_stb"            : 1,
-        "sata_command_rx_source_payload_read"    : 1,
+        "sata_command_rx_source_stb": 1,
+        "sata_command_rx_source_payload_read": 1,
     }
 
     la.configure_term(port=0, cond=conditions[trig])

diff --git a/misoclib/mem/litesata/example_designs/test/tools.py b/misoclib/mem/litesata/example_designs/test/tools.py
index ebaf4b01c4e3efdf6b3197b8573738cd8d0eb95e..6afd3df5979327e78498fd1ba5fbd7a4d89ca281 100644 (file)
--- a/misoclib/mem/litesata/example_designs/test/tools.py
+++ b/misoclib/mem/litesata/example_designs/test/tools.py
@@ -1,20 +1,20 @@
 from litescope.host.dump import *
 
 primitives = {
-    "ALIGN"    :    0x7B4A4ABC,
-    "CONT"    :     0X9999AA7C,
-    "SYNC"    :    0xB5B5957C,
-    "R_RDY"    :    0x4A4A957C,
-    "R_OK"    :    0x3535B57C,
-    "R_ERR"    :    0x5656B57C,
-    "R_IP"    :    0X5555B57C,
-    "X_RDY"    :    0x5757B57C,
-    "CONT"    :    0x9999AA7C,
-    "WTRM"    :    0x5858B57C,
-    "SOF"    :    0x3737B57C,
-    "EOF"    :    0xD5D5B57C,
-    "HOLD"    :    0xD5D5AA7C,
-    "HOLDA"    :     0X9595AA7C
+    "ALIGN":  0x7B4A4ABC,
+    "CONT":   0X9999AA7C,
+    "SYNC":   0xB5B5957C,
+    "R_RDY":  0x4A4A957C,
+    "R_OK":   0x3535B57C,
+    "R_ERR":  0x5656B57C,
+    "R_IP":   0X5555B57C,
+    "X_RDY":  0x5757B57C,
+    "CONT":   0x9999AA7C,
+    "WTRM":   0x5858B57C,
+    "SOF":    0x3737B57C,
+    "EOF":    0xD5D5B57C,
+    "HOLD":   0xD5D5AA7C,
+    "HOLDA":  0X9595AA7C
 }
 
 

diff --git a/misoclib/mem/litesata/phy/k7/crg.py b/misoclib/mem/litesata/phy/k7/crg.py
index 380f19ee68673c39db2776c2603321b246238bd2..86aeb86cb977df00f65cbdd2f79070a9d1518bdd 100644 (file)
--- a/misoclib/mem/litesata/phy/k7/crg.py
+++ b/misoclib/mem/litesata/phy/k7/crg.py
@@ -31,9 +31,9 @@ class K7LiteSATAPHYCRG(Module):
         mmcm_clk_i = Signal()
         mmcm_clk0_o = Signal()
         mmcm_div_config = {
-            "sata_gen1" :     16.0,
-            "sata_gen2" :    8.0,
-            "sata_gen3" :     4.0
+            "sata_gen1":     16.0,
+            "sata_gen2":    8.0,
+            "sata_gen3":     4.0
             }
         mmcm_div = mmcm_div_config[revision]
         self.specials += [

diff --git a/misoclib/mem/litesata/phy/k7/trx.py b/misoclib/mem/litesata/phy/k7/trx.py
index 71eae0801e844df19e79ee46626c424bd77ef612..72da64bf674e7529942bd2acf60981719dde73ed 100644 (file)
--- a/misoclib/mem/litesata/phy/k7/trx.py
+++ b/misoclib/mem/litesata/phy/k7/trx.py
@@ -105,17 +105,17 @@ class K7LiteSATAPHYTRX(Module):
 
     # Config at startup
         div_config = {
-            "sata_gen1" :     4,
-            "sata_gen2" :    2,
-            "sata_gen3" :     1
+            "sata_gen1": 4,
+            "sata_gen2": 2,
+            "sata_gen3": 1
             }
         rxout_div = div_config[revision]
         txout_div = div_config[revision]
 
         cdr_config = {
-            "sata_gen1" :    0x0380008BFF40100008,
-            "sata_gen2" :    0x0388008BFF40200008,
-            "sata_gen3" :    0X0380008BFF10200010
+            "sata_gen1": 0x0380008BFF40100008,
+            "sata_gen2": 0x0388008BFF40200008,
+            "sata_gen3": 0X0380008BFF10200010
         }
         rxcdr_cfg = cdr_config[revision]