fromIEW->mispredictInst[tid];
toIEW->commitInfo[tid].branchTaken =
fromIEW->branchTaken[tid];
- toIEW->commitInfo[tid].squashInst = NULL;
+ toIEW->commitInfo[tid].squashInst =
+ rob->findInst(tid, squashed_inst);
toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
// StaticInst from the rom, the current macroop, or what's already
// in the predecoder.
bool needMem = !inRom && !curMacroop && !predecoder.extMachInstReady();
+ fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
+ Addr block_PC = icacheBlockAlignPC(fetchAddr);
if (needMem) {
+ // If buffer is no longer valid or fetchAddr has moved to point
+ // to the next cache block then start fetch from icache.
+ if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid])
+ break;
+
if (blkOffset >= numInsts) {
// We need to process more memory, but we've run out of the
// current block.
*/
DynInstPtr readHeadInst(ThreadID tid);
+ /** Returns a pointer to the instruction with the given sequence if it is
+ * in the ROB.
+ */
+ DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst);
+
/** Returns pointer to the tail instruction within the ROB. There is
* no guarantee as to the return value if the ROB is empty.
* @retval Pointer to the DynInst that is at the tail of the ROB.
.desc("The number of ROB writes");
}
+template <class Impl>
+typename Impl::DynInstPtr
+ROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst)
+{
+ for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++) {
+ if ((*it)->seqNum == squash_inst) {
+ return *it;
+ }
+ }
+ return NULL;
+}