src_reg(struct ::brw_reg reg);
bool equals(const src_reg &r) const;
+ bool negative_equals(const src_reg &r) const;
src_reg(class vec4_visitor *v, const struct glsl_type *type);
src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
return a->bits == b->bits && (df ? a->u64 == b->u64 : a->ud == b->ud);
}
+static inline bool
+brw_regs_negative_equal(const struct brw_reg *a, const struct brw_reg *b)
+{
+ if (a->file == IMM) {
+ if (a->bits != b->bits)
+ return false;
+
+ switch (a->type) {
+ case BRW_REGISTER_TYPE_UQ:
+ case BRW_REGISTER_TYPE_Q:
+ return a->d64 == -b->d64;
+ case BRW_REGISTER_TYPE_DF:
+ return a->df == -b->df;
+ case BRW_REGISTER_TYPE_UD:
+ case BRW_REGISTER_TYPE_D:
+ return a->d == -b->d;
+ case BRW_REGISTER_TYPE_F:
+ return a->f == -b->f;
+ case BRW_REGISTER_TYPE_VF:
+ /* It is tempting to treat 0 as a negation of 0 (and -0 as a negation
+ * of -0). There are occasions where 0 or -0 is used and the exact
+ * bit pattern is desired. At the very least, changing this to allow
+ * 0 as a negation of 0 causes some fp64 tests to fail on IVB.
+ */
+ return a->ud == (b->ud ^ 0x80808080);
+ case BRW_REGISTER_TYPE_UW:
+ case BRW_REGISTER_TYPE_W:
+ case BRW_REGISTER_TYPE_UV:
+ case BRW_REGISTER_TYPE_V:
+ case BRW_REGISTER_TYPE_HF:
+ /* FINISHME: Implement support for these types once there is
+ * something in the compiler that can generate them. Until then,
+ * they cannot be tested.
+ */
+ return false;
+ case BRW_REGISTER_TYPE_UB:
+ case BRW_REGISTER_TYPE_B:
+ case BRW_REGISTER_TYPE_NF:
+ unreachable("not reached");
+ }
+ } else {
+ struct brw_reg tmp = *a;
+
+ tmp.negate = !tmp.negate;
+
+ return brw_regs_equal(&tmp, b);
+ }
+}
+
struct brw_indirect {
unsigned addr_subnr:4;
int addr_offset:10;