mips.md (div_trap_normal): Don't ask for the REGNO of (const_int 0)...

* config/mips/mips.md (div_trap_normal): Don't ask for the REGNO
of (const_int 0), when what we really care about is
whether it's a zero constant anyway.
(div_trap_mips16): Likewise.

From-SVN: r30648

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 55f7c7a653ddf2a5a0ae7419f12a81c51118896f..d0ae9ba9937b83014a276eb062d0e90c9ba1883f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+1999-11-24  Geoffrey Keating  <geoffk@cygnus.com>
+
+       * config/mips/mips.md (div_trap_normal): Don't ask for the REGNO
+       of (const_int 0), when what we really care about is
+       whether it's a zero constant anyway.
+       (div_trap_mips16): Likewise.
+
 1999-11-23  Mark Mitchell  <mark@codesourcery.com>
 
        * loop.c (loop_optimize): Always find_loop_tree_blocks and

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 923fcbf7f6015786772117850647efab3f43e9b2..c909a134d65b02bd3677b6299eb7e23ee7dbbd93 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -2395,8 +2395,8 @@
 }")
 
 (define_insn "div_trap_normal"
-  [(trap_if (eq (match_operand 0 "register_operand" "d")
-               (match_operand 1 "true_reg_or_0_operand" "dJ"))
+  [(trap_if (eq (match_operand 0 "register_operand" "d,d")
+               (match_operand 1 "true_reg_or_0_operand" "d,J"))
             (match_operand 2 "immediate_operand" ""))]
   "!TARGET_MIPS16"
   "*
@@ -2411,20 +2411,20 @@
     if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
         && GET_CODE (XEXP (link, 0)) == INSN
         && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
-       && REGNO (operands[1]) == 0)
+       && which_alternative == 1)
       have_dep_anti = 1;
   if (! have_dep_anti)
     {
       if (GENERATE_BRANCHLIKELY)
        {
-          if (GET_CODE (operands[1]) == CONST_INT)
+          if (which_alternative == 1)
            return \"%(beql\\t%0,$0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
          else
            return \"%(beql\\t%0,%1,1f\\n\\tbreak\\t%2\\n%~1:%)\";
        }
       else
        {
-          if (GET_CODE (operands[1]) == CONST_INT)
+          if (which_alternative == 1)
            return \"%(bne\\t%0,$0,1f\\n\\tnop\\n\\tbreak\\t%2\\n%~1:%)\";
          else
            return \"%(bne\\t%0,%1,1f\\n\\tnop\\n\\tbreak\\t%2\\n%~1:%)\";
@@ -2439,8 +2439,8 @@
 ;; The mips16 bne insns is a macro which uses reg 24 as an intermediate.
 
 (define_insn "div_trap_mips16"
-  [(trap_if (eq (match_operand 0 "register_operand" "d")
-               (match_operand 1 "true_reg_or_0_operand" "dJ"))
+  [(trap_if (eq (match_operand 0 "register_operand" "d,d")
+               (match_operand 1 "true_reg_or_0_operand" "d,J"))
             (match_operand 2 "immediate_operand" ""))
    (clobber (reg:SI 24))]
   "TARGET_MIPS16"
@@ -2456,12 +2456,12 @@
     if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
         && GET_CODE (XEXP (link, 0)) == INSN
         && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
-       && REGNO (operands[1]) == 0)
+       && which_alternative == 1)
       have_dep_anti = 1;
   if (! have_dep_anti)
     {
       /* No branch delay slots on mips16. */ 
-      if (GET_CODE (operands[1]) == CONST_INT)
+      if (which_alternative == 1)
         return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
       else
         return \"%(bne\\t%0,%1,1f\\n\\tbreak\\t%2\\n%~1:%)\";