// Copy the misc regs.
TheISA::copyMiscRegs(tc, this);
- // Then finally set the PC and the next PC.
+ // Then finally set the PC, the next PC, the nextNPC, the micropc, and the
+ // next micropc.
cpu->setPC(tc->readPC(), tid);
cpu->setNextPC(tc->readNextPC(), tid);
+ cpu->setNextNPC(tc->readNextNPC(), tid);
+ cpu->setMicroPC(tc->readMicroPC(), tid);
+ cpu->setNextMicroPC(tc->readNextMicroPC(), tid);
#if !FULL_SYSTEM
this->thread->funcExeInst = tc->readFuncExeInst();
#endif
TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
{
+ reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
switch(width) {
case 32:
return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx)
{
+ reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
}
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
{
DPRINTF(Fault, "Reading floatint register through the TC!\n");
+ reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
}
TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
{
+ reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
}
void
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
{
+ reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
switch(width) {
case 32:
cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
void
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
{
+ reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
if (!thread->trapPending && !thread->inSyscall) {
int width)
{
DPRINTF(Fault, "Setting floatint register through the TC!\n");
+ reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
// Squash if we're not already in a state update mode.
void
O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
+ reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
// Squash if we're not already in a state update mode.
}
}
+template <class Impl>
+void
+O3ThreadContext<Impl>::setMicroPC(uint64_t val)
+{
+ cpu->setMicroPC(val, thread->readTid());
+
+ // Squash if we're not already in a state update mode.
+ if (!thread->trapPending && !thread->inSyscall) {
+ cpu->squashFromTC(thread->readTid());
+ }
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
+{
+ cpu->setNextMicroPC(val, thread->readTid());
+
+ // Squash if we're not already in a state update mode.
+ if (!thread->trapPending && !thread->inSyscall) {
+ cpu->squashFromTC(thread->readTid());
+ }
+}
+
template <class Impl>
void
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)