Cray-style variable-length Vectors on the other hand result in
stunningly elegant and small loops, exceptionally high data throughput
-per instruction (by one *or greater* orders of magnitude), with no alarmingly high setup and cleanup code, where
+per instruction (by one *or greater* orders of magnitude than SIMD), with no alarmingly high setup and cleanup code, where
at the hardware level the microarchitecture may execute from one element
right the way through to tens of thousands at a time, yet the executable
remains exactly the same and the ISA remains clear, true to the RISC