As per @daveshah1 remove async DFF timing from xilinx

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index a4182ed63e9d23f2de568a2e6123dd74c006800c..8a48bad4e53edf9804e96c95523b64e091215f68 100644 (file)
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -54,9 +54,9 @@ FDSE 7 0 4 1
 # Inputs: C CE CLR D
 # Outputs: Q
 FDCE 8 0 4 1
-- - 404 -
+- - - -
 
 # Inputs: C CE D PRE
 # Outputs: Q
 FDPE 9 0 4 1
-- - - 404
+- - - -