(no commit message)

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index ca67cc98d03f0cf1d6a89d95838c4a3a6c7d2d00..9b6a5a82c004aa89505c1966d1f13accd4489a2b 100644 (file)
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -215,7 +215,7 @@ Special Registers Altered:
     SVSTATE
 ```
 
-`svremap` determines the relationship between registers and SVSHAPE SPRs.
+`svremap` establishes the connection between registers and SVSHAPE SPRs.
 The bitmask `SVme` determines which registers have a REMAP applied, and mi0-mo1
 determine which shape is applied to an activated register.  the `pst` bit if
 cleared indicated that the REMAP operation shall only apply to the immediately-following
@@ -231,7 +231,8 @@ the bits 32 to 46 will at least have been set in SVSTATE. This may prove useful
 when using `svindex` or `svshape2`.
 
 Hardware Architectural Note: when persistence is not set it is critically important
-to treat the `svremap` and the following SVP64 instruction as an indivisible fused operation.
+to treat the `svremap` and the immediately-following SVP64 instruction as an
+indivisible fused operation.
 *No state* is stored in the SVSTATE SPR in order to allow continuation should an
 Interrupt occur between the two instructions. Thus, Interrupts must be prohibited
 from occurring or other workaround deployed.  When persistence is set this issue
@@ -248,9 +249,11 @@ to activate REMAP on any given (following) instruction.  If persistence is set h
 # SHAPE Remapping SPRs
 
 There are four "shape" SPRs, SHAPE0-3, 32-bits in each,
-which have the same format.  
+which have the same format.  It is possible to write directly to these
+SPRs but it is recommended to use the Management instructions
+`svshape`, `svshape2` or `svindex`.
 
-Shape is 32-bits.  When SHAPE is set entirely to zeros, remapping is
+When SHAPE is set entirely to zeros, remapping is
 disabled: the register's elements are a linear (1D) vector.
 
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