}
/* Set up color TS to source surface before blit, if needed */
+ bool source_ts_valid = false;
if (src->levels[blit_info->src.level].ts_size &&
src->levels[blit_info->src.level].ts_valid) {
struct etna_reloc reloc;
etna_set_state(ctx->stream, VIVS_TS_COLOR_CLEAR_VALUE,
src->levels[blit_info->src.level].clear_value);
+
+ source_ts_valid = true;
} else {
etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG, ts_mem_config);
}
.source_stride = src_lev->stride,
.source_padded_width = src_lev->padded_width,
.source_padded_height = src_lev->padded_height,
+ .source_ts_valid = source_ts_valid,
.dest_format = translate_rs_format(dst_format),
.dest_tiling = dst->layout,
.dest = dst->bo,
struct etna_cmd_stream *stream = ctx->stream;
struct etna_coalesce coalesce;
+ if (cs->RS_KICKER_INPLACE && !cs->source_ts_valid)
+ /* Inplace resolve is no-op if TS is not configured */
+ return;
+
ctx->stats.rs_operations++;
if (cs->RS_KICKER_INPLACE) {
struct rs_state {
uint8_t downsample_x : 1; /* Downsample in x direction */
uint8_t downsample_y : 1; /* Downsample in y direction */
+ uint8_t source_ts_valid : 1;
uint8_t source_format; /* RS_FORMAT_XXX */
uint8_t source_tiling; /* ETNA_LAYOUT_XXX */
/* treat this as opaque structure */
struct compiled_rs_state {
+ uint8_t source_ts_valid : 1;
uint32_t RS_CONFIG;
uint32_t RS_SOURCE_STRIDE;
uint32_t RS_DEST_STRIDE;