macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
if (mips_opts.noat)
- as_warn (_("Macro used $at after \".set noat\""));
+ as_bad (_("Macro used $at after \".set noat\""));
}
}
}
else
abort ();
+
+ if (mips_opts.noat && *used_at == 1)
+ as_bad (_("Macro used $at after \".set noat\""));
}
/* Move the contents of register SOURCE into register DEST. */
macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
--mips_opts.noreorder;
- return;
+ break;
case M_ADD_I:
s = "addi";
&& imm_expr.X_add_number < 0x8000)
{
macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
- return;
+ break;
}
+ used_at = 1;
load_register (AT, &imm_expr, dbl);
macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
break;
treg, sreg, BFD_RELOC_LO16);
macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
}
- return;
+ break;
}
+ used_at = 1;
load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
break;
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
macro_build (&offset_expr, s, "s,t,p", sreg, 0);
- return;
+ break;
}
+ used_at = 1;
load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build (&offset_expr, s, "s,t,p", sreg, AT);
break;
if (treg == 0)
{
macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
- return;
+ break;
}
if (sreg == 0)
{
macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
macro_build (NULL, "nop", "", 0);
else
macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
- return;
+ break;
}
if (imm_expr.X_op != O_constant)
as_bad (_("Unsupported large constant"));
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
- return;
+ break;
}
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
{
macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
- return;
+ break;
}
maxnum = 0x7fffffff;
if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
/* result is always true */
as_warn (_("Branch %s is always true"), ip->insn_mo->name);
macro_build (&offset_expr, "b", "p");
- return;
+ break;
}
+ used_at = 1;
set_at (sreg, 0);
macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
{
macro_build (&offset_expr, likely ? "beql" : "beq",
"s,t,p", 0, treg);
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
{
macro_build (&offset_expr, likely ? "bnel" : "bne",
"s,t,p", sreg, 0);
- return;
+ break;
}
+ used_at = 1;
set_at (sreg, 1);
macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
if (treg == 0)
{
macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
- return;
+ break;
}
if (sreg == 0)
{
macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
{
macro_build (&offset_expr, likely ? "bnel" : "bne",
"s,t,p", sreg, 0);
- return;
+ break;
}
if (sreg == 0)
goto do_false;
+ used_at = 1;
macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
if (treg == 0)
{
macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
- return;
+ break;
}
if (sreg == 0)
{
macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
- return;
+ break;
}
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
{
macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
- return;
+ break;
}
+ used_at = 1;
set_at (sreg, 0);
macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
{
macro_build (&offset_expr, likely ? "beql" : "beq",
"s,t,p", sreg, 0);
- return;
+ break;
}
if (sreg == 0)
goto do_true;
+ used_at = 1;
macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
{
macro_build (&offset_expr, likely ? "beql" : "beq",
"s,t,p", sreg, 0);
- return;
+ break;
}
+ used_at = 1;
set_at (sreg, 1);
macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
if (treg == 0)
{
macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
- return;
+ break;
}
if (sreg == 0)
{
macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
{
macro_build (&offset_expr, likely ? "bnel" : "bne",
"s,t,p", 0, treg);
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
}
macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
}
- return;
+ break;
case M_DINS:
{
macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
pos + size - 1);
}
- return;
+ break;
case M_DDIV_3:
dbl = 1;
macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
else
macro_build (NULL, "break", "c", 7);
- return;
+ break;
}
mips_emit_delays (TRUE);
macro_build (NULL, "break", "c", 7);
}
expr1.X_add_number = -1;
+ used_at = 1;
load_register (AT, &expr1, dbl);
expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
macro_build (&expr1, "bne", "s,t,p", treg, AT);
macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
else
macro_build (NULL, "break", "c", 7);
- return;
+ break;
}
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
{
move_register (dreg, sreg);
else
move_register (dreg, 0);
- return;
+ break;
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number == -1
}
else
move_register (dreg, 0);
- return;
+ break;
}
+ used_at = 1;
load_register (AT, &imm_expr, dbl);
macro_build (NULL, s, "z,s,t", sreg, AT);
macro_build (NULL, s2, "d", dreg);
macro_build (NULL, "break", "c", 7);
}
macro_build (NULL, s2, "d", dreg);
- return;
+ break;
case M_DLCA_AB:
dbl = 1;
macro_build (&offset_expr,
(dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
"t,r,j", treg, sreg, BFD_RELOC_LO16);
- return;
+ break;
}
if (!mips_opts.noat && (treg == breg))
AT, AT, BFD_RELOC_LO16);
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, AT);
+ used_at = 1;
}
relax_end ();
}
macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
}
-
- if (!used_at)
- return;
-
break;
case M_J_A:
macro_build (&offset_expr, "j", "a");
else
macro_build (&offset_expr, "b", "p");
- return;
+ break;
/* The jal instructions must be handled as macros because when
generating PIC code they expand to multi-instruction
else
abort ();
- return;
+ break;
case M_JAL_A:
if (mips_pic == NO_PIC)
else
abort ();
- return;
+ break;
case M_LB_AB:
s = "lb";
if (mips_opts.arch == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
- return;
+ break;
}
s = "ldc1";
/* Itbl support may require additional care here. */
case M_LWU_AB:
s = "lwu";
ld:
- /* XXX Why don't we try to use AT for all expansions? */
- if (!mips_opts.noat && (breg == treg || coproc || lr))
+ if (breg == treg || coproc || lr)
{
tempreg = AT;
used_at = 1;
}
- else if (breg == treg
- && (offset_expr.X_op != O_constant
- || (offset_expr.X_add_number > 0x7fff
- || offset_expr.X_add_number < -0x8000)))
- {
- as_bad(_("load expansion needs $at register"));
- }
else
{
tempreg = treg;
- used_at = 0;
}
goto ld_st;
case M_SB_AB:
if (mips_opts.arch == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
- return;
+ break;
}
s = "sdc1";
coproc = 1;
case M_SDR_AB:
s = "sdr";
st:
- if (!mips_opts.noat)
- {
- tempreg = AT;
- used_at = 1;
- }
- else if (breg == treg
- && (offset_expr.X_op != O_constant
- || (offset_expr.X_add_number > 0x7fff
- || offset_expr.X_add_number < -0x8000)))
- {
- as_bad(_("store expansion needs $at register"));
- }
- else
- {
- tempreg = treg;
- used_at = 0;
- }
+ tempreg = AT;
+ used_at = 1;
ld_st:
/* Itbl support may require additional care here. */
if (mask == M_LWC1_AB
macro_build (&offset_expr, s, fmt, treg,
BFD_RELOC_LO16, tempreg);
}
-
- if (used_at)
- break;
-
- return;
+ break;
}
if (offset_expr.X_op == O_constant
tempreg, tempreg, breg);
macro_build (&offset_expr, s, fmt, treg,
BFD_RELOC_MIPS_GOT_OFST, tempreg);
-
- if (!used_at)
- return;
-
break;
}
expr1.X_add_number = offset_expr.X_add_number;
else
abort ();
- if (!used_at)
- return;
-
break;
case M_LI:
case M_LI_S:
load_register (treg, &imm_expr, 0);
- return;
+ break;
case M_DLI:
load_register (treg, &imm_expr, 1);
- return;
+ break;
case M_LI_SS:
if (imm_expr.X_op == O_constant)
{
+ used_at = 1;
load_register (AT, &imm_expr, 0);
macro_build (NULL, "mtc1", "t,G", AT, treg);
break;
&& offset_expr.X_add_number == 0);
macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
BFD_RELOC_MIPS_LITERAL, mips_gp_register);
- return;
+ break;
}
case M_LI_D:
}
}
}
- return;
+ break;
}
/* We know that sym is in the .rdata section. First we get the
if (mips_pic == NO_PIC)
{
macro_build_lui (&offset_expr, AT);
+ used_at = 1;
}
else if (mips_pic == SVR4_PIC)
{
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
BFD_RELOC_MIPS_GOT16, mips_gp_register);
+ used_at = 1;
}
else
abort ();
/* Now we load the register(s). */
if (HAVE_64BIT_GPRS)
- macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
+ {
+ used_at = 1;
+ macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
+ }
else
{
+ used_at = 1;
macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
if (treg != RA)
{
OFFSET_EXPR. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
+ used_at = 1;
load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
if (HAVE_64BIT_FPRS)
{
{
macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
BFD_RELOC_MIPS_LITERAL, mips_gp_register);
- return;
+ break;
}
breg = mips_gp_register;
r = BFD_RELOC_MIPS_LITERAL;
else
{
assert (strcmp (s, RDATA_SECTION_NAME) == 0);
+ used_at = 1;
if (mips_pic == SVR4_PIC)
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
BFD_RELOC_MIPS_GOT16, mips_gp_register);
if (mips_opts.arch == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
- return;
+ break;
}
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when loading from memory. */
offset_expr.X_add_number += 4;
macro_build (&offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg : treg + 1, r, breg);
-
- if (breg != AT)
- return;
break;
case M_L_DAB:
if (mips_opts.arch == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
- return;
+ break;
}
/* Itbl support may require additional care here. */
coproc = 1;
if (mips_opts.arch == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
- return;
+ break;
}
if (mips_opts.isa != ISA_MIPS1)
offset_expr.X_op = O_constant;
}
}
+ used_at = 1;
macro_build_lui (&offset_expr, AT);
if (breg != 0)
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
else
abort ();
- if (!used_at)
- return;
-
break;
case M_LD_OB:
macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
offset_expr.X_add_number += 4;
macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
- return;
+ break;
/* New code added to support COPZ instructions.
This code builds table entries out of the macros in mip_opcodes.
/* For now we just do C (same as Cz). The parameter will be
stored in insn_opcode by mips_ip. */
macro_build (NULL, s, "C", ip->insn_opcode);
- return;
+ break;
case M_MOVE:
move_register (dreg, sreg);
- return;
+ break;
#ifdef LOSING_COMPILER
default:
s2 = "cop3";
coproc = ITBL_DECODE_PNUM (immed_expr);;
macro_build (&immed_expr, s, "C");
- return;
+ break;
}
macro2 (ip);
- return;
+ break;
}
- if (mips_opts.noat)
- as_warn (_("Macro used $at after \".set noat\""));
+ if (mips_opts.noat && used_at)
+ as_bad (_("Macro used $at after \".set noat\""));
}
static void
case M_MUL:
macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
macro_build (NULL, "mflo", "d", dreg);
- return;
+ break;
case M_DMUL_I:
dbl = 1;
/* The MIPS assembler some times generates shifts and adds. I'm
not trying to be that fancy. GCC should do this for us
anyway. */
+ used_at = 1;
load_register (AT, &imm_expr, dbl);
macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
macro_build (NULL, "mflo", "d", dreg);
mips_emit_delays (TRUE);
++mips_opts.noreorder;
mips_any_noreorder = 1;
+ used_at = 1;
if (imm)
load_register (AT, &imm_expr, dbl);
macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
mips_emit_delays (TRUE);
++mips_opts.noreorder;
mips_any_noreorder = 1;
+ used_at = 1;
if (imm)
load_register (AT, &imm_expr, dbl);
macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
}
macro_build (NULL, "dnegu", "d,w", tempreg, treg);
macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
- if (used_at)
- break;
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
}
macro_build (NULL, "negu", "d,w", tempreg, treg);
macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
- if (used_at)
- break;
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
else
macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
- return;
+ break;
}
if (rot == 0)
{
macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
- return;
+ break;
}
l = (rot < 0x20) ? "dsll" : "dsll32";
r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
rot &= 0x1f;
+ used_at = 1;
macro_build (NULL, l, "d,w,<", AT, sreg, rot);
macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
{
macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
- return;
+ break;
}
if (rot == 0)
{
macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
{
macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
{
macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
else
macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
- return;
+ break;
}
if (rot == 0)
{
macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
- return;
+ break;
}
r = (rot < 0x20) ? "dsrl" : "dsrl32";
l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
rot &= 0x1f;
+ used_at = 1;
macro_build (NULL, r, "d,w,<", AT, sreg, rot);
macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
{
macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
- return;
+ break;
}
if (rot == 0)
{
macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
- return;
+ break;
}
+ used_at = 1;
macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
if (mips_opts.arch == CPU_R4650)
{
as_bad (_("opcode not supported on this processor"));
- return;
+ break;
}
assert (mips_opts.isa == ISA_MIPS1);
/* Even on a big endian machine $fn comes before $fn+1. We have
offset_expr.X_add_number += 4;
macro_build (&offset_expr, "swc1", "T,o(b)",
target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
- return;
+ break;
case M_SEQ:
if (sreg == 0)
macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
}
- return;
+ break;
case M_SEQ_I:
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
- return;
+ break;
}
if (sreg == 0)
{
as_warn (_("Instruction %s: result is always false"),
ip->insn_mo->name);
move_register (dreg, 0);
- return;
+ break;
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= 0
used_at = 1;
}
macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
- if (used_at)
- break;
- return;
+ break;
case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
s = "slt";
sge:
macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
- return;
+ break;
case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
case M_SGEU_I:
used_at = 1;
}
macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
- if (used_at)
- break;
- return;
+ break;
case M_SGT: /* sreg > treg <==> treg < sreg */
s = "slt";
s = "sltu";
sgt:
macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
- return;
+ break;
case M_SGT_I: /* sreg > I <==> I < sreg */
s = "slt";
case M_SGTU_I:
s = "sltu";
sgti:
+ used_at = 1;
load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
break;
sle:
macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
- return;
+ break;
case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
s = "slt";
case M_SLEU_I:
s = "sltu";
slei:
+ used_at = 1;
load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
&& imm_expr.X_add_number < 0x8000)
{
macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
- return;
+ break;
}
+ used_at = 1;
load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
break;
{
macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
BFD_RELOC_LO16);
- return;
+ break;
}
+ used_at = 1;
load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
break;
macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
}
- return;
+ break;
case M_SNE_I:
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
- return;
+ break;
}
if (sreg == 0)
{
ip->insn_mo->name);
macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
dreg, 0, BFD_RELOC_LO16);
- return;
+ break;
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= 0
used_at = 1;
}
macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
- if (used_at)
- break;
- return;
+ break;
case M_DSUB_I:
dbl = 1;
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
dreg, sreg, BFD_RELOC_LO16);
- return;
+ break;
}
+ used_at = 1;
load_register (AT, &imm_expr, dbl);
macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
break;
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
dreg, sreg, BFD_RELOC_LO16);
- return;
+ break;
}
+ used_at = 1;
load_register (AT, &imm_expr, dbl);
macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
break;
case M_TNE_I:
s = "tne";
trap:
+ used_at = 1;
load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
macro_build (NULL, s, "s,t", sreg, AT);
break;
case M_TRUNCWS:
case M_TRUNCWD:
assert (mips_opts.isa == ISA_MIPS1);
+ used_at = 1;
sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
case M_ULHU:
s = "lbu";
ulh:
+ used_at = 1;
if (offset_expr.X_add_number >= 0x7fff)
as_bad (_("operand overflow"));
if (! target_big_endian)
if (treg != breg)
tempreg = treg;
else
- tempreg = AT;
+ {
+ used_at = 1;
+ tempreg = AT;
+ }
if (! target_big_endian)
offset_expr.X_add_number += off;
macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
/* If necessary, move the result in tempreg the final destination. */
if (treg == tempreg)
- return;
+ break;
/* Protect second load's delay slot. */
load_delay_nop ();
move_register (treg, tempreg);
break;
case M_USH:
+ used_at = 1;
if (offset_expr.X_add_number >= 0x7fff)
as_bad (_("operand overflow"));
if (target_big_endian)
else
offset_expr.X_add_number += off;
macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
- return;
+ break;
case M_USD_A:
s = "sdl";
as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
break;
}
- if (mips_opts.noat)
- as_warn (_("Macro used $at after \".set noat\""));
+ if (mips_opts.noat && used_at)
+ as_bad (_("Macro used $at after \".set noat\""));
}
/* Implement macros in mips16 mode. */
case M_MUL:
macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
macro_build (NULL, "mflo", "x", zreg);
- return;
+ break;
case M_DSUBU_I:
dbl = 1;