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add MSR to ldst operand debug gtkw
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 10 Nov 2021 19:05:49 +0000 (19:05 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 10 Nov 2021 19:05:49 +0000 (19:05 +0000)
src/openpower/test/runner.py patch | blob | history

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index dd59e9faf5774a5218c2d068ab3d7406b04f26b5..c429ee14bea49b69412444964773d42e67ac6cc0 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -381,6 +381,7 @@ class TestRunnerBase(FHDLTestCase):
 
         traces += [('ld/st port interface', {'submodule': pi_module}, [
             'oper_r__insn_type',
+            'oper_r__msr',
             'ldst_port0_is_ld_i',
             'ldst_port0_is_st_i',
             'ldst_port0_busy_o',