gm107/ir: optimize 32-bit CONST load to mov

This is not allowed for indirect accesses because the source
GPR might be erased by a subsequent instruction (WaR hazard)
if we don't emit a read dep bar.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
index 84ef4e0fb7d38f5e73884863b80bb1ee787b9b8c..371ebae40c19db4e81b1e968426e5d053b64aa27 100644 (file)
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
@@ -61,6 +61,19 @@ GM107LegalizeSSA::handlePFETCH(Instruction *i)
    i->setSrc(1, NULL);
 }
 
+void
+GM107LegalizeSSA::handleLOAD(Instruction *i)
+{
+   if (i->src(0).getFile() != FILE_MEMORY_CONST)
+      return;
+   if (i->src(0).isIndirect(0))
+      return;
+   if (typeSizeof(i->dType) != 4)
+      return;
+
+   i->op = OP_MOV;
+}
+
 bool
 GM107LegalizeSSA::visit(Instruction *i)
 {
@@ -68,6 +81,9 @@ GM107LegalizeSSA::visit(Instruction *i)
    case OP_PFETCH:
       handlePFETCH(i);
       break;
+   case OP_LOAD:
+      handleLOAD(i);
+      break;
    default:
       break;
    }

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
index 81749bf57edf9ddeae7e819870770945ca36d41c..d0737beda679615fcb7e3788634e857a8a87dab0 100644 (file)
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
@@ -21,6 +21,7 @@ private:
    virtual bool visit(Instruction *);
 
    void handlePFETCH(Instruction *);
+   void handleLOAD(Instruction *);
 };
 
 } // namespace nv50_ir