---------- Begin Simulation Statistics ----------
-sim_seconds 1.902683 # Number of seconds simulated
-sim_ticks 1902682770000 # Number of ticks simulated
-final_tick 1902682770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.898954 # Number of seconds simulated
+sim_ticks 1898954186500 # Number of ticks simulated
+final_tick 1898954186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 192931 # Simulator instruction rate (inst/s)
-host_op_rate 192931 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6436506827 # Simulator tick rate (ticks/s)
-host_mem_usage 296908 # Number of bytes of host memory used
-host_seconds 295.61 # Real time elapsed on the host
-sim_insts 57032045 # Number of instructions simulated
-sim_ops 57032045 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 906816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24518592 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 73984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 789824 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28940032 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 906816 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 73984 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 980800 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7895360 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7895360 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 14169 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 383103 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1156 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 12341 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 452188 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 123365 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 123365 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 476599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12886327 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1393199 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 38884 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 415111 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15210119 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 476599 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 38884 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 515483 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4149593 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4149593 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4149593 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 476599 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12886327 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1393199 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 38884 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 415111 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19359713 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 345291 # number of replacements
-system.l2c.tagsinuse 65280.360301 # Cycle average of tags in use
-system.l2c.total_refs 2575351 # Total number of references to valid blocks.
-system.l2c.sampled_refs 410382 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.275497 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 6143524000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 53635.672684 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5378.326569 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 6042.958234 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 144.667579 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 78.735234 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.818415 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.082067 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.092208 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.002207 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.001201 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.996099 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 798441 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 696934 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 292090 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 99595 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1887060 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 812223 # number of Writeback hits
-system.l2c.Writeback_hits::total 812223 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 566 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 46 # number of SCUpgradeReq hits
+host_inst_rate 93254 # Simulator instruction rate (inst/s)
+host_op_rate 93254 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3072830921 # Simulator tick rate (ticks/s)
+host_mem_usage 330780 # Number of bytes of host memory used
+host_seconds 617.98 # Real time elapsed on the host
+sim_insts 57629320 # Number of instructions simulated
+sim_ops 57629320 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 946048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24721152 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 36608 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 493888 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28848320 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 946048 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 36608 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 982656 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7831936 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7831936 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 14782 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 386268 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 572 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 7717 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 450755 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 122374 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 122374 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 498194 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 13018298 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1395834 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 19278 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 260084 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15191688 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 498194 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 19278 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 517472 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4124342 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4124342 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4124342 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 498194 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 13018298 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1395834 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 19278 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 260084 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19316030 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 450755 # Total number of read requests seen
+system.physmem.writeReqs 122374 # Total number of write requests seen
+system.physmem.cpureqs 604625 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28848320 # Total number of bytes read from memory
+system.physmem.bytesWritten 7831936 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28848320 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7831936 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 7306 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28435 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28036 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28258 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 28415 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 28091 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 28033 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 28162 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28315 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27858 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28248 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 28366 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 28107 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 28166 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 28158 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 28038 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7848 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7611 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7694 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7488 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7537 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7442 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7588 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7788 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7389 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7747 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7895 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7671 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7728 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7650 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7483 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1898947634000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 450755 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 123146 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 7306 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 322964 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66672 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 31035 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 6570 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2878 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2432 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1794 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1990 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1691 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1963 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1555 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1554 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1804 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1273 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1481 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 919 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 238 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 126 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4068 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 5048 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 5145 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 5193 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5273 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5291 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 5321 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 5321 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 5321 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 5321 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 5321 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 5320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 5320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 5320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5320 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1253 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 273 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 176 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 48 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 6521684939 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13830350939 # Sum of mem lat for all requests
+system.physmem.totBusLat 1802760000 # Total cycles spent in databus access
+system.physmem.totBankLat 5505906000 # Total cycles spent in bank access
+system.physmem.avgQLat 14470.45 # Average queueing delay per request
+system.physmem.avgBankLat 12216.61 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 30687.06 # Average memory access latency
+system.physmem.avgRdBW 15.19 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 15.19 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 4.12 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.12 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.01 # Average read queue length over time
+system.physmem.avgWrQLen 13.13 # Average write queue length over time
+system.physmem.readRowHits 430277 # Number of row buffer hits during reads
+system.physmem.writeRowHits 78021 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 95.47 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes
+system.physmem.avgGap 3313298.81 # Average gap between requests
+system.l2c.replacements 343856 # number of replacements
+system.l2c.tagsinuse 65278.684390 # Cycle average of tags in use
+system.l2c.total_refs 2547974 # Total number of references to valid blocks.
+system.l2c.sampled_refs 408869 # Sample count of references to valid blocks.
+system.l2c.avg_refs 6.231761 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 53716.705985 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 5434.737424 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 5906.149934 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 139.277407 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 81.813640 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.819652 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.082928 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.090121 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.002125 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.001248 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.996074 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst 735942 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 661355 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 365668 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 116985 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1879950 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 792215 # number of Writeback hits
+system.l2c.Writeback_hits::total 792215 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 181 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 554 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 735 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 48 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 135544 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 39704 # number of ReadExReq hits
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+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10007.698969 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10060.030036 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59453.322940 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 114397.203146 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 62799.785091 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 48644.579246 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38718.064012 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 55700.059441 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 111549.634263 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40474.601494 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 48644.579246 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38718.064012 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 55700.059441 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 111549.634263 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40474.601494 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 41697 # number of replacements
-system.iocache.tagsinuse 0.492574 # Cycle average of tags in use
+system.iocache.replacements 41694 # number of replacements
+system.iocache.tagsinuse 0.494943 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 41713 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1709348959000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 0.492574 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.030786 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.030786 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 177 # number of ReadReq misses
+system.iocache.warmup_cycle 1705457230000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 0.494943 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.030934 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.030934 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41729 # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses
-system.iocache.overall_misses::total 41729 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 21127998 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 21127998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 11486516806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 11486516806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 11507644804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 11507644804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 11507644804 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 11507644804 # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
+system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
+system.iocache.overall_misses::total 41726 # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide 21041998 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 21041998 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 9500949806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 9500949806 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 9521991804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 9521991804 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 9521991804 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 9521991804 # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119367.220339 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119367.220339 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276437.158404 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 276437.158404 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 275770.921997 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 275770.921997 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 275770.921997 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 200533 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120931.022989 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 120931.022989 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228652.045774 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 228652.045774 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 228202.842448 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 228202.842448 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 228202.842448 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 228202.842448 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 192112 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 24673 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 23026 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8.127629 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 8.343264 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11923998 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 11923998 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9325812806 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 9325812806 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 9337736804 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 9337736804 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 9337736804 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 9337736804 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11993000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 11993000 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338178524 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 7338178524 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 7350171524 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 7350171524 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 7350171524 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 7350171524 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67367.220339 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67367.220339 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224437.158404 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 224437.158404 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68925.287356 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68925.287356 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176602.294089 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 176602.294089 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176153.274313 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 176153.274313 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176153.274313 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 176153.274313 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 8304100 # DTB read hits
-system.cpu0.dtb.read_misses 28307 # DTB read misses
-system.cpu0.dtb.read_acv 549 # DTB read access violations
-system.cpu0.dtb.read_accesses 542239 # DTB read accesses
-system.cpu0.dtb.write_hits 5411904 # DTB write hits
-system.cpu0.dtb.write_misses 5987 # DTB write misses
+system.cpu0.dtb.read_hits 8153093 # DTB read hits
+system.cpu0.dtb.read_misses 30801 # DTB read misses
+system.cpu0.dtb.read_acv 546 # DTB read access violations
+system.cpu0.dtb.read_accesses 631302 # DTB read accesses
+system.cpu0.dtb.write_hits 5186191 # DTB write hits
+system.cpu0.dtb.write_misses 6023 # DTB write misses
system.cpu0.dtb.write_acv 347 # DTB write access violations
-system.cpu0.dtb.write_accesses 182798 # DTB write accesses
-system.cpu0.dtb.data_hits 13716004 # DTB hits
-system.cpu0.dtb.data_misses 34294 # DTB misses
-system.cpu0.dtb.data_acv 896 # DTB access violations
-system.cpu0.dtb.data_accesses 725037 # DTB accesses
-system.cpu0.itb.fetch_hits 908718 # ITB hits
-system.cpu0.itb.fetch_misses 19910 # ITB misses
-system.cpu0.itb.fetch_acv 927 # ITB acv
-system.cpu0.itb.fetch_accesses 928628 # ITB accesses
+system.cpu0.dtb.write_accesses 217125 # DTB write accesses
+system.cpu0.dtb.data_hits 13339284 # DTB hits
+system.cpu0.dtb.data_misses 36824 # DTB misses
+system.cpu0.dtb.data_acv 893 # DTB access violations
+system.cpu0.dtb.data_accesses 848427 # DTB accesses
+system.cpu0.itb.fetch_hits 954719 # ITB hits
+system.cpu0.itb.fetch_misses 30502 # ITB misses
+system.cpu0.itb.fetch_acv 1031 # ITB acv
+system.cpu0.itb.fetch_accesses 985221 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 102599658 # number of cpu cycles simulated
+system.cpu0.numCycles 96359628 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 11825647 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 9917652 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 342692 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 8240217 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 5044056 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 11511160 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 9658650 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 337362 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 8089137 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 5013359 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 768623 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 31919 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 23566044 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 60418395 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 11825647 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 5812679 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 11434253 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1624928 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 35275815 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 31363 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 170412 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 309547 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 7444211 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 224420 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 71849758 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.840899 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.174060 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 738841 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 28813 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 22209501 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 59836413 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 11511160 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 5752200 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 11350991 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1703319 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 34574956 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 35024 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 203611 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 316697 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 7365602 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 218420 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 69794661 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.857321 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.189603 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 60415505 84.09% 84.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 744936 1.04% 85.12% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1526054 2.12% 87.25% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 669496 0.93% 88.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2482176 3.45% 91.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 513952 0.72% 92.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 559997 0.78% 93.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 746719 1.04% 94.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4190923 5.83% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 58443670 83.74% 83.74% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 721745 1.03% 84.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1525948 2.19% 86.96% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 670208 0.96% 87.92% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2529232 3.62% 91.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 511055 0.73% 92.27% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 558087 0.80% 93.07% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 646305 0.93% 94.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4188411 6.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 71849758 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.115260 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.588875 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 24832568 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 34702410 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 10423010 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 862232 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1029537 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 502827 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 32976 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 59359454 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 95150 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1029537 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 25748676 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 14416729 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 17004300 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 9792924 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3857590 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 56337606 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 6610 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 598180 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1362975 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 37819724 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 68629747 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 68286150 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 343597 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 33121112 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4698612 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1343902 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 201432 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 10333121 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 8734327 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5677673 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1105299 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 704273 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 50005822 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1695696 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 48865145 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 103608 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5731519 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 2860845 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1151664 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 71849758 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.680102 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.326568 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 69794661 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.119460 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.620970 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 23572170 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 33977525 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 10309860 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 863665 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1071440 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 494315 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 32656 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 58557743 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 90732 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1071440 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 24508121 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 14373596 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 16410684 # count of cycles rename stalled for serializing inst
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+system.cpu0.rename.UnblockCycles 3786145 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 55387876 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 6888 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 592503 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1353497 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 37339158 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 67830341 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 67526671 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 303670 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 32375017 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4964141 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1283235 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 190076 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 10267361 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 8584787 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5466291 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1084962 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 724878 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 49128818 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1589448 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 47805943 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 98656 # Number of squashed instructions issued
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+system.cpu0.iq.iqSquashedOperandsExamined 3193389 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 50068220 69.68% 69.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 9955153 13.86% 83.54% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 4454682 6.20% 89.74% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2911875 4.05% 93.79% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2358569 3.28% 97.08% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1157257 1.61% 98.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 610758 0.85% 99.54% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 286058 0.40% 99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 47186 0.07% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 48560473 69.58% 69.58% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 9626391 13.79% 83.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4360326 6.25% 89.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2905573 4.16% 93.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2277062 3.26% 97.04% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1128487 1.62% 98.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 610541 0.87% 99.53% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 278212 0.40% 99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 47596 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 71849758 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 69794661 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 80509 12.84% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 1 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 294043 46.91% 59.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 252280 40.25% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 83272 13.43% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 13.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 288642 46.54% 59.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 248279 40.03% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 2557 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 33918404 69.41% 69.42% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 54116 0.11% 69.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 12070 0.02% 69.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 8648673 17.70% 87.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5478002 11.21% 98.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 750056 1.53% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 3328 0.01% 0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 33277792 69.61% 69.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 52563 0.11% 69.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 13047 0.03% 69.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 8484999 17.75% 87.51% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5253957 10.99% 98.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 718601 1.50% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 48865145 # Type of FU issued
-system.cpu0.iq.rate 0.476270 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 626833 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.012828 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 169818867 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 57206555 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 47890608 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 491622 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 238128 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 232129 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 49232078 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 257343 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 523556 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 47805943 # Type of FU issued
+system.cpu0.iq.rate 0.496120 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 620193 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.012973 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 165689680 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 56419476 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 46799675 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 435716 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 211307 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 205983 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 48194794 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 228014 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 514272 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1075506 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2442 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 11895 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 454594 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1137404 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2618 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 12330 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 467046 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 86028 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 18608 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 143062 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1029537 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 10326104 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 769928 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 54791843 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 549393 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 8734327 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5677673 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1493453 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 559696 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 5669 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 11895 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 183351 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 329192 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 512543 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 48451300 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 8354077 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 413845 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1071440 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 10277613 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 727728 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 53688552 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 610167 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 8584787 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5466291 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1400307 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 521112 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 4713 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 12330 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 181936 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 316829 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 498765 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 47397397 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 8205181 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 408546 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 3090325 # number of nop insts executed
-system.cpu0.iew.exec_refs 13784796 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 7754310 # Number of branches executed
-system.cpu0.iew.exec_stores 5430719 # Number of stores executed
-system.cpu0.iew.exec_rate 0.472236 # Inst execution rate
-system.cpu0.iew.wb_sent 48208648 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 48122737 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 24107105 # num instructions producing a value
-system.cpu0.iew.wb_consumers 32426814 # num instructions consuming a value
+system.cpu0.iew.exec_nop 2970286 # number of nop insts executed
+system.cpu0.iew.exec_refs 13410008 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 7582856 # Number of branches executed
+system.cpu0.iew.exec_stores 5204827 # Number of stores executed
+system.cpu0.iew.exec_rate 0.491880 # Inst execution rate
+system.cpu0.iew.wb_sent 47094366 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 47005658 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 23624719 # num instructions producing a value
+system.cpu0.iew.wb_consumers 31676204 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.469034 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.743431 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.487815 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.745819 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6216029 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 544032 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 479899 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 70820221 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.684637 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.594318 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6363159 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 510744 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 465851 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 68723221 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.687218 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.593416 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 52470926 74.09% 74.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7676401 10.84% 84.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 4235846 5.98% 90.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2227139 3.14% 94.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1283042 1.81% 95.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 528527 0.75% 96.61% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 441494 0.62% 97.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 421867 0.60% 97.83% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1534979 2.17% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 50805017 73.93% 73.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7482510 10.89% 84.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 4158339 6.05% 90.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2211388 3.22% 94.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1226271 1.78% 95.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 519535 0.76% 96.62% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 434174 0.63% 97.26% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 401210 0.58% 97.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1484777 2.16% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 70820221 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 48486178 # Number of instructions committed
-system.cpu0.commit.committedOps 48486178 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 68723221 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 47227841 # Number of instructions committed
+system.cpu0.commit.committedOps 47227841 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 12881900 # Number of memory references committed
-system.cpu0.commit.loads 7658821 # Number of loads committed
-system.cpu0.commit.membars 183715 # Number of memory barriers committed
-system.cpu0.commit.branches 7346956 # Number of branches committed
-system.cpu0.commit.fp_insts 229898 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 44900899 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 613493 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1534979 # number cycles where commit BW limit reached
+system.cpu0.commit.refs 12446628 # Number of memory references committed
+system.cpu0.commit.loads 7447383 # Number of loads committed
+system.cpu0.commit.membars 170869 # Number of memory barriers committed
+system.cpu0.commit.branches 7170885 # Number of branches committed
+system.cpu0.commit.fp_insts 203520 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 43794871 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 589410 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1484777 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 123809295 # The number of ROB reads
-system.cpu0.rob.rob_writes 110434143 # The number of ROB writes
-system.cpu0.timesIdled 1033297 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 30749900 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3702120338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 45684021 # Number of Instructions Simulated
-system.cpu0.committedOps 45684021 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 45684021 # Number of Instructions Simulated
-system.cpu0.cpi 2.245854 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.245854 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.445265 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.445265 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 63838240 # number of integer regfile reads
-system.cpu0.int_regfile_writes 34928793 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 112215 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 113746 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1561574 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 757779 # number of misc regfile writes
+system.cpu0.rob.rob_reads 120629648 # The number of ROB reads
+system.cpu0.rob.rob_writes 108253472 # The number of ROB writes
+system.cpu0.timesIdled 983557 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 26564967 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 3700831730 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 44545141 # Number of Instructions Simulated
+system.cpu0.committedOps 44545141 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 44545141 # Number of Instructions Simulated
+system.cpu0.cpi 2.163191 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.163191 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.462280 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.462280 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 62595782 # number of integer regfile reads
+system.cpu0.int_regfile_writes 34216642 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 100415 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 101247 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 1454133 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 720721 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 812060 # number of replacements
-system.cpu0.icache.tagsinuse 510.054551 # Cycle average of tags in use
-system.cpu0.icache.total_refs 6590229 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 812572 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 8.110332 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 23200943000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 510.054551 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.996200 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.996200 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 6590229 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 6590229 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 6590229 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 6590229 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 6590229 # number of overall hits
-system.cpu0.icache.overall_hits::total 6590229 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 853981 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 853981 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 853981 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 853981 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 853981 # number of overall misses
-system.cpu0.icache.overall_misses::total 853981 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11857055495 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 11857055495 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 11857055495 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 11857055495 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 11857055495 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 11857055495 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 7444210 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 7444210 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 7444210 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 7444210 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 7444210 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 7444210 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114717 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.114717 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114717 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.114717 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114717 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.114717 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13884.448828 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13884.448828 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13884.448828 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13884.448828 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 2511 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.771654 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.replacements 750148 # number of replacements
+system.cpu0.icache.tagsinuse 510.325521 # Cycle average of tags in use
+system.cpu0.icache.total_refs 6574672 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 750660 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 8.758522 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 20341529000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 510.325521 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.996730 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.996730 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 6574672 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 6574672 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 6574672 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 6574672 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 6574672 # number of overall hits
+system.cpu0.icache.overall_hits::total 6574672 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 790930 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 790930 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 790930 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 790930 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 790930 # number of overall misses
+system.cpu0.icache.overall_misses::total 790930 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11244615993 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 11244615993 # number of ReadReq miss cycles
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+system.cpu0.dcache.overall_miss_rate::total 0.244010 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22364.222790 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 22364.222790 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43843.196966 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 43843.196966 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13330.220617 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13330.220617 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7566.723404 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7566.723404 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33593.137562 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33593.137562 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33593.137562 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33593.137562 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 2427231 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 1005 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 46334 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.579127 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 62.142857 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 52.385527 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 143.571429 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 710192 # number of writebacks
-system.cpu0.dcache.writebacks::total 710192 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 524907 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 524907 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1358576 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1358576 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4179 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4179 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1883483 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1883483 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1883483 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1883483 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 967539 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 967539 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254155 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 254155 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15250 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15250 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4062 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 4062 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1221694 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 1221694 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 1221694 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 1221694 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23357450000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23357450000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8081474275 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8081474275 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 163906000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 163906000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 39490500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 39490500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31438924275 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 31438924275 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31438924275 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 31438924275 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451861000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451861000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167064498 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167064498 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3618925498 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3618925498 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128055 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128055 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050527 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050527 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088965 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088965 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.022756 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.022756 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.097070 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.097070 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24141.094054 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24141.094054 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31797.423915 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31797.423915 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10747.934426 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10747.934426 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9721.935007 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9721.935007 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 669951 # number of writebacks
+system.cpu0.dcache.writebacks::total 669951 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 478870 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 478870 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1309589 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1309589 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3866 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3866 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1788459 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1788459 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1788459 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1788459 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939041 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 939041 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 243729 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 243729 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13857 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13857 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5874 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 5874 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182770 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1182770 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182770 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1182770 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20515201000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20515201000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9973935364 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9973935364 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136652000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136652000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32706500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32706500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30489136364 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 30489136364 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30489136364 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 30489136364 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1471717500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1471717500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2287191498 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2287191498 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3758908998 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3758908998 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127569 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127569 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050612 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050612 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086093 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086093 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.034867 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.034867 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097134 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.097134 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097134 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.097134 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21846.970473 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21846.970473 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40922.234794 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40922.234794 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9861.586202 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9861.586202 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5568.011576 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5568.011576 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25777.739006 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25777.739006 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25777.739006 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25777.739006 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 2472786 # DTB read hits
-system.cpu1.dtb.read_misses 14686 # DTB read misses
-system.cpu1.dtb.read_acv 33 # DTB read access violations
-system.cpu1.dtb.read_accesses 413814 # DTB read accesses
-system.cpu1.dtb.write_hits 1645990 # DTB write hits
-system.cpu1.dtb.write_misses 3399 # DTB write misses
-system.cpu1.dtb.write_acv 61 # DTB write access violations
-system.cpu1.dtb.write_accesses 158815 # DTB write accesses
-system.cpu1.dtb.data_hits 4118776 # DTB hits
-system.cpu1.dtb.data_misses 18085 # DTB misses
-system.cpu1.dtb.data_acv 94 # DTB access violations
-system.cpu1.dtb.data_accesses 572629 # DTB accesses
-system.cpu1.itb.fetch_hits 546471 # ITB hits
-system.cpu1.itb.fetch_misses 10636 # ITB misses
-system.cpu1.itb.fetch_acv 251 # ITB acv
-system.cpu1.itb.fetch_accesses 557107 # ITB accesses
+system.cpu1.dtb.read_hits 2751784 # DTB read hits
+system.cpu1.dtb.read_misses 11470 # DTB read misses
+system.cpu1.dtb.read_acv 7 # DTB read access violations
+system.cpu1.dtb.read_accesses 320817 # DTB read accesses
+system.cpu1.dtb.write_hits 1920140 # DTB write hits
+system.cpu1.dtb.write_misses 2953 # DTB write misses
+system.cpu1.dtb.write_acv 42 # DTB write access violations
+system.cpu1.dtb.write_accesses 122077 # DTB write accesses
+system.cpu1.dtb.data_hits 4671924 # DTB hits
+system.cpu1.dtb.data_misses 14423 # DTB misses
+system.cpu1.dtb.data_acv 49 # DTB access violations
+system.cpu1.dtb.data_accesses 442894 # DTB accesses
+system.cpu1.itb.fetch_hits 498760 # ITB hits
+system.cpu1.itb.fetch_misses 8025 # ITB misses
+system.cpu1.itb.fetch_acv 112 # ITB acv
+system.cpu1.itb.fetch_accesses 506785 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 20144234 # number of cpu cycles simulated
+system.cpu1.numCycles 23450533 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 3332472 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 2756183 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 108633 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 2168857 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 1160511 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 3776767 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 3137470 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 107427 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 2636449 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 1329693 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 228547 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 10150 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 7838813 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 15883595 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 3332472 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 1389058 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 2861385 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 534677 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 7961253 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 27792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 84864 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 61219 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 1925840 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 71197 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 19177134 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.828257 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.199800 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 256698 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 10696 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 9578000 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 17862357 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 3776767 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 1586391 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 3193569 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 532728 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 8846684 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 29714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 64849 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 64234 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.CacheLines 2092153 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 72512 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 22109536 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.807903 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.182028 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 16315749 85.08% 85.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 188313 0.98% 86.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 313367 1.63% 87.70% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 233008 1.22% 88.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 393584 2.05% 90.96% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 151826 0.79% 91.75% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 167771 0.87% 92.63% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 278696 1.45% 94.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 1134820 5.92% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 18915967 85.56% 85.56% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 225371 1.02% 86.58% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 332195 1.50% 88.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 235368 1.06% 89.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 429129 1.94% 91.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 160604 0.73% 91.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 176264 0.80% 92.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 387732 1.75% 94.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 1246906 5.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 19177134 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.165431 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.788493 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 7716271 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 8310209 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 2661595 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 156637 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 332421 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 147192 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 9531 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 15577857 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 28018 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 332421 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 7986115 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 672083 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 6791538 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 2542197 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 852778 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 14454091 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 131 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 86206 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 218054 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 9478411 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 17286766 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 17086477 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 200289 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 8045295 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1433108 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 570111 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 60569 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 2590157 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 2624799 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 1738404 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 257229 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 149585 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 12667252 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 630653 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 12308685 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 34992 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1859186 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 963032 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 447479 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 19177134 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.641842 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.313805 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 22109536 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.161053 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.761704 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 9287856 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 9344742 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 2981707 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 172176 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 323054 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 161936 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 9554 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 17577560 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 27080 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 323054 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 9598975 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 567037 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 7834145 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 2842462 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 943861 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 16294411 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 85147 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 230847 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 10570715 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 19279832 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 19004281 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 275551 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 9242282 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1328425 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 653029 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 73319 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 2960053 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 2891333 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 2010374 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 258927 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 184993 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 14228135 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 747471 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 13980669 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 34327 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1780795 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 830376 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 520995 # Number of squashed non-spec instructions that were removed
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system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 13743416 71.67% 71.67% # Number of insts issued each cycle
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-system.cpu1.iq.issued_per_cycle::2 1066336 5.56% 90.30% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 706714 3.69% 93.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 606260 3.16% 97.14% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 273557 1.43% 98.57% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 174545 0.91% 99.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 89739 0.47% 99.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 10148 0.05% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 15925897 72.03% 72.03% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 2876428 13.01% 85.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 1188641 5.38% 90.42% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 788361 3.57% 93.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 710967 3.22% 97.20% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 312206 1.41% 98.61% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 203719 0.92% 99.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 91872 0.42% 99.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 11445 0.05% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 19177134 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 22109536 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 4629 1.86% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 131937 52.95% 54.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 112626 45.20% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 4072 1.54% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 138321 52.40% 53.95% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 121563 46.05% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 7659302 62.23% 62.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 19564 0.16% 62.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.42% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 14781 0.12% 62.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.54% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 2596890 21.10% 83.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1675725 13.61% 97.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 335297 2.72% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 3973 0.03% 0.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 8718475 62.36% 62.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 23525 0.17% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 14518 0.10% 62.66% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.66% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.66% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.66% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 1986 0.01% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.68% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 2887601 20.65% 83.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 1950660 13.95% 97.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 379931 2.72% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 12308685 # Type of FU issued
-system.cpu1.iq.rate 0.611028 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 249192 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.020245 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 43789272 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 15018387 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 11932725 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 289415 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 141077 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 136872 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 12402102 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 151024 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 115183 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 13980669 # Type of FU issued
+system.cpu1.iq.rate 0.596177 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 263956 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.018880 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 49973211 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 16565755 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 13576031 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 395945 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 192396 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 186883 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 14033908 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 206744 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 127652 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 382493 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 2469 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 155910 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 343707 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 718 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 1847 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 149646 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 398 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 20099 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 268 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 8933 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 332421 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 409059 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 59053 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 13963733 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 192284 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 2624799 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 1738404 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 567278 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 49311 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2791 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 2469 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 54746 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 126604 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 181350 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 12183266 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 2497630 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 125418 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 323054 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 323914 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 83587 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 15804070 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 217247 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 2891333 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 2010374 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 666348 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 75335 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2938 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 1847 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 54178 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 138289 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 192467 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 13856768 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 2775542 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 123900 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 665828 # number of nop insts executed
-system.cpu1.iew.exec_refs 4154589 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 1827055 # Number of branches executed
-system.cpu1.iew.exec_stores 1656959 # Number of stores executed
-system.cpu1.iew.exec_rate 0.604802 # Inst execution rate
-system.cpu1.iew.wb_sent 12107744 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 12069597 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 5640555 # num instructions producing a value
-system.cpu1.iew.wb_consumers 7931807 # num instructions consuming a value
+system.cpu1.iew.exec_nop 828464 # number of nop insts executed
+system.cpu1.iew.exec_refs 4708126 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 2079937 # Number of branches executed
+system.cpu1.iew.exec_stores 1932584 # Number of stores executed
+system.cpu1.iew.exec_rate 0.590894 # Inst execution rate
+system.cpu1.iew.wb_sent 13794604 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 13762914 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 6356145 # num instructions producing a value
+system.cpu1.iew.wb_consumers 9022133 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.599159 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.711131 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.586891 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.704506 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 1943114 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 183174 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 170211 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 18844713 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.633421 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.575988 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 1892811 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 226476 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 180279 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 21786482 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.634671 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.584399 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 14387001 76.35% 76.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 2066578 10.97% 87.31% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 777942 4.13% 91.44% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 478446 2.54% 93.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 347277 1.84% 95.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 135394 0.72% 96.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 132721 0.70% 97.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 138400 0.73% 97.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 380954 2.02% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 16693912 76.63% 76.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 2323450 10.66% 87.29% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 881751 4.05% 91.34% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 546550 2.51% 93.85% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 424121 1.95% 95.79% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 149663 0.69% 96.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 143043 0.66% 97.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 194342 0.89% 98.03% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 429650 1.97% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 18844713 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 11936636 # Number of instructions committed
-system.cpu1.commit.committedOps 11936636 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 21786482 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 13827253 # Number of instructions committed
+system.cpu1.commit.committedOps 13827253 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 3824800 # Number of memory references committed
-system.cpu1.commit.loads 2242306 # Number of loads committed
-system.cpu1.commit.membars 59908 # Number of memory barriers committed
-system.cpu1.commit.branches 1711003 # Number of branches committed
-system.cpu1.commit.fp_insts 135276 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 11053668 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 186526 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 380954 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 4408354 # Number of memory references committed
+system.cpu1.commit.loads 2547626 # Number of loads committed
+system.cpu1.commit.membars 77059 # Number of memory barriers committed
+system.cpu1.commit.branches 1974738 # Number of branches committed
+system.cpu1.commit.fp_insts 185573 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 12741220 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 216858 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 429650 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 32234171 # The number of ROB reads
-system.cpu1.rob.rob_writes 28090700 # The number of ROB writes
-system.cpu1.timesIdled 170938 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 967100 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 3785218747 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 11348024 # Number of Instructions Simulated
-system.cpu1.committedOps 11348024 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 11348024 # Number of Instructions Simulated
-system.cpu1.cpi 1.775131 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.775131 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.563339 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.563339 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 15713233 # number of integer regfile reads
-system.cpu1.int_regfile_writes 8535659 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 74431 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 74222 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 667576 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 284444 # number of misc regfile writes
-system.cpu1.icache.replacements 292722 # number of replacements
-system.cpu1.icache.tagsinuse 471.494279 # Cycle average of tags in use
-system.cpu1.icache.total_refs 1621349 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 293230 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 5.529274 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1876700215000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 471.494279 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.920887 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.920887 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 1621349 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 1621349 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 1621349 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 1621349 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 1621349 # number of overall hits
-system.cpu1.icache.overall_hits::total 1621349 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 304491 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 304491 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 304491 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 304491 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 304491 # number of overall misses
-system.cpu1.icache.overall_misses::total 304491 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4065162500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 4065162500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 4065162500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 4065162500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 4065162500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 4065162500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 1925840 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 1925840 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 1925840 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 1925840 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 1925840 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 1925840 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158108 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.158108 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158108 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.158108 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158108 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.158108 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13350.681958 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13350.681958 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13350.681958 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13350.681958 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked
+system.cpu1.rob.rob_reads 36982885 # The number of ROB reads
+system.cpu1.rob.rob_writes 31761465 # The number of ROB writes
+system.cpu1.timesIdled 211192 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 1340997 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 3774455201 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 13084179 # Number of Instructions Simulated
+system.cpu1.committedOps 13084179 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 13084179 # Number of Instructions Simulated
+system.cpu1.cpi 1.792282 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.792282 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.557948 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.557948 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 17801475 # number of integer regfile reads
+system.cpu1.int_regfile_writes 9673582 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 97896 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 98917 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 828029 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 335588 # number of misc regfile writes
+system.cpu1.icache.replacements 365714 # number of replacements
+system.cpu1.icache.tagsinuse 472.361820 # Cycle average of tags in use
+system.cpu1.icache.total_refs 1714322 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 366225 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 4.681062 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1888132363000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 472.361820 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.922582 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.922582 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 1714323 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 1714323 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 1714323 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 1714323 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 1714323 # number of overall hits
+system.cpu1.icache.overall_hits::total 1714323 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 377830 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 377830 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 377830 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 377830 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 377830 # number of overall misses
+system.cpu1.icache.overall_misses::total 377830 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5021047500 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 5021047500 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 5021047500 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 5021047500 # number of demand (read+write) miss cycles
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+system.cpu1.icache.demand_avg_miss_latency::total 13289.171056 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13289.171056 # average overall miss latency
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system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
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-system.cpu1.icache.ReadReq_mshr_misses::total 293321 # number of ReadReq MSHR misses
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-system.cpu1.icache.overall_mshr_misses::total 293321 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11540.321013 # average ReadReq mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11457.572796 # average overall mshr miss latency
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+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14423.884830 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14423.884830 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30003.227783 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 30003.227783 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9948.222715 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9948.222715 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.269365 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.269365 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22367.215652 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 22367.215652 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22367.215652 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 22367.215652 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 367146 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 7912 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 4032 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.788549 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 91.058036 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 102031 # number of writebacks
-system.cpu1.dcache.writebacks::total 102031 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180109 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 180109 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 273076 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 273076 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 765 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 765 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 453185 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 453185 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 453185 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 453185 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 108656 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 108656 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57473 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 57473 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6725 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6725 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4282 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 4282 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 166129 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 166129 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 166129 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 166129 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1328748500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1328748500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1211037987 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1211037987 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54734500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54734500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 40806500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 40806500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539786487 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 2539786487 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539786487 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 2539786487 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30975000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30975000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 686558000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 686558000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717533000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 717533000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047272 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047272 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037669 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037669 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123110 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123110 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085561 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085561 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.043441 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.043441 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12228.947320 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12228.947320 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21071.424617 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21071.424617 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8138.959108 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8138.959108 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9529.775806 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9529.775806 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 122264 # number of writebacks
+system.cpu1.dcache.writebacks::total 122264 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 218997 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 218997 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 293003 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 293003 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 737 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 737 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 512000 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 512000 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 512000 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 512000 # number of overall MSHR hits
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+system.cpu1.dcache.ReadReq_mshr_misses::total 126578 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 66480 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 66480 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9644 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9644 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6325 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 6325 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 193058 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 193058 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 193058 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 193058 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1500682500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1500682500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1627145493 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1627145493 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75395000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75395000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 33822500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 33822500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3127827993 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 3127827993 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3127827993 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 3127827993 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18098500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18098500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718992500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718992500 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737091000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049398 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049398 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037121 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037121 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.142490 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.142490 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100853 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100853 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044347 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.044347 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044347 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.044347 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11855.792476 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11855.792476 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24475.714395 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24475.714395 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7817.814185 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.814185 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5347.430830 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5347.430830 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16201.493815 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16201.493815 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16201.493815 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16201.493815 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6652 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 169834 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 59752 40.24% 40.24% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.09% 40.32% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1927 1.30% 41.62% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 283 0.19% 41.81% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 86412 58.19% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 148505 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 58939 49.14% 49.14% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1927 1.61% 50.86% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 283 0.24% 51.09% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 58656 48.91% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 119936 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1864736682500 98.02% 98.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 62604500 0.00% 98.03% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 575436000 0.03% 98.06% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 137989000 0.01% 98.06% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 36850597000 1.94% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1902363309000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.986394 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6891 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 160705 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 55206 40.22% 40.22% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 141 0.10% 40.32% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1925 1.40% 41.72% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 459 0.33% 42.06% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 79532 57.94% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 137263 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 54744 49.07% 49.07% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 141 0.13% 49.20% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1925 1.73% 50.92% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 459 0.41% 51.34% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 54290 48.66% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 111559 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1864428350500 98.20% 98.20% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 66694000 0.00% 98.20% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 571257500 0.03% 98.23% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 222612500 0.01% 98.25% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 33310195000 1.75% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1898599109500 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.991631 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.678795 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.807623 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed
-system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed
-system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed
-system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed
-system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed
-system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed
-system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed
-system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed
-system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed
-system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed
-system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed
-system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed
-system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed
-system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed
-system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed
-system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed
-system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed
-system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed
-system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed
-system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed
-system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 178 # number of syscalls executed
+system.cpu0.kern.ipl_used::31 0.682618 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.812739 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
+system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
+system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
+system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
+system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
+system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
+system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
+system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
+system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
+system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
+system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
+system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
+system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
+system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
+system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
+system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
+system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
+system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
+system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
+system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
+system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
+system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
+system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
+system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
+system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
+system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
+system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
+system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
+system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total 222 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 383 0.25% 0.25% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.25% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.25% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.25% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3188 2.04% 2.29% # number of callpals executed
-system.cpu0.kern.callpal::tbi 48 0.03% 2.32% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 141921 90.80% 93.12% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6055 3.87% 96.99% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 2 0.00% 96.99% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 8 0.01% 97.00% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed
-system.cpu0.kern.callpal::rti 4242 2.71% 99.71% # number of callpals executed
-system.cpu0.kern.callpal::callsys 315 0.20% 99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 156308 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6637 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches
+system.cpu0.kern.callpal::wripir 540 0.37% 0.37% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.37% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.37% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 2997 2.06% 2.43% # number of callpals executed
+system.cpu0.kern.callpal::tbi 51 0.04% 2.47% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.47% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 130488 89.67% 92.14% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6655 4.57% 96.71% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed
+system.cpu0.kern.callpal::rti 4254 2.92% 99.64% # number of callpals executed
+system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed
+system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 145528 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 6813 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1098
-system.cpu0.kern.mode_good::user 1098
+system.cpu0.kern.mode_good::kernel 1282
+system.cpu0.kern.mode_good::user 1282
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.165436 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.188170 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.283904 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1900423407500 99.92% 99.92% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1609733000 0.08% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.316739 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1896637292000 99.90% 99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 1952797500 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3189 # number of times the context was actually changed
+system.cpu0.kern.swap_context 2998 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2560 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 70963 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 22970 38.17% 38.17% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1925 3.20% 41.37% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 383 0.64% 42.01% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 34900 57.99% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 60178 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 22406 47.94% 47.94% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1925 4.12% 52.06% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 383 0.82% 52.88% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 22023 47.12% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 46737 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1874192202500 98.50% 98.50% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 532510000 0.03% 98.53% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 178162000 0.01% 98.54% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 27779026000 1.46% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1902681900500 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.975446 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2640 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 82284 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 28208 38.75% 38.75% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1924 2.64% 41.39% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 540 0.74% 42.13% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 42124 57.87% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 72796 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 27293 48.30% 48.30% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1924 3.40% 51.70% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 540 0.96% 52.66% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 26753 47.34% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 56510 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1872083396500 98.59% 98.59% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 532362500 0.03% 98.61% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 246280000 0.01% 98.63% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 26091314000 1.37% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1898953353000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.967562 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.631032 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.776646 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed
-system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed
-system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed
-system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed
-system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed
-system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed
-system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed
-system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed
-system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed
-system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed
-system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed
-system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed
-system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed
-system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed
-system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed
-system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed
-system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed
-system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed
-system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed
-system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 148 # number of syscalls executed
+system.cpu1.kern.ipl_used::31 0.635101 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.776279 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
+system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
+system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
+system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
+system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
+system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
+system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
+system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
+system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
+system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
+system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
+system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
+system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total 104 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 283 0.45% 0.45% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1593 2.54% 3.00% # number of callpals executed
-system.cpu1.kern.callpal::tbi 5 0.01% 3.00% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 3.01% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 54358 86.66% 89.67% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2709 4.32% 93.99% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 93.99% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 5 0.01% 94.00% # number of callpals executed
-system.cpu1.kern.callpal::rdusp 1 0.00% 94.00% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.00% 94.01% # number of callpals executed
-system.cpu1.kern.callpal::rti 3511 5.60% 99.60% # number of callpals executed
-system.cpu1.kern.callpal::callsys 200 0.32% 99.92% # number of callpals executed
-system.cpu1.kern.callpal::imb 48 0.08% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 459 0.61% 0.61% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 2146 2.85% 3.47% # number of callpals executed
+system.cpu1.kern.callpal::tbi 3 0.00% 3.47% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 3.48% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 66489 88.37% 91.85% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2102 2.79% 94.64% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 94.64% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 4 0.01% 94.65% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.00% 94.65% # number of callpals executed
+system.cpu1.kern.callpal::rti 3842 5.11% 99.76% # number of callpals executed
+system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed
+system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 62728 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1948 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 639 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2607 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 948
-system.cpu1.kern.mode_good::user 639
-system.cpu1.kern.mode_good::idle 309
-system.cpu1.kern.mode_switch_good::kernel 0.486653 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 75240 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 2162 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2922 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 928
+system.cpu1.kern.mode_good::user 464
+system.cpu1.kern.mode_good::idle 464
+system.cpu1.kern.mode_switch_good::kernel 0.429232 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.118527 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.365037 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 6500961500 0.34% 0.34% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1047066000 0.06% 0.40% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1895133865000 99.60% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1594 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.158795 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.334535 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 8174267000 0.43% 0.43% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 802919500 0.04% 0.47% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1889976158500 99.53% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 2147 # number of times the context was actually changed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.855236 # Number of seconds simulated
-sim_ticks 1855236450500 # Number of ticks simulated
-final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.854370 # Number of seconds simulated
+sim_ticks 1854370484500 # Number of ticks simulated
+final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 182093 # Simulator instruction rate (inst/s)
-host_op_rate 182093 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6374280472 # Simulator tick rate (ticks/s)
-host_mem_usage 298212 # Number of bytes of host memory used
-host_seconds 291.05 # Real time elapsed on the host
-sim_insts 52998368 # Number of instructions simulated
-sim_ops 52998368 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28503040 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7522688 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7522688 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 15149 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388769 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 445360 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 117542 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 117542 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 522594 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13411345 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1429623 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15363562 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 522594 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 522594 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4054841 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4054841 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4054841 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 522594 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13411345 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1429623 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19418402 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 94446 # Simulator instruction rate (inst/s)
+host_op_rate 94446 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3304859837 # Simulator tick rate (ticks/s)
+host_mem_usage 326668 # Number of bytes of host memory used
+host_seconds 561.10 # Real time elapsed on the host
+sim_insts 52993965 # Number of instructions simulated
+sim_ops 52993965 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24876288 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28497728 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7507712 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7507712 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388692 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 445277 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 117308 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 117308 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 522597 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13414950 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1430325 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15367872 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 522597 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 522597 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4048658 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4048658 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4048658 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 522597 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13414950 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1430325 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19416530 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 445277 # Total number of read requests seen
+system.physmem.writeReqs 117308 # Total number of write requests seen
+system.physmem.cpureqs 564090 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28497728 # Total number of bytes read from memory
+system.physmem.bytesWritten 7507712 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28497728 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7507712 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28080 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 27611 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 27911 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 27629 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 28123 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 28001 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27963 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27770 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 27692 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27278 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 27918 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 28145 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 27747 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27834 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27734 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7584 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7291 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7101 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7583 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7405 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7380 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7215 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7260 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6854 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7428 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7671 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7427 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7350 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7315 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7174 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1854365055000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 445277 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 118080 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 175 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 331917 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 65103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 18248 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 6337 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2872 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2456 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1809 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2035 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1684 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1980 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1575 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1648 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1261 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1518 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 936 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 252 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 140 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::1 4841 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4917 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4965 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5049 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5061 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5094 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5094 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5093 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1189 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 260 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 184 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 136 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 6175508423 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13385774423 # Sum of mem lat for all requests
+system.physmem.totBusLat 1780884000 # Total cycles spent in databus access
+system.physmem.totBankLat 5429382000 # Total cycles spent in bank access
+system.physmem.avgQLat 13870.66 # Average queueing delay per request
+system.physmem.avgBankLat 12194.80 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 30065.46 # Average memory access latency
+system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.12 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.01 # Average read queue length over time
+system.physmem.avgWrQLen 10.01 # Average write queue length over time
+system.physmem.readRowHits 425232 # Number of row buffer hits during reads
+system.physmem.writeRowHits 76485 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 65.20 # Row buffer hit rate for writes
+system.physmem.avgGap 3296150.90 # Average gap between requests
system.iocache.replacements 41685 # number of replacements
-system.iocache.tagsinuse 1.255779 # Cycle average of tags in use
+system.iocache.tagsinuse 1.265505 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1706412007000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.255779 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.078486 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.078486 # Average percentage of cache occupancy
+system.iocache.warmup_cycle 1704471567000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 1.265505 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.079094 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.079094 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 11469598806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 11469598806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 11490271804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 11490271804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 11490271804 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 11490271804 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide 20930998 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 20930998 # number of ReadReq miss cycles
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+system.iocache.WriteReq_miss_latency::total 9501230806 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 9522161804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 9522161804 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 9522161804 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 9522161804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120988.427746 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 120988.427746 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228658.808385 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 228658.808385 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 228212.385956 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 228212.385956 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 190847 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 22837 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 8.356921 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles
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+system.iocache.ReadReq_mshr_miss_latency::total 11934000 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338470481 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 7338470481 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 7350404481 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 7350404481 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 7350404481 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 7350404481 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68982.658960 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68982.658960 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176609.320394 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 176609.320394 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9942716 # DTB read hits
-system.cpu.dtb.read_misses 44791 # DTB read misses
-system.cpu.dtb.read_acv 565 # DTB read access violations
-system.cpu.dtb.read_accesses 947396 # DTB read accesses
-system.cpu.dtb.write_hits 6623666 # DTB write hits
-system.cpu.dtb.write_misses 10259 # DTB write misses
-system.cpu.dtb.write_acv 393 # DTB write access violations
-system.cpu.dtb.write_accesses 338396 # DTB write accesses
-system.cpu.dtb.data_hits 16566382 # DTB hits
-system.cpu.dtb.data_misses 55050 # DTB misses
-system.cpu.dtb.data_acv 958 # DTB access violations
-system.cpu.dtb.data_accesses 1285792 # DTB accesses
-system.cpu.itb.fetch_hits 1328947 # ITB hits
-system.cpu.itb.fetch_misses 38142 # ITB misses
-system.cpu.itb.fetch_acv 1080 # ITB acv
-system.cpu.itb.fetch_accesses 1367089 # ITB accesses
+system.cpu.dtb.read_hits 10013236 # DTB read hits
+system.cpu.dtb.read_misses 44959 # DTB read misses
+system.cpu.dtb.read_acv 558 # DTB read access violations
+system.cpu.dtb.read_accesses 947796 # DTB read accesses
+system.cpu.dtb.write_hits 6616814 # DTB write hits
+system.cpu.dtb.write_misses 10390 # DTB write misses
+system.cpu.dtb.write_acv 394 # DTB write access violations
+system.cpu.dtb.write_accesses 338465 # DTB write accesses
+system.cpu.dtb.data_hits 16630050 # DTB hits
+system.cpu.dtb.data_misses 55349 # DTB misses
+system.cpu.dtb.data_acv 952 # DTB access violations
+system.cpu.dtb.data_accesses 1286261 # DTB accesses
+system.cpu.itb.fetch_hits 1329992 # ITB hits
+system.cpu.itb.fetch_misses 37108 # ITB misses
+system.cpu.itb.fetch_acv 1110 # ITB acv
+system.cpu.itb.fetch_accesses 1367100 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 112948398 # number of cpu cycles simulated
+system.cpu.numCycles 109331520 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 13966796 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11655953 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 444631 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10036743 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 5871104 # Number of BTB hits
+system.cpu.BPredUnit.lookups 14034298 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11727409 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 442398 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 10070774 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 5936443 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 934424 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 41946 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 28374488 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 71061459 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13966796 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 6805528 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 13370359 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2059258 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 37279668 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 255422 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 316546 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 158 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8741472 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 286615 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 80977441 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.877546 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.218344 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 932889 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 42550 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 28466944 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 71882691 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14034298 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 37395096 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 81356871 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 67607082 83.49% 83.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 875013 1.08% 84.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1738431 2.15% 86.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 848390 1.05% 87.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2741333 3.39% 91.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 593371 0.73% 91.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 672322 0.83% 92.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1013697 1.25% 93.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4887802 6.04% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 67855364 83.40% 83.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2811672 3.46% 91.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 591009 0.73% 91.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 671901 0.83% 92.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1016398 1.25% 93.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 80977441 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.123656 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.629150 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29512235 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 36965653 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 12232048 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 961909 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1305595 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 610411 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 43204 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 69782793 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 129607 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1305595 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 30617338 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 13493069 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 19707624 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 11473805 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4380008 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 66097462 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 499537 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 1599586 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 44156593 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 80173165 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 79693699 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 479466 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 38191541 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5965044 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1694326 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 247806 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12010371 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 10525116 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 6937010 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1314782 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 853291 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 58559009 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 81356871 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 37116939 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 610220 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 43308 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 70446207 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 129922 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 19830183 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 6758 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 499961 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1485755 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 44416415 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 80669752 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 80190207 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 479545 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 38187514 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 6228893 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1695379 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 248206 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12171415 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 10595299 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 6961029 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1313529 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 845283 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 58768050 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2080813 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 57151750 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 119190 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 81356871 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56509821 69.46% 69.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2660699 3.27% 96.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1462898 1.80% 98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 750627 0.92% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 334208 0.41% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 80977441 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 81356871 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 88366 11.20% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 374779 47.48% 58.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 326184 41.32% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 375615 47.50% 58.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 326165 41.25% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 38932323 68.21% 68.23% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 61748 0.11% 68.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 10391482 18.21% 86.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 6703636 11.75% 98.34% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 948755 1.66% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 38947584 68.15% 68.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 61688 0.11% 68.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 10460697 18.30% 86.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 6696198 11.72% 98.34% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 949053 1.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 57074473 # Type of FU issued
-system.cpu.iq.rate 0.505315 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 789329 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013830 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 195341432 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 67578548 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 55793685 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 692544 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 336641 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 327847 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 57495160 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 361356 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 596122 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 57151750 # Type of FU issued
+system.cpu.iq.rate 0.522738 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 195876832 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 336801 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 327935 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 57573031 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 362154 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 597795 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1429701 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3754 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 13594 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 555558 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1500833 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 3663 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 13623 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 580148 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17950 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 159161 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17973 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 208284 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1305595 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 9769239 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 682868 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 64195167 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 659293 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 10525116 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 6937010 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1832536 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 511952 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 18439 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 13594 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 242380 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 420357 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 662737 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 56550869 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 10016393 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 523603 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1354175 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 9957840 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 684465 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 64406962 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 718774 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 10595299 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 6961029 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1833098 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 512595 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 19043 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 13623 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 239398 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 420347 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 659745 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 56634449 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 10087078 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 517300 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3555305 # number of nop insts executed
-system.cpu.iew.exec_refs 16665522 # number of memory reference insts executed
-system.cpu.iew.exec_branches 8969939 # Number of branches executed
-system.cpu.iew.exec_stores 6649129 # Number of stores executed
-system.cpu.iew.exec_rate 0.500679 # Inst execution rate
-system.cpu.iew.wb_sent 56244022 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 56121532 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 27804186 # num instructions producing a value
-system.cpu.iew.wb_consumers 37617732 # num instructions consuming a value
+system.cpu.iew.exec_nop 3558099 # number of nop insts executed
+system.cpu.iew.exec_refs 16729501 # number of memory reference insts executed
+system.cpu.iew.exec_branches 8966109 # Number of branches executed
+system.cpu.iew.exec_stores 6642423 # Number of stores executed
+system.cpu.iew.exec_rate 0.518007 # Inst execution rate
+system.cpu.iew.wb_sent 56249945 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 56126682 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 27860065 # num instructions producing a value
+system.cpu.iew.wb_consumers 37718288 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.496878 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.739124 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.513362 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.738635 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 7890216 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 664845 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 612833 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 79671846 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.705254 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.627009 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 80002696 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 58664724 73.63% 73.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8821985 11.07% 84.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4676702 5.87% 90.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2526569 3.17% 93.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1499177 1.88% 95.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 615140 0.77% 96.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 529950 0.67% 97.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 519091 0.65% 97.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1818508 2.28% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 59120918 73.90% 73.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1525301 1.91% 95.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 612184 0.77% 96.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 529748 0.66% 97.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 518714 0.65% 97.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 79671846 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 56188905 # Number of instructions committed
-system.cpu.commit.committedOps 56188905 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 80002696 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 56184240 # Number of instructions committed
+system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 15476867 # Number of memory references committed
-system.cpu.commit.loads 9095415 # Number of loads committed
-system.cpu.commit.membars 226300 # Number of memory barriers committed
-system.cpu.commit.branches 8447820 # Number of branches committed
+system.cpu.commit.refs 15475347 # Number of memory references committed
+system.cpu.commit.loads 9094466 # Number of loads committed
+system.cpu.commit.membars 226347 # Number of memory barriers committed
+system.cpu.commit.branches 8447798 # Number of branches committed
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 52034961 # Number of committed integer instructions.
-system.cpu.commit.function_calls 740468 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 1818508 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 52030338 # Number of committed integer instructions.
+system.cpu.commit.function_calls 740415 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 141682968 # The number of ROB reads
-system.cpu.rob.rob_writes 129465441 # The number of ROB writes
-system.cpu.timesIdled 1179964 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 31970957 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 3597518061 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 52998368 # Number of Instructions Simulated
-system.cpu.committedOps 52998368 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 52998368 # Number of Instructions Simulated
-system.cpu.cpi 2.131167 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.131167 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.469226 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.469226 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 74144483 # number of integer regfile reads
-system.cpu.int_regfile_writes 40484328 # number of integer regfile writes
-system.cpu.fp_regfile_reads 165992 # number of floating regfile reads
-system.cpu.fp_regfile_writes 167427 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1993361 # number of misc regfile reads
-system.cpu.misc_regfile_writes 946826 # number of misc regfile writes
+system.cpu.rob.rob_reads 142220967 # The number of ROB reads
+system.cpu.rob.rob_writes 129940455 # The number of ROB writes
+system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 27974649 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 52993965 # Number of Instructions Simulated
+system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 52993965 # Number of Instructions Simulated
+system.cpu.cpi 2.063094 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.063094 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.484709 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.484709 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 74218754 # number of integer regfile reads
+system.cpu.int_regfile_writes 40498790 # number of integer regfile writes
+system.cpu.fp_regfile_reads 166070 # number of floating regfile reads
+system.cpu.fp_regfile_writes 167447 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1994018 # number of misc regfile reads
+system.cpu.misc_regfile_writes 947042 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 1020348 # number of replacements
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+system.cpu.dcache.ReadReq_hits::total 7264730 # number of ReadReq hits
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+system.cpu.dcache.LoadLockedReq_hits::total 190246 # number of LoadLockedReq hits
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+system.cpu.dcache.StoreCondReq_hits::total 219552 # number of StoreCondReq hits
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+system.cpu.dcache.overall_hits::total 11469625 # number of overall hits
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+system.cpu.dcache.ReadReq_misses::total 1801434 # number of ReadReq misses
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+system.cpu.dcache.WriteReq_misses::total 1941730 # number of WriteReq misses
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+system.cpu.dcache.LoadLockedReq_misses::total 22995 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
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+system.cpu.dcache.demand_misses::total 3743164 # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total 3743164 # number of overall misses
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+system.cpu.dcache.overall_miss_latency::total 104297759139 # number of overall miss cycles
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+system.cpu.dcache.StoreCondReq_accesses::total 219554 # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::total 15212789 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 15212789 # number of overall (read+write) accesses
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+system.cpu.dcache.WriteReq_miss_rate::total 0.315902 # miss rate for WriteReq accesses
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+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107836 # miss rate for LoadLockedReq accesses
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+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses
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+system.cpu.dcache.demand_miss_rate::total 0.246054 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.246054 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.547949 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.547949 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 27863.529126 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27863.529126 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 2571682 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946948 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks
-system.cpu.dcache.writebacks::total 841878 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712313 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 712313 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642186 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1642186 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5152 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 5152 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2354499 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2354499 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2354499 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2354499 # number of overall MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total 1085162 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300228 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 300228 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17888 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 17888 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
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-system.cpu.dcache.demand_mshr_misses::total 1385390 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses
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-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles
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-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 32065701283 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997524498 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119614 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119614 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048840 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048840 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083809 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083809 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
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-system.cpu.dcache.demand_mshr_miss_rate::total 0.091028 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.513620 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.513620 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 841139 # number of writebacks
+system.cpu.dcache.writebacks::total 841139 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716695 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 716695 # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_hits::total 1641513 # number of WriteReq MSHR hits
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+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5045 # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total 1084739 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total 300217 # number of WriteReq MSHR misses
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+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17950 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712390769 # number of WriteReq MSHR miss cycles
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+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 31907863269 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997718998 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421626998 # number of overall MSHR uncacheable cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048843 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084177 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084177 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091039 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.159135 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.159135 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 338417 # number of replacements
-system.cpu.l2cache.tagsinuse 65352.111585 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2559541 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 403585 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 6.342012 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 4707423000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 53923.419199 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 5354.651362 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6074.041024 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.822806 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.081705 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.092683 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.997194 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 1005811 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 828504 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1834315 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 841878 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 841878 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
+system.cpu.l2cache.replacements 338360 # number of replacements
+system.cpu.l2cache.tagsinuse 65364.997376 # Cycle average of tags in use
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273859 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 289002 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115327 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 115327 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 389186 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 404329 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 389186 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 404329 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725022440 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8259922361 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8984944801 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067951103 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067951103 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327873464 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16052895904 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327873464 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16052895904 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331389500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331389500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1881061000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1881061000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212450500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212450500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.537313 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.537313 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383388 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383388 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.166828 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.166828 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47878.388694 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30161.222969 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31089.559245 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.178458 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.178458 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 210941 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74638 40.97% 40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 211013 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105526 57.93% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182173 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73271 49.32% 49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 105569 57.93% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73271 49.32% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 148551 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1816492246000 97.91% 97.91% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 64137000 0.00% 97.92% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 560297500 0.03% 97.95% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 38118929000 2.05% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1855235609500 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981685 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1818451122500 98.06% 98.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 64044500 0.00% 98.07% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 561305000 0.03% 98.10% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 35293166500 1.90% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1854369638500 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.694295 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175060 91.22% 93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175126 91.22% 93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
-system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed
+system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 191902 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches
+system.cpu.kern.callpal::total 191972 # number of callpals executed
+system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches
system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
+system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1909
system.cpu.kern.mode_good::user 1739
system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 28997338000 1.56% 1.56% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 2608198500 0.14% 1.70% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1823630065000 98.30% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 29748704000 1.60% 1.60% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 2690261500 0.15% 1.75% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1821930665000 98.25% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.534173 # Number of seconds simulated
-sim_ticks 2534173219000 # Number of ticks simulated
-final_tick 2534173219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.523636 # Number of seconds simulated
+sim_ticks 2523635852000 # Number of ticks simulated
+final_tick 2523635852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 58476 # Simulator instruction rate (inst/s)
-host_op_rate 75217 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2445371941 # Simulator tick rate (ticks/s)
-host_mem_usage 386340 # Number of bytes of host memory used
-host_seconds 1036.31 # Real time elapsed on the host
-sim_insts 60599410 # Number of instructions simulated
-sim_ops 77948210 # Number of ops (including micro ops) simulated
+host_inst_rate 60184 # Simulator instruction rate (inst/s)
+host_op_rate 77414 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2506430956 # Simulator tick rate (ticks/s)
+host_mem_usage 399764 # Number of bytes of host memory used
+host_seconds 1006.86 # Real time elapsed on the host
+sim_insts 60597347 # Number of instructions simulated
+sim_ops 77945524 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798080 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9096016 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129435344 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798080 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798080 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 799360 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129436368 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 799360 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 799360 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 56 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12470 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142159 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096893 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12490 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096909 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47170281 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1389 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47367240 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1420 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314927 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51075966 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314927 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314927 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493669 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190160 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683829 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493669 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47170281 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1389 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 316749 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3604203 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51289637 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 316749 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 316749 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499145 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1195130 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2694275 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1499145 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47367240 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1420 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314927 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4779503 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53759795 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 316749 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4799333 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53983912 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096909 # Total number of read requests seen
+system.physmem.writeReqs 813132 # Total number of write requests seen
+system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966202176 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040448 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129436368 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 363 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943955 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943427 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 943468 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943391 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943248 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943111 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943293 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943780 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943638 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943709 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943744 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 943610 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 943654 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50098 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 49973 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50033 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50667 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50819 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51122 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51107 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51166 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51028 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 1156323 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2523634566000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 36 # Categorize read packet sizes
+system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 154665 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 1910341 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 59114 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 14955787 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 89824 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 6501 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2877 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2340 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2145 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1923 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1719 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1284 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1282 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1247 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 6296 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 9574 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 13083 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 566 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 49 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 32 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2806 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2951 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3069 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3199 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3759 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 3930 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4091 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32548 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32403 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32285 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32155 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31424 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31263 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 46870409147 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 317530293147 # Sum of mem lat for all requests
+system.physmem.totBusLat 60386184000 # Total cycles spent in databus access
+system.physmem.totBankLat 210273700000 # Total cycles spent in bank access
+system.physmem.avgQLat 3104.71 # Average queueing delay per request
+system.physmem.avgBankLat 13928.60 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 21033.31 # Average memory access latency
+system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 2.52 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.13 # Average read queue length over time
+system.physmem.avgWrQLen 12.37 # Average write queue length over time
+system.physmem.readRowHits 15050555 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784512 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 96.48 # Row buffer hit rate for writes
+system.physmem.avgGap 158618.99 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 15049590 # DTB read hits
-system.cpu.checker.dtb.read_misses 7303 # DTB read misses
-system.cpu.checker.dtb.write_hits 11294593 # DTB write hits
+system.cpu.checker.dtb.read_hits 15048983 # DTB read hits
+system.cpu.checker.dtb.read_misses 7307 # DTB read misses
+system.cpu.checker.dtb.write_hits 11294245 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15056893 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11296782 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 15056290 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11296434 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26344183 # DTB hits
-system.cpu.checker.dtb.misses 9492 # DTB misses
-system.cpu.checker.dtb.accesses 26353675 # DTB accesses
-system.cpu.checker.itb.inst_hits 61778177 # ITB inst hits
+system.cpu.checker.dtb.hits 26343228 # DTB hits
+system.cpu.checker.dtb.misses 9496 # DTB misses
+system.cpu.checker.dtb.accesses 26352724 # DTB accesses
+system.cpu.checker.itb.inst_hits 61776100 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61782648 # ITB inst accesses
-system.cpu.checker.itb.hits 61778177 # DTB hits
+system.cpu.checker.itb.inst_accesses 61780571 # ITB inst accesses
+system.cpu.checker.itb.hits 61776100 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61782648 # DTB accesses
-system.cpu.checker.numCycles 78238784 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61780571 # DTB accesses
+system.cpu.checker.numCycles 78236084 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51719750 # DTB read hits
-system.cpu.dtb.read_misses 77229 # DTB read misses
-system.cpu.dtb.write_hits 11809411 # DTB write hits
-system.cpu.dtb.write_misses 17373 # DTB write misses
+system.cpu.dtb.read_hits 51390867 # DTB read hits
+system.cpu.dtb.read_misses 77330 # DTB read misses
+system.cpu.dtb.write_hits 11807590 # DTB write hits
+system.cpu.dtb.write_misses 17145 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7767 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2639 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 7744 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2913 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 528 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1315 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51796979 # DTB read accesses
-system.cpu.dtb.write_accesses 11826784 # DTB write accesses
+system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51468197 # DTB read accesses
+system.cpu.dtb.write_accesses 11824735 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63529161 # DTB hits
-system.cpu.dtb.misses 94602 # DTB misses
-system.cpu.dtb.accesses 63623763 # DTB accesses
-system.cpu.itb.inst_hits 13045523 # ITB inst hits
-system.cpu.itb.inst_misses 12142 # ITB inst misses
+system.cpu.dtb.hits 63198457 # DTB hits
+system.cpu.dtb.misses 94475 # DTB misses
+system.cpu.dtb.accesses 63292932 # DTB accesses
+system.cpu.itb.inst_hits 11866859 # ITB inst hits
+system.cpu.itb.inst_misses 12387 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5168 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 5196 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 3109 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 3124 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13057665 # ITB inst accesses
-system.cpu.itb.hits 13045523 # DTB hits
-system.cpu.itb.misses 12142 # DTB misses
-system.cpu.itb.accesses 13057665 # DTB accesses
-system.cpu.numCycles 475815628 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11879246 # ITB inst accesses
+system.cpu.itb.hits 11866859 # DTB hits
+system.cpu.itb.misses 12387 # DTB misses
+system.cpu.itb.accesses 11879246 # DTB accesses
+system.cpu.numCycles 471620131 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15155227 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12146705 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 783529 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10394615 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8308125 # Number of BTB hits
+system.cpu.BPredUnit.lookups 14707897 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11700483 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 783548 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 9751137 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7864369 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1454278 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 82490 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 31347726 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 100822937 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15155227 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9762403 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22167713 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5923551 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 130252 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 97680521 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2843 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 98238 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 209120 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13041690 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1002552 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6432 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 155704074 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.799073 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.166371 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1453661 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 82859 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 30173854 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 91943847 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14707897 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9318030 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20602156 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4980521 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 134933 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 96636325 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2675 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 101652 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 208965 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11862984 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 731347 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6597 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151294412 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.758755 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.115735 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 133553129 85.77% 85.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1381799 0.89% 86.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1755926 1.13% 87.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2652519 1.70% 89.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2328486 1.50% 90.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1136180 0.73% 91.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2905092 1.87% 93.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 785179 0.50% 94.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9205764 5.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130709145 86.39% 86.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1380335 0.91% 87.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1756131 1.16% 88.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2339631 1.55% 90.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2142384 1.42% 91.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1132136 0.75% 92.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2619139 1.73% 93.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 785245 0.52% 94.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8430266 5.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 155704074 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031851 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.211895 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 33480524 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 97304946 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19992509 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1030333 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3895762 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2022425 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 174533 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 117498058 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 576273 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3895762 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 35565671 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37584641 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 53601603 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18869314 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6187083 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 110088875 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21357 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1014287 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4146063 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 32391 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 114923514 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 504161217 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 504070393 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78734130 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36189383 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 892416 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 798033 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12508562 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20972747 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13834973 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1961849 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2465756 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 100830951 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2058696 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 126177528 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 189533 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 24329335 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 64639752 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 514100 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 155704074 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.810368 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.523012 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151294412 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.194953 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32008731 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96268896 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18723702 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1031258 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3261825 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2020367 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 174818 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 109258714 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3261825 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33805354 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36852775 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 53319596 # count of cycles rename stalled for serializing inst
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+system.cpu.rename.UnblockCycles 6153748 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 104067610 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21499 # Number of times rename has blocked due to ROB full
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+system.cpu.rename.LSQFullEvents 4122290 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 31949 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 107816884 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 475027641 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 474936857 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90784 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78731329 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 29085554 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 891358 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 796895 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12333147 # count of insts added to the skid buffer
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+system.cpu.memDep0.conflictingLoads 1975115 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2433562 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 96511960 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2056994 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 123962105 # Number of instructions issued
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+system.cpu.iq.iqSquashedInstsExamined 20009013 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 50083503 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::4 12721239 8.17% 96.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2798387 1.80% 98.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1680857 1.08% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 475213 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126955 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106913550 70.67% 70.67% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::2 7098415 4.69% 84.52% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::6 1718676 1.14% 99.61% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 155704074 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151294412 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8370496 94.62% 95.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 418270 4.73% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 56852 0.64% 0.64% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8372882 94.63% 95.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 417861 4.72% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59895243 47.47% 47.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95317 0.08% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 7 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53367566 42.30% 90.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12453578 9.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58285332 47.02% 47.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95139 0.08% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52764596 42.57% 89.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12451206 10.04% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 126177528 # Type of FU issued
-system.cpu.iq.rate 0.265182 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8846360 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.070110 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 417165828 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 127235505 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87177257 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23405 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 134647760 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12462 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 624931 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 123962105 # Type of FU issued
+system.cpu.iq.rate 0.262843 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8847599 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071373 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 408327002 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 118594240 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86288141 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23234 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12518 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10286 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132433714 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12324 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 628913 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5256081 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7285 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30200 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2036035 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4346263 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7649 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 29949 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1722835 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34106907 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1030049 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107855 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 695994 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3895762 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28674144 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 449674 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 103114750 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 233495 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20972747 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13834973 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1466916 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113563 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3765 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30200 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 409921 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 292907 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 702828 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 122963273 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52407414 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3214255 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3261825 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27934565 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 435305 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 98793776 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 231675 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20062338 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13521403 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1465659 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 113955 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3708 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 29949 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 409673 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 293589 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 703262 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121754884 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52078341 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2207221 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 225103 # number of nop insts executed
-system.cpu.iew.exec_refs 64729141 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11726228 # Number of branches executed
-system.cpu.iew.exec_stores 12321727 # Number of stores executed
-system.cpu.iew.exec_rate 0.258426 # Inst execution rate
-system.cpu.iew.wb_sent 121618308 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 87187548 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47710631 # num instructions producing a value
-system.cpu.iew.wb_consumers 88857501 # num instructions consuming a value
+system.cpu.iew.exec_nop 224822 # number of nop insts executed
+system.cpu.iew.exec_refs 64398044 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11600510 # Number of branches executed
+system.cpu.iew.exec_stores 12319703 # Number of stores executed
+system.cpu.iew.exec_rate 0.258163 # Inst execution rate
+system.cpu.iew.wb_sent 120731241 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 86298427 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47352499 # num instructions producing a value
+system.cpu.iew.wb_consumers 88423671 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.183238 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182983 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535518 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24186815 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1544596 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 612016 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 151890748 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.514176 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.495245 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 19868331 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1544505 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 611839 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 148115015 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.527265 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.512607 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 124092082 81.70% 81.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13579714 8.94% 90.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3980091 2.62% 93.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2134436 1.41% 94.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1949184 1.28% 95.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1000796 0.66% 96.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1579621 1.04% 97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 721647 0.48% 98.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2853177 1.88% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120340532 81.25% 81.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13566988 9.16% 90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3964696 2.68% 93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2137699 1.44% 94.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1955021 1.32% 95.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 974024 0.66% 96.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1590640 1.07% 97.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 730936 0.49% 98.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2854479 1.93% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 151890748 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60749791 # Number of instructions committed
-system.cpu.commit.committedOps 78098591 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 148115015 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60747728 # Number of instructions committed
+system.cpu.commit.committedOps 78095905 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27515604 # Number of memory references committed
-system.cpu.commit.loads 15716666 # Number of loads committed
-system.cpu.commit.membars 413138 # Number of memory barriers committed
-system.cpu.commit.branches 10023383 # Number of branches committed
+system.cpu.commit.refs 27514643 # Number of memory references committed
+system.cpu.commit.loads 15716075 # Number of loads committed
+system.cpu.commit.membars 413107 # Number of memory barriers committed
+system.cpu.commit.branches 10023098 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69136784 # Number of committed integer instructions.
-system.cpu.commit.function_calls 996034 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2853177 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 69134339 # Number of committed integer instructions.
+system.cpu.commit.function_calls 995983 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2854479 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 249407638 # The number of ROB reads
-system.cpu.rob.rob_writes 208557399 # The number of ROB writes
-system.cpu.timesIdled 1773714 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320111554 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4592442776 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60599410 # Number of Instructions Simulated
-system.cpu.committedOps 77948210 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60599410 # Number of Instructions Simulated
-system.cpu.cpi 7.851819 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.851819 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.127359 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.127359 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 556670721 # number of integer regfile reads
-system.cpu.int_regfile_writes 89963166 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8373 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2910 # number of floating regfile writes
-system.cpu.misc_regfile_reads 132949410 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912934 # number of misc regfile writes
-system.cpu.icache.replacements 989799 # number of replacements
-system.cpu.icache.tagsinuse 511.593898 # Cycle average of tags in use
-system.cpu.icache.total_refs 11967809 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 990311 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 12.084900 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6924990000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.593898 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999207 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999207 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 11967809 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 11967809 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 11967809 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 11967809 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 11967809 # number of overall hits
-system.cpu.icache.overall_hits::total 11967809 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1073749 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1073749 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1073749 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1073749 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1073749 # number of overall misses
-system.cpu.icache.overall_misses::total 1073749 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14109467991 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14109467991 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14109467991 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14109467991 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14109467991 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14109467991 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13041558 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13041558 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13041558 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13041558 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13041558 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13041558 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082333 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.082333 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.082333 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.082333 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.082333 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.082333 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13140.378236 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13140.378236 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13140.378236 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13140.378236 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13140.378236 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 4599 # number of cycles access was blocked
+system.cpu.rob.rob_reads 241309637 # The number of ROB reads
+system.cpu.rob.rob_writes 199282329 # The number of ROB writes
+system.cpu.timesIdled 1774359 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320325719 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575563546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60597347 # Number of Instructions Simulated
+system.cpu.committedOps 77945524 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60597347 # Number of Instructions Simulated
+system.cpu.cpi 7.782851 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.782851 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 551501620 # number of integer regfile reads
+system.cpu.int_regfile_writes 88408652 # number of integer regfile writes
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+system.cpu.misc_regfile_writes 912885 # number of misc regfile writes
+system.cpu.icache.replacements 990639 # number of replacements
+system.cpu.icache.tagsinuse 510.412932 # Cycle average of tags in use
+system.cpu.icache.total_refs 10788740 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 991151 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 10.885062 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 510.412932 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.996900 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.996900 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 10788740 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 10788740 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 10788740 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 10788740 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1074113 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1074113 # number of ReadReq misses
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+system.cpu.icache.overall_misses::total 1074113 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14116777488 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14116777488 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14116777488 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14116777488 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14116777488 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14116777488 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11862853 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total 11862853 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11862853 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11862853 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.090544 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.090544 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.090544 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.090544 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.090544 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.090544 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13142.730316 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13142.730316 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13142.730316 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13142.730316 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13142.730316 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13142.730316 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 4157 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 306 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 287 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 15.029412 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 14.484321 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11592.099877 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu.l2cache.replacements 64413 # number of replacements
-system.cpu.l2cache.tagsinuse 51352.307141 # Cycle average of tags in use
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-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5363194498 # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5292000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166679722000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166685014000 # number of ReadReq MSHR uncacheable cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198964561499 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198969853499 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000664 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000086 # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222789 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41044.839598 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40459.418744 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40773.060165 # average ReadReq mshr miss latency
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-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40005.288298 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40261.502586 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40261.502586 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40490.909091 # average overall mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40337.019024 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41044.839598 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40276.179957 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1202929249396 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1202929249396 # number of overall MSHR uncacheable cycles
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system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88035 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88028 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.603785 # Number of seconds simulated
-sim_ticks 2603784540500 # Number of ticks simulated
-final_tick 2603784540500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.003417 # Number of seconds simulated
+sim_ticks 1003417221500 # Number of ticks simulated
+final_tick 1003417221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 66983 # Simulator instruction rate (inst/s)
-host_op_rate 86203 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2766471262 # Simulator tick rate (ticks/s)
-host_mem_usage 391460 # Number of bytes of host memory used
-host_seconds 941.19 # Real time elapsed on the host
-sim_insts 63043892 # Number of instructions simulated
-sim_ops 81133946 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
+host_inst_rate 74785 # Simulator instruction rate (inst/s)
+host_op_rate 96230 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1214309093 # Simulator tick rate (ticks/s)
+host_mem_usage 406952 # Number of bytes of host memory used
+host_seconds 826.33 # Real time elapsed on the host
+sim_insts 61797296 # Number of instructions simulated
+sim_ops 79517775 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd 44040192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 398208 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4365108 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 424768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5242032 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131542884 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 398208 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 424768 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 822976 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4259200 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 410432 # Number of bytes read from this memory
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+system.physmem.bytes_read::cpu1.data 5217200 # Number of bytes read from this memory
+system.physmem.bytes_read::total 54451236 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 410432 # Number of instructions bytes read from this memory
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+system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4253056 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7288336 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
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+system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7280144 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 5505024 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6222 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 68277 # Number of read requests responded to by this memory
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-system.physmem.num_reads::cpu1.inst 6637 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 81933 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15301920 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66550 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 823834 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46513268 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 152934 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1676447 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 516 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 163135 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 2013236 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50519881 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 152934 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 163135 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 316069 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1635773 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6529 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 1156830 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2799132 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1635773 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46513268 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 152934 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1682976 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 516 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 163135 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 3170066 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53319012 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 823226 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43890209 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 957 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 128 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 409034 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 4361787 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 957 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 403294 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 5199432 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 54265798 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 409034 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 403294 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 812328 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4238572 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 16942 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2999837 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 7255351 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4238572 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43890209 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 957 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 128 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 409034 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 4378729 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 957 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 403294 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 8199269 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 61521149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5667795 # Total number of read requests seen
+system.physmem.writeReqs 823226 # Total number of write requests seen
+system.physmem.cpureqs 281286 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 362738880 # Total number of bytes read from memory
+system.physmem.bytesWritten 52686464 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 54451236 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7280144 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 148 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 12596 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 354151 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 354519 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 354412 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 354404 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 354227 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 354027 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 353803 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 353914 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 354718 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 354198 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 354245 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 354391 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 354136 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 354309 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 354144 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 354049 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50660 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50996 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50931 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50952 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51753 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 51624 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 51424 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 51487 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51960 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51682 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51566 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51627 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51620 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51748 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51624 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51572 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 1152068 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1003416092000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 105 # Categorize read packet sizes
+system.physmem.readPktSize::3 5505024 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 162666 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 1908840 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 66454 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 12596 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 5540802 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 75454 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 7331 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2660 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2178 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1962 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1847 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1666 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1365 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1309 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1343 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 6450 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 9578 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 13035 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 550 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 66 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 35 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3176 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3360 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3508 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3617 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3779 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3969 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4192 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4384 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4579 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35793 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35792 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32617 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32433 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32285 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32176 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32014 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 31824 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 31601 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31409 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31214 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 46980948909 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 148397952909 # Sum of mem lat for all requests
+system.physmem.totBusLat 22670588000 # Total cycles spent in databus access
+system.physmem.totBankLat 78746416000 # Total cycles spent in bank access
+system.physmem.avgQLat 8289.32 # Average queueing delay per request
+system.physmem.avgBankLat 13894.02 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 26183.34 # Average memory access latency
+system.physmem.avgRdBW 361.50 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 52.51 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 54.27 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 7.26 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 2.59 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.15 # Average read queue length over time
+system.physmem.avgWrQLen 11.87 # Average write queue length over time
+system.physmem.readRowHits 5638305 # Number of row buffer hits during reads
+system.physmem.writeRowHits 788804 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.48 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 95.82 # Row buffer hit rate for writes
+system.physmem.avgGap 154585.25 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 72716 # number of replacements
-system.l2c.tagsinuse 53054.127627 # Cycle average of tags in use
-system.l2c.total_refs 1921007 # Total number of references to valid blocks.
-system.l2c.sampled_refs 137887 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.931748 # Average number of references to valid blocks.
+system.realview.nvmem.bw_read::cpu0.inst 64 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 383 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 446 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 64 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 383 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 446 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 64 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 383 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 446 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 72379 # number of replacements
+system.l2c.tagsinuse 54036.280833 # Cycle average of tags in use
+system.l2c.total_refs 1885694 # Total number of references to valid blocks.
+system.l2c.sampled_refs 137571 # Sample count of references to valid blocks.
+system.l2c.avg_refs 13.707060 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 37702.750245 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 4.539457 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.000261 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4229.509835 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 2960.828509 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 15.234392 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 4027.989211 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 4113.275716 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.575298 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.064537 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.045179 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker 0.000232 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.061462 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.062764 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.809542 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 35167 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 5217 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 398405 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 165702 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 54913 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 6451 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 614994 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 202172 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1483021 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 584447 # number of Writeback hits
-system.l2c.Writeback_hits::total 584447 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 1035 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 765 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1800 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 171 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 381 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 48064 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 58867 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 106931 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 35167 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 5217 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 398405 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 213766 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 54913 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 6451 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 614994 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 261039 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1589952 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 35167 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 5217 # number of overall hits
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43095.384144 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40553.319947 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53901.866667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39862.102976 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37453.051352 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55368.533333 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42142.290220 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43095.384144 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40553.319947 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 9065848 # DTB read hits
-system.cpu0.dtb.read_misses 36360 # DTB read misses
-system.cpu0.dtb.write_hits 5285915 # DTB write hits
-system.cpu0.dtb.write_misses 6625 # DTB write misses
+system.cpu0.dtb.read_hits 8990701 # DTB read hits
+system.cpu0.dtb.read_misses 35639 # DTB read misses
+system.cpu0.dtb.write_hits 5196869 # DTB write hits
+system.cpu0.dtb.write_misses 6420 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2165 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 342 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 2140 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1264 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 358 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 9102208 # DTB read accesses
-system.cpu0.dtb.write_accesses 5292540 # DTB write accesses
+system.cpu0.dtb.perms_faults 552 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 9026340 # DTB read accesses
+system.cpu0.dtb.write_accesses 5203289 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14351763 # DTB hits
-system.cpu0.dtb.misses 42985 # DTB misses
-system.cpu0.dtb.accesses 14394748 # DTB accesses
-system.cpu0.itb.inst_hits 4413372 # ITB inst hits
-system.cpu0.itb.inst_misses 5476 # ITB inst misses
+system.cpu0.dtb.hits 14187570 # DTB hits
+system.cpu0.dtb.misses 42059 # DTB misses
+system.cpu0.dtb.accesses 14229629 # DTB accesses
+system.cpu0.itb.inst_hits 4354083 # ITB inst hits
+system.cpu0.itb.inst_misses 5531 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1363 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1472 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1565 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4418848 # ITB inst accesses
-system.cpu0.itb.hits 4413372 # DTB hits
-system.cpu0.itb.misses 5476 # DTB misses
-system.cpu0.itb.accesses 4418848 # DTB accesses
-system.cpu0.numCycles 70012496 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4359614 # ITB inst accesses
+system.cpu0.itb.hits 4354083 # DTB hits
+system.cpu0.itb.misses 5531 # DTB misses
+system.cpu0.itb.accesses 4359614 # DTB accesses
+system.cpu0.numCycles 68779590 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 6217398 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 4733750 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 327130 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 4014715 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 3051469 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 6151354 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 4687077 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 326469 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 3738602 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 3006788 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 700588 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 31775 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 12151517 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 33217564 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6217398 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3752057 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7806548 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1581421 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 67728 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 22157211 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 5913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 54633 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 92488 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4411708 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 171100 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2593 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 43471985 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.986228 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.366083 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 689169 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 32083 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 11912972 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 32706056 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6151354 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3695957 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7689921 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1565411 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 62995 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 21287015 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 56402 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4352320 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 172729 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2628 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 42226826 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.000152 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.378860 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 35673429 82.06% 82.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 623255 1.43% 83.49% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 822107 1.89% 85.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 699884 1.61% 87.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 794381 1.83% 88.82% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 577438 1.33% 90.15% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 719535 1.66% 91.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 371399 0.85% 92.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3190557 7.34% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 34545116 81.81% 81.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 600326 1.42% 83.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 813270 1.93% 85.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 699242 1.66% 86.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 789636 1.87% 88.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 563805 1.34% 90.02% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 711205 1.68% 91.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 369975 0.88% 92.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3134251 7.42% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 43471985 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.088804 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.474452 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12679354 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 22114744 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 7023055 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 583785 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1071047 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 976895 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 65884 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 41430285 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 215511 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1071047 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 13270486 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5876098 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 14061413 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6963478 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2229463 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 40231881 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 2342 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 440788 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1249784 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 63 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 40621534 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 181781749 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 181747462 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34287 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 31667723 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8953810 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 461246 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 417498 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5499956 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7912486 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5888217 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1140849 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1237786 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 37992607 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 949484 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 38225982 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 89034 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6781394 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 14357702 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 260797 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 43471985 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.879325 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.495049 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 42226826 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.089436 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.475520 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12413850 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 21262916 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6920770 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 571279 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1058011 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 957289 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 65649 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 40810463 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 214284 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1058011 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 12995838 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5806909 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13316140 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6858946 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2190982 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 39610027 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 2116 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 435032 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1231897 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 105 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 39982485 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 178864927 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 178830724 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 34203 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 31105315 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8877169 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 451261 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 410052 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5376793 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7771036 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5796008 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1117778 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1234382 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 37385936 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 932152 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37680469 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 87348 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6705798 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 14225412 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 253293 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 42226826 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.892335 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 27798434 63.95% 63.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 6055917 13.93% 77.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3289826 7.57% 85.44% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2491193 5.73% 91.17% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2118698 4.87% 96.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 969648 2.23% 98.28% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 500024 1.15% 99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 192302 0.44% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 55943 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 26789201 63.44% 63.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5974229 14.15% 77.59% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3183905 7.54% 85.13% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2487856 5.89% 91.02% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2118052 5.02% 96.04% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 933005 2.21% 98.25% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 499456 1.18% 99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 188083 0.45% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 53039 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 43471985 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 42226826 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 25214 2.35% 2.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 458 0.04% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 837969 78.03% 80.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 210208 19.58% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 25386 2.38% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 456 0.04% 2.42% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::MemRead 843676 78.98% 81.40% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 198710 18.60% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22961950 60.07% 60.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 49879 0.13% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued
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-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued
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-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9545903 24.97% 85.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5615312 14.69% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22597326 59.97% 60.11% # Type of FU issued
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+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.24% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued
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+system.cpu0.iq.FU_type_0::MemRead 9468734 25.13% 85.37% # Type of FU issued
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system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 38225982 # Type of FU issued
-system.cpu0.iq.rate 0.545988 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1073849 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028092 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 121121114 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 45731569 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 35283041 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8365 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4658 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3880 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 39243245 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4372 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 321528 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37680469 # Type of FU issued
+system.cpu0.iq.rate 0.547844 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1068228 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.028350 # FU busy rate (busy events/executed inst)
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+system.cpu0.iq.int_inst_queue_writes 45031578 # Number of integer instruction queue writes
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+system.cpu0.iq.fp_inst_queue_reads 8278 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4652 # Number of floating instruction queue writes
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+system.cpu0.iq.fp_alu_accesses 4305 # Number of floating point alu accesses
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system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1492825 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3508 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13401 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 615446 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1466992 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3639 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 12971 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 614314 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2149535 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5390 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2192663 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5266 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1071047 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4218607 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 98464 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 39061403 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 95550 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7912486 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5888217 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 616723 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 40108 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 2851 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13401 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 172679 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 129654 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 302333 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 37800204 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9383648 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 425778 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1058011 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 4168228 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 100403 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 38437075 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 94997 # Number of squashed instructions skipped by dispatch
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+system.cpu0.iew.iewLSQFullEvents 3188 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 12971 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 173285 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 127529 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 300814 # Number of branch mispredicts detected at execute
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system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 119312 # number of nop insts executed
-system.cpu0.iew.exec_refs 14941647 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4991029 # Number of branches executed
-system.cpu0.iew.exec_stores 5557999 # Number of stores executed
-system.cpu0.iew.exec_rate 0.539907 # Inst execution rate
-system.cpu0.iew.wb_sent 37583639 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 35286921 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18740450 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35992151 # num instructions consuming a value
+system.cpu0.iew.exec_nop 118987 # number of nop insts executed
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+system.cpu0.iew.exec_stores 5455303 # Number of stores executed
+system.cpu0.iew.exec_rate 0.541811 # Inst execution rate
+system.cpu0.iew.wb_sent 37049261 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 34710512 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18431396 # num instructions producing a value
+system.cpu0.iew.wb_consumers 35371181 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.504009 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.520682 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.504663 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.521085 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6642216 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 688687 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 262418 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 42437322 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.753690 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.709171 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6565608 # The number of squashed insts skipped by commit
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+system.cpu0.commit.branchMispredicts 262014 # The number of times a branch was mispredicted
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+system.cpu0.commit.committed_per_cycle::mean 0.762989 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.718954 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 30360862 71.54% 71.54% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5984991 14.10% 85.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1981270 4.67% 90.31% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1011467 2.38% 92.70% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 801137 1.89% 94.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 524678 1.24% 95.82% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 395620 0.93% 96.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 217374 0.51% 97.27% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1159923 2.73% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 29337596 71.20% 71.20% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5890386 14.30% 85.50% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1942613 4.71% 90.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 987342 2.40% 92.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 788686 1.91% 94.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 508616 1.23% 95.75% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 388471 0.94% 96.70% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 215239 0.52% 97.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1145721 2.78% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 42437322 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 24255943 # Number of instructions committed
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-system.cpu0.cpi 2.896046 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.896046 # CPI: Total CPI of All Threads
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2337539000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2337539000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4029396491 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4029396491 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66744000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66744000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31921000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31921000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6366935491 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6366935491 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6366935491 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6366935491 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13497539000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13497539000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1126787391 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1126787391 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14624326391 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14624326391 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030296 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030296 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027498 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027498 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045785 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045785 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.041703 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.041703 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029086 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029086 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029086 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029086 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12408.439190 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12408.439190 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30901.701696 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30901.701696 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7985.642498 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7985.642498 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4280.101904 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4280.101904 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19973.007748 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19973.007748 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19973.007748 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19973.007748 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 43411799 # DTB read hits
-system.cpu1.dtb.read_misses 44882 # DTB read misses
-system.cpu1.dtb.write_hits 7014123 # DTB write hits
-system.cpu1.dtb.write_misses 11858 # DTB write misses
+system.cpu1.dtb.read_hits 42793425 # DTB read hits
+system.cpu1.dtb.read_misses 43166 # DTB read misses
+system.cpu1.dtb.write_hits 6855715 # DTB write hits
+system.cpu1.dtb.write_misses 11673 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2347 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 3336 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 317 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2301 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 3409 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 352 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 43456681 # DTB read accesses
-system.cpu1.dtb.write_accesses 7025981 # DTB write accesses
+system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 42836591 # DTB read accesses
+system.cpu1.dtb.write_accesses 6867388 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 50425922 # DTB hits
-system.cpu1.dtb.misses 56740 # DTB misses
-system.cpu1.dtb.accesses 50482662 # DTB accesses
-system.cpu1.itb.inst_hits 9129638 # ITB inst hits
-system.cpu1.itb.inst_misses 6055 # ITB inst misses
+system.cpu1.dtb.hits 49649140 # DTB hits
+system.cpu1.dtb.misses 54839 # DTB misses
+system.cpu1.dtb.accesses 49703979 # DTB accesses
+system.cpu1.itb.inst_hits 7790428 # ITB inst hits
+system.cpu1.itb.inst_misses 6195 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1576 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1551 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1653 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1608 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 9135693 # ITB inst accesses
-system.cpu1.itb.hits 9129638 # DTB hits
-system.cpu1.itb.misses 6055 # DTB misses
-system.cpu1.itb.accesses 9135693 # DTB accesses
-system.cpu1.numCycles 413048277 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 7796623 # ITB inst accesses
+system.cpu1.itb.hits 7790428 # DTB hits
+system.cpu1.itb.misses 6195 # DTB misses
+system.cpu1.itb.accesses 7796623 # DTB accesses
+system.cpu1.numCycles 407481845 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 9610060 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 7888453 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 467347 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 6680212 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 5602853 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 8945563 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 7276620 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 457303 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 6059330 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 5044901 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 834872 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 50683 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 20902821 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 71155819 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9610060 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 6437725 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 15200148 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 4519747 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 75962 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 79085155 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 48956 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 142448 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 9127576 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 837727 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3443 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 118542872 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.725366 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.076680 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 808900 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 49599 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 19209398 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 61160390 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 8945563 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 5853801 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 13372143 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3528800 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 72716 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 77592776 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 4530 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 48363 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 137630 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 7788411 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 558980 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3579 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 112853111 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.663918 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.993452 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 103350754 87.18% 87.18% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 840912 0.71% 87.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 1013712 0.86% 88.75% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 2056350 1.73% 90.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1628340 1.37% 91.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 605586 0.51% 92.37% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 2262195 1.91% 94.28% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 445115 0.38% 94.65% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 6339908 5.35% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 99488795 88.16% 88.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 820731 0.73% 88.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 982302 0.87% 89.76% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1718236 1.52% 91.28% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1416689 1.26% 92.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 588425 0.52% 93.05% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1946926 1.73% 94.78% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 433337 0.38% 95.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5457670 4.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 118542872 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.023266 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.172270 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 22607772 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 78712094 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 13698658 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 543937 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2980411 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1178240 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 102814 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 80488884 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 342985 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2980411 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 24131061 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 32829819 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 41497762 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 12625753 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4478066 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 74194515 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 19311 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 694411 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3187694 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 34028 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 78612274 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 341980095 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 341920829 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 50181552 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 28430722 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 479709 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 419295 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 8182404 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 13956070 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8535310 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1073815 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1496663 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 66987245 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1207542 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 91662010 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 107326 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 18596353 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 52788554 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 287891 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 118542872 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.773239 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.509704 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 112853111 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.021953 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.150094 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 20594111 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 77223821 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 12189210 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 529456 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2316513 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1140486 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 100773 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 70872122 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 333080 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2316513 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 21811188 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 31999564 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 40913868 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 11406608 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4405370 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 66851676 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 19516 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 679552 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3147713 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 33677 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 70148588 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 306845192 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 306785894 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 59298 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 49106817 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 21041771 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 463027 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 405725 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 7962793 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 12778752 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 8032472 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1035556 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1464082 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 61394803 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1176532 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 88185041 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 108507 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 14048968 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 37726295 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 276552 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 112853111 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.781414 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.519020 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 87045508 73.43% 73.43% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 8827320 7.45% 80.88% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4565356 3.85% 84.73% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3971386 3.35% 88.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10748062 9.07% 97.14% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1958505 1.65% 98.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1059536 0.89% 99.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 289761 0.24% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 77438 0.07% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 82669825 73.25% 73.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8481760 7.52% 80.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 4273659 3.79% 84.56% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3671895 3.25% 87.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10427666 9.24% 97.05% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1949609 1.73% 98.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1042899 0.92% 99.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 262209 0.23% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 73589 0.07% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 118542872 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 112853111 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 27804 0.35% 0.35% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 991 0.01% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 26972 0.34% 0.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 996 0.01% 0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7575099 95.91% 96.28% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 294066 3.72% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7550123 96.09% 96.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 279583 3.56% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 39285679 42.86% 43.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 61425 0.07% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 44600762 48.66% 91.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7398685 8.07% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 313997 0.36% 0.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 36904735 41.85% 42.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 59478 0.07% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1462 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 43687858 49.54% 91.82% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7217483 8.18% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 91662010 # Type of FU issued
-system.cpu1.iq.rate 0.221916 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7897960 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.086164 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 309913949 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 86800137 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 55536555 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 14796 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 99238492 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7741 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 357612 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 88185041 # Type of FU issued
+system.cpu1.iq.rate 0.216415 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7857674 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.089104 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 297228981 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 76628774 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 53465228 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 15030 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8076 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6856 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 95720841 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7877 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 343881 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 3966417 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 4317 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 17649 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1516764 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 3018668 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 4236 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17116 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1176826 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31964885 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 1028430 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31906521 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 692078 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2980411 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 24884610 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 372296 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 68300564 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 134907 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 13956070 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8535310 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 896808 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 67508 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3396 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 17649 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 244559 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 171299 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 415858 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 88842251 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43794323 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2819759 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2316513 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 24121346 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 362647 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 62677152 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 130612 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 12778752 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 8032472 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 873727 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 64946 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17116 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 239035 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 168853 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 407888 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 86386034 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43162344 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1799007 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 105777 # number of nop insts executed
-system.cpu1.iew.exec_refs 51113945 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 7256967 # Number of branches executed
-system.cpu1.iew.exec_stores 7319622 # Number of stores executed
-system.cpu1.iew.exec_rate 0.215089 # Inst execution rate
-system.cpu1.iew.wb_sent 87693649 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 55543356 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 30809625 # num instructions producing a value
-system.cpu1.iew.wb_consumers 54951337 # num instructions consuming a value
+system.cpu1.iew.exec_nop 105817 # number of nop insts executed
+system.cpu1.iew.exec_refs 50303914 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 6949979 # Number of branches executed
+system.cpu1.iew.exec_stores 7141570 # Number of stores executed
+system.cpu1.iew.exec_rate 0.212000 # Inst execution rate
+system.cpu1.iew.wb_sent 85560494 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 53472084 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 29815301 # num instructions producing a value
+system.cpu1.iew.wb_consumers 53181116 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.134472 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.560671 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.131226 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.560637 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 18558974 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 919651 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 366370 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 115610884 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.426428 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.387814 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 14046998 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 899980 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 358444 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 110583599 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.436135 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.404322 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 98380656 85.10% 85.10% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8456019 7.31% 92.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2240447 1.94% 94.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1287846 1.11% 95.46% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1284560 1.11% 96.57% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 584416 0.51% 97.08% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1022455 0.88% 97.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 531646 0.46% 98.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1822839 1.58% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 93772628 84.80% 84.80% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8260056 7.47% 92.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2160964 1.95% 94.22% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1246626 1.13% 95.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1244768 1.13% 96.47% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 580382 0.52% 97.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 994186 0.90% 97.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 530445 0.48% 98.38% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1793544 1.62% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 115610884 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38938330 # Number of instructions committed
-system.cpu1.commit.committedOps 49299735 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 110583599 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38115610 # Number of instructions committed
+system.cpu1.commit.committedOps 48229427 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 17008199 # Number of memory references committed
-system.cpu1.commit.loads 9989653 # Number of loads committed
-system.cpu1.commit.membars 202304 # Number of memory barriers committed
-system.cpu1.commit.branches 6136573 # Number of branches committed
-system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 43691789 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 556207 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1822839 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 16615730 # Number of memory references committed
+system.cpu1.commit.loads 9760084 # Number of loads committed
+system.cpu1.commit.membars 196512 # Number of memory barriers committed
+system.cpu1.commit.branches 5981373 # Number of branches committed
+system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 42745221 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 536771 # Number of function calls committed.
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-system.cpu1.cpi 10.626761 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 10.626761 # CPI: Total CPI of All Threads
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.demand_mshr_miss_latency::total 7328903994 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8073339214 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8073339214 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 8073339214 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168945425000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168945425000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26941470024 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26941470024 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195886895024 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195886895024 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026029 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026029 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028353 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028353 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108401 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108401 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096945 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096945 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026944 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026944 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026944 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.026944 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12330.303229 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12330.303229 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32442.684686 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32442.684686 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7109.463722 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7109.463722 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3039.469948 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3039.469948 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20661.982868 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20661.982868 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20661.982868 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20661.982868 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1218779341193 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1218779341193 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 421898642152 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 421898642152 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 421898642152 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 421898642152 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 43799 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 43084 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 53911 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 52242 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.534173 # Number of seconds simulated
-sim_ticks 2534173219000 # Number of ticks simulated
-final_tick 2534173219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.523636 # Number of seconds simulated
+sim_ticks 2523635852000 # Number of ticks simulated
+final_tick 2523635852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 83771 # Simulator instruction rate (inst/s)
-host_op_rate 107754 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3503174864 # Simulator tick rate (ticks/s)
-host_mem_usage 385312 # Number of bytes of host memory used
-host_seconds 723.39 # Real time elapsed on the host
-sim_insts 60599410 # Number of instructions simulated
-sim_ops 77948210 # Number of ops (including micro ops) simulated
+host_inst_rate 45530 # Simulator instruction rate (inst/s)
+host_op_rate 58565 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1896155435 # Simulator tick rate (ticks/s)
+host_mem_usage 399768 # Number of bytes of host memory used
+host_seconds 1330.92 # Real time elapsed on the host
+sim_insts 60597347 # Number of instructions simulated
+sim_ops 77945524 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798080 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9096016 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129435344 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798080 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798080 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 799360 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129436368 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 799360 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 799360 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 56 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12470 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142159 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096893 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12490 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096909 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47170281 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1389 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47367240 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1420 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314927 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51075966 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314927 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314927 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493669 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190160 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683829 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493669 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47170281 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1389 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 316749 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3604203 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51289637 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 316749 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 316749 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499145 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1195130 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2694275 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1499145 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47367240 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1420 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314927 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4779503 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53759795 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 316749 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4799333 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53983912 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096909 # Total number of read requests seen
+system.physmem.writeReqs 813132 # Total number of write requests seen
+system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966202176 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040448 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129436368 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 363 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943955 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943427 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 943468 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943391 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943248 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943111 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943293 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943780 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943638 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943709 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943744 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 943610 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 943654 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50098 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 49973 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50033 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50667 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50819 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51122 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51107 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51166 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51028 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 1156323 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2523634566000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 36 # Categorize read packet sizes
+system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 154665 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 1910341 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 59114 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 14955787 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 89824 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 6501 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2877 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2340 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2145 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1923 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1719 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1284 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1282 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1247 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 6296 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 9574 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 13083 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 566 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 49 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 32 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2806 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2951 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3069 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3199 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3759 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 3930 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4091 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32548 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32403 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32285 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32155 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 31424 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 31263 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 46870409147 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 317530293147 # Sum of mem lat for all requests
+system.physmem.totBusLat 60386184000 # Total cycles spent in databus access
+system.physmem.totBankLat 210273700000 # Total cycles spent in bank access
+system.physmem.avgQLat 3104.71 # Average queueing delay per request
+system.physmem.avgBankLat 13928.60 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 21033.31 # Average memory access latency
+system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 2.52 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.13 # Average read queue length over time
+system.physmem.avgWrQLen 12.37 # Average write queue length over time
+system.physmem.readRowHits 15050555 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784512 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 96.48 # Row buffer hit rate for writes
+system.physmem.avgGap 158618.99 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51719750 # DTB read hits
-system.cpu.dtb.read_misses 77229 # DTB read misses
-system.cpu.dtb.write_hits 11809411 # DTB write hits
-system.cpu.dtb.write_misses 17373 # DTB write misses
+system.cpu.dtb.read_hits 51390867 # DTB read hits
+system.cpu.dtb.read_misses 77330 # DTB read misses
+system.cpu.dtb.write_hits 11807590 # DTB write hits
+system.cpu.dtb.write_misses 17145 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4263 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2639 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4249 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2913 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 528 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1315 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51796979 # DTB read accesses
-system.cpu.dtb.write_accesses 11826784 # DTB write accesses
+system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51468197 # DTB read accesses
+system.cpu.dtb.write_accesses 11824735 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63529161 # DTB hits
-system.cpu.dtb.misses 94602 # DTB misses
-system.cpu.dtb.accesses 63623763 # DTB accesses
-system.cpu.itb.inst_hits 13045523 # ITB inst hits
-system.cpu.itb.inst_misses 12142 # ITB inst misses
+system.cpu.dtb.hits 63198457 # DTB hits
+system.cpu.dtb.misses 94475 # DTB misses
+system.cpu.dtb.accesses 63292932 # DTB accesses
+system.cpu.itb.inst_hits 11866859 # ITB inst hits
+system.cpu.itb.inst_misses 12387 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2586 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2600 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 3109 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 3124 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13057665 # ITB inst accesses
-system.cpu.itb.hits 13045523 # DTB hits
-system.cpu.itb.misses 12142 # DTB misses
-system.cpu.itb.accesses 13057665 # DTB accesses
-system.cpu.numCycles 475815628 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11879246 # ITB inst accesses
+system.cpu.itb.hits 11866859 # DTB hits
+system.cpu.itb.misses 12387 # DTB misses
+system.cpu.itb.accesses 11879246 # DTB accesses
+system.cpu.numCycles 471620131 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15155227 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12146705 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 783529 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10394615 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8308125 # Number of BTB hits
+system.cpu.BPredUnit.lookups 14707897 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11700483 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 783548 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 9751137 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7864369 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1454278 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 82490 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 31347726 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 100822937 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15155227 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9762403 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22167713 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5923551 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 130252 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 97680521 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2843 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 98238 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 209120 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13041690 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1002552 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6432 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 155704074 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.799073 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.166371 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1453661 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 82859 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 30173854 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 91943847 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14707897 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9318030 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20602156 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4980521 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 134933 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 96636325 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2675 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 101652 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 208965 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11862984 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 731347 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6597 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151294412 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.758755 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.115735 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 133553129 85.77% 85.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1381799 0.89% 86.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1755926 1.13% 87.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2652519 1.70% 89.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2328486 1.50% 90.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1136180 0.73% 91.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2905092 1.87% 93.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 785179 0.50% 94.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9205764 5.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130709145 86.39% 86.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1380335 0.91% 87.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1756131 1.16% 88.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2339631 1.55% 90.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2142384 1.42% 91.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1132136 0.75% 92.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2619139 1.73% 93.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 785245 0.52% 94.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8430266 5.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 155704074 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031851 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.211895 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 33480524 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 97304946 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19992509 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1030333 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3895762 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2022425 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 174533 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 117498058 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 576273 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3895762 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 35565671 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37584641 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 53601603 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18869314 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6187083 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 110088875 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21357 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1014287 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4146063 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 32391 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 114923514 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 504161217 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 504070393 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78734130 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36189383 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 892416 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 798033 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12508562 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20972747 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13834973 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1961849 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2465756 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 100830951 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2058696 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 126177528 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 189533 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 24329335 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 64639752 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 514100 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 155704074 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.810368 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.523012 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151294412 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.194953 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32008731 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96268896 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18723702 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1031258 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3261825 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2020367 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 174818 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 109258714 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3261825 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33805354 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36852775 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 53319596 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17901114 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6153748 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 104067610 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21499 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1015662 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4122290 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 31949 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 107816884 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 475027641 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 474936857 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90784 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78731329 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 29085554 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 891358 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 796895 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12333147 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20062338 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13521403 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1975115 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2433562 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 96511960 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2056994 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 123962105 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 189941 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 20009013 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 50083503 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 512489 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151294412 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.819344 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.531574 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 110503842 70.97% 70.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14006844 9.00% 79.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7305691 4.69% 84.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6085046 3.91% 88.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12721239 8.17% 96.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2798387 1.80% 98.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1680857 1.08% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 475213 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126955 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106913550 70.67% 70.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13863924 9.16% 79.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7098415 4.69% 84.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5869010 3.88% 88.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12472838 8.24% 96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2771623 1.83% 98.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1718676 1.14% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 458210 0.30% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128166 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 155704074 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151294412 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 57592 0.65% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8370496 94.62% 95.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 418270 4.73% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 56852 0.64% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8372882 94.63% 95.28% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 417861 4.72% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59895243 47.47% 47.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95317 0.08% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 7 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53367566 42.30% 90.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12453578 9.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58285332 47.02% 47.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95139 0.08% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52764596 42.57% 89.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12451206 10.04% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 126177528 # Type of FU issued
-system.cpu.iq.rate 0.265182 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8846360 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.070110 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 417165828 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 127235505 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87177257 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23405 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 134647760 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12462 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 624931 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 123962105 # Type of FU issued
+system.cpu.iq.rate 0.262843 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8847599 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071373 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 408327002 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 118594240 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86288141 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23234 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12518 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10286 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132433714 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12324 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 628913 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5256081 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7285 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30200 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2036035 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4346263 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7649 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 29949 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1722835 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34106907 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1030049 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107855 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 695994 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3895762 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28674144 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 449674 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 103114750 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 233495 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20972747 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13834973 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1466916 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113563 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3765 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30200 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 409921 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 292907 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 702828 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 122963273 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52407414 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3214255 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3261825 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27934565 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 435305 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 98793776 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 231675 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20062338 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13521403 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1465659 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 113955 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3708 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 29949 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 409673 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 293589 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 703262 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121754884 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52078341 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2207221 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 225103 # number of nop insts executed
-system.cpu.iew.exec_refs 64729141 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11726228 # Number of branches executed
-system.cpu.iew.exec_stores 12321727 # Number of stores executed
-system.cpu.iew.exec_rate 0.258426 # Inst execution rate
-system.cpu.iew.wb_sent 121618308 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 87187548 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47710631 # num instructions producing a value
-system.cpu.iew.wb_consumers 88857501 # num instructions consuming a value
+system.cpu.iew.exec_nop 224822 # number of nop insts executed
+system.cpu.iew.exec_refs 64398044 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11600510 # Number of branches executed
+system.cpu.iew.exec_stores 12319703 # Number of stores executed
+system.cpu.iew.exec_rate 0.258163 # Inst execution rate
+system.cpu.iew.wb_sent 120731241 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 86298427 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47352499 # num instructions producing a value
+system.cpu.iew.wb_consumers 88423671 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.183238 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182983 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535518 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24186815 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1544596 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 612016 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 151890748 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.514176 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.495245 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 19868331 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1544505 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 611839 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 148115015 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.527265 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.512607 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 124092082 81.70% 81.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13579714 8.94% 90.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3980091 2.62% 93.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2134436 1.41% 94.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1949184 1.28% 95.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1000796 0.66% 96.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1579621 1.04% 97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 721647 0.48% 98.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2853177 1.88% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120340532 81.25% 81.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13566988 9.16% 90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3964696 2.68% 93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2137699 1.44% 94.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1955021 1.32% 95.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 974024 0.66% 96.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1590640 1.07% 97.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 730936 0.49% 98.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2854479 1.93% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 151890748 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60749791 # Number of instructions committed
-system.cpu.commit.committedOps 78098591 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 148115015 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60747728 # Number of instructions committed
+system.cpu.commit.committedOps 78095905 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27515604 # Number of memory references committed
-system.cpu.commit.loads 15716666 # Number of loads committed
-system.cpu.commit.membars 413138 # Number of memory barriers committed
-system.cpu.commit.branches 10023383 # Number of branches committed
+system.cpu.commit.refs 27514643 # Number of memory references committed
+system.cpu.commit.loads 15716075 # Number of loads committed
+system.cpu.commit.membars 413107 # Number of memory barriers committed
+system.cpu.commit.branches 10023098 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69136784 # Number of committed integer instructions.
-system.cpu.commit.function_calls 996034 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2853177 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 69134339 # Number of committed integer instructions.
+system.cpu.commit.function_calls 995983 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2854479 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 249407638 # The number of ROB reads
-system.cpu.rob.rob_writes 208557399 # The number of ROB writes
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13329.671950 # average LoadLockedReq miss latency
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+system.cpu.dcache.avg_refs 33.725428 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 35202000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.writebacks::total 609382 # number of writebacks
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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541026 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000672 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012492 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222853 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.090296 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000672 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012492 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222853 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.090296 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40979.476225 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42280.789844 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41609.810573 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10006.448382 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10006.448382 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37908.793347 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37908.793347 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40979.476225 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38233.136793 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38455.716975 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 53002 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40979.476225 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38233.136793 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38455.716975 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1202929249396 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1202929249396 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1202929249396 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068189786972 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1068189786972 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068189786972 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1068189786972 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88035 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88028 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 5.133289 # Number of seconds simulated
-sim_ticks 5133289198000 # Number of ticks simulated
-final_tick 5133289198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.128875 # Number of seconds simulated
+sim_ticks 5128875494000 # Number of ticks simulated
+final_tick 5128875494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 170996 # Simulator instruction rate (inst/s)
-host_op_rate 338013 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2151657827 # Simulator tick rate (ticks/s)
-host_mem_usage 361992 # Number of bytes of host memory used
-host_seconds 2385.74 # Real time elapsed on the host
-sim_insts 407952579 # Number of instructions simulated
-sim_ops 806410876 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2466560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2496 # Number of bytes read from this memory
+host_inst_rate 179743 # Simulator instruction rate (inst/s)
+host_op_rate 355302 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2259848354 # Simulator tick rate (ticks/s)
+host_mem_usage 404644 # Number of bytes of host memory used
+host_seconds 2269.57 # Real time elapsed on the host
+sim_insts 407937807 # Number of instructions simulated
+sim_ops 806381430 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2484160 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1078720 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10839424 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14387648 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1078720 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1078720 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9551232 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9551232 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38540 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 39 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 1082048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10897856 # Number of bytes read from this memory
+system.physmem.bytes_read::total 14467456 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1082048 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1082048 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9613376 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9613376 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38815 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16855 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 169366 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 224807 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149238 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149238 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 480503 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 486 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 16907 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 170279 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 226054 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 150209 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 150209 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 484348 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 574 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 210142 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2111594 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2802813 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 210142 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 210142 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1860646 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1860646 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1860646 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 480503 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 210972 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2124804 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2820785 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 210972 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 210972 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1874363 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1874363 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1874363 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 484348 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 574 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 210142 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2111594 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4663458 # Total bandwidth to/from this memory (bytes/s)
-system.iocache.replacements 47577 # number of replacements
-system.iocache.tagsinuse 0.116486 # Cycle average of tags in use
+system.physmem.bw_total::cpu.inst 210972 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2124804 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4695148 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 226054 # Total number of read requests seen
+system.physmem.writeReqs 150209 # Total number of write requests seen
+system.physmem.cpureqs 390083 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 14467456 # Total number of bytes read from memory
+system.physmem.bytesWritten 9613376 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 14467456 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 9613376 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 85 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 3870 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 13592 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 14674 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 12790 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 14969 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 13832 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 14849 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 12900 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 14193 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 13720 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 14770 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 14195 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 14927 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 13783 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 14903 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 12863 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 15009 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 8622 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 10212 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 8230 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 10302 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 8995 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 10163 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 8186 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 9599 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 8962 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 10025 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 9289 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 10268 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 8898 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 10138 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 8164 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 10156 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5128875413000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 226054 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 150209 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 3870 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 177383 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 21698 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 8154 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2813 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2817 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2133 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1311 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1375 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1300 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1219 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1091 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 470 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 266 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 194 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 116 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 5738 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 6395 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 6494 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 6512 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 6522 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 6525 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 6530 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 6530 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 6530 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 6531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 6531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 6531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 6531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 6531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 6531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 6531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6530 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 6530 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6530 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6530 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 793 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 136 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 3329517724 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7605839724 # Sum of mem lat for all requests
+system.physmem.totBusLat 903876000 # Total cycles spent in databus access
+system.physmem.totBankLat 3372446000 # Total cycles spent in bank access
+system.physmem.avgQLat 14734.40 # Average queueing delay per request
+system.physmem.avgBankLat 14924.37 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 33658.77 # Average memory access latency
+system.physmem.avgRdBW 2.82 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2.82 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 14.06 # Average write queue length over time
+system.physmem.readRowHits 199198 # Number of row buffer hits during reads
+system.physmem.writeRowHits 88428 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 58.87 # Row buffer hit rate for writes
+system.physmem.avgGap 13631091.58 # Average gap between requests
+system.iocache.replacements 47576 # number of replacements
+system.iocache.tagsinuse 0.091613 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47593 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47592 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.116486 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.007280 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.007280 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 912 # number of ReadReq misses
+system.iocache.warmup_cycle 4991895066000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.091613 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.005726 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.005726 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47632 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses
-system.iocache.overall_misses::total 47632 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138482932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 138482932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9931610160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 9931610160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10070093092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10070093092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10070093092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10070093092 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
+system.iocache.overall_misses::total 47631 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143697932 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 143697932 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8983849160 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 8983849160 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 9127547092 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 9127547092 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 9127547092 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 9127547092 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151845.320175 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 151845.320175 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212577.272260 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 212577.272260 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 211414.450202 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 211414.450202 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 71516 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157736.478595 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 157736.478595 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192291.291952 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 192291.291952 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 191630.389704 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 191630.389704 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 56345 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 8861 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 7566 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8.070872 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 7.447132 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91058932 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 91058932 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7502170160 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7502170160 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7593229092 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7593229092 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96295990 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 96295990 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6552154765 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 6552154765 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 6648450755 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 6648450755 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99845.320175 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 99845.320175 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160577.272260 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 160577.272260 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105703.611416 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 105703.611416 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140243.038634 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 140243.038634 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 448600431 # number of cpu cycles simulated
+system.cpu.numCycles 448887765 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 86509944 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 86509944 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1185802 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 81830934 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 79445705 # Number of BTB hits
+system.cpu.BPredUnit.lookups 86493598 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 86493598 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1184200 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 81985656 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 79438611 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 27983612 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 427293864 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86509944 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79445705 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 164022517 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5056605 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 118707 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 62987614 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 36438 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 56602 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9268852 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 518204 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 3676 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 259039385 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.256241 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.417856 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 28044653 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 427268280 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86493598 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79438611 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 164008180 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5056188 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 124973 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 62751260 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 36198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 62335 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9257771 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 519239 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3803 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 258861392 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.258152 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.417945 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 95447322 36.85% 36.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1594478 0.62% 37.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71953209 27.78% 65.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 971457 0.38% 65.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1620147 0.63% 66.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2451072 0.95% 67.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1123457 0.43% 67.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1423255 0.55% 68.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 82454988 31.83% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 95283812 36.81% 36.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1591927 0.61% 37.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71954404 27.80% 65.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 971846 0.38% 65.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1615863 0.62% 66.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2450126 0.95% 67.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1121647 0.43% 67.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1424659 0.55% 68.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 82447108 31.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 259039385 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192844 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.952504 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31701157 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 60460157 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 159747770 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3296725 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3833576 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 840199157 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 1214 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3833576 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34469655 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37373675 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 10858241 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159947646 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12556592 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 836331491 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21404 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5918645 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4820353 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 7887 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 998118157 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1816257155 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1816256355 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 800 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964383755 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 33734395 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 466799 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 473697 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 28937943 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17313250 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10261817 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1158356 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 954062 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 829878064 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1256439 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 824382236 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 167222 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23705426 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 36106397 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 203573 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 259039385 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.182459 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.385421 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 258861392 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192684 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.951838 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31762033 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 60235448 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 159762632 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3267698 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3833581 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 840104917 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1244 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3833581 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34530134 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37412206 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 10702091 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 159938633 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 12444747 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 836257763 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19698 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5896480 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4716940 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 7816 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 997992319 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1816026440 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1816025416 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1024 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964353103 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 33639209 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 466352 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 473282 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 28808345 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17312855 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10260076 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1206444 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 946818 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 829834961 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1255797 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 824342965 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 165215 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 23689940 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 36113140 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 203193 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 258861392 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.184496 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.385380 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 72064876 27.82% 27.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15723846 6.07% 33.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10360482 4.00% 37.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7566572 2.92% 40.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75946167 29.32% 70.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3904049 1.51% 71.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72535410 28.00% 99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 783527 0.30% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 154456 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 72001826 27.81% 27.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15596239 6.02% 33.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10365970 4.00% 37.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7555139 2.92% 40.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75952295 29.34% 70.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3901347 1.51% 71.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72539766 28.02% 99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 795622 0.31% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 153188 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 259039385 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 258861392 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 355366 33.47% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 553588 52.14% 85.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 152800 14.39% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 354431 33.41% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 554175 52.24% 85.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 152275 14.35% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 305432 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 796570576 96.63% 96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 306719 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 796534260 96.63% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 18033245 2.19% 98.85% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9472983 1.15% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 18029662 2.19% 98.85% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9472324 1.15% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 824382236 # Type of FU issued
-system.cpu.iq.rate 1.837676 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1061754 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001288 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1909166354 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 854849744 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 819707401 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 374 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 65 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 825138441 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1650685 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 824342965 # Type of FU issued
+system.cpu.iq.rate 1.836412 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1060881 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1908906757 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 854790380 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 819662460 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 438 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 58 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 825097030 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1650086 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3332850 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 26850 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11358 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1844760 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3338406 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 26898 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11294 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1845192 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1932315 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 11695 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1932288 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 11793 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3833576 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26046353 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2116686 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 831134503 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 342849 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17313250 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10261817 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 725973 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1616805 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 16237 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11358 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 710415 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 622755 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1333170 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 822369106 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17608498 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2013129 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3833581 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 26182715 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2118325 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 831090758 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 325842 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17312855 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10260082 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 724912 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1616921 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11294 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 708686 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 624381 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1333067 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 822327193 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 17600649 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2015771 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26834247 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83283502 # Number of branches executed
-system.cpu.iew.exec_stores 9225749 # Number of stores executed
-system.cpu.iew.exec_rate 1.833188 # Inst execution rate
-system.cpu.iew.wb_sent 821860005 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 819707466 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 640500741 # num instructions producing a value
-system.cpu.iew.wb_consumers 1046431080 # num instructions consuming a value
+system.cpu.iew.exec_refs 26823265 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83275848 # Number of branches executed
+system.cpu.iew.exec_stores 9222616 # Number of stores executed
+system.cpu.iew.exec_rate 1.831922 # Inst execution rate
+system.cpu.iew.wb_sent 821819072 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 819662518 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 640525310 # num instructions producing a value
+system.cpu.iew.wb_consumers 1046521436 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.827255 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.612081 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.825985 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.612052 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24617133 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1052864 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1189777 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 255221218 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.159655 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.852368 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 24603279 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1052602 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1189396 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 255043204 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 3.161744 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.853415 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 83203030 32.60% 32.60% # Number of insts commited each cycle
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.committedInsts_total 407952579 # Number of Instructions Simulated
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-system.cpu.cpi_total 1.099639 # CPI: Total CPI of All Threads
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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency
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-system.cpu.icache.ReadReq_mshr_misses::total 1071350 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1071350 # number of demand (read+write) MSHR misses
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-system.cpu.itb_walker_cache.ReadReq_misses::total 10592 # number of ReadReq misses
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-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10592 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 10592 # number of overall misses
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-system.cpu.itb_walker_cache.overall_miss_latency::total 116124000 # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38435 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 38435 # number of ReadReq accesses(hits+misses)
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+system.cpu.itb_walker_cache.demand_hits::total 29382 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 29382 # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total 29382 # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11163 # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total 11163 # number of ReadReq misses
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+system.cpu.itb_walker_cache.demand_misses::total 11163 # number of demand (read+write) misses
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+system.cpu.itb_walker_cache.overall_misses::total 11163 # number of overall misses
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+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 123160000 # number of demand (read+write) miss cycles
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+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 123160000 # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total 123160000 # number of overall miss cycles
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+system.cpu.itb_walker_cache.ReadReq_accesses::total 40542 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
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-system.cpu.itb_walker_cache.demand_accesses::total 38438 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38438 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 38438 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275582 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275582 # miss rate for ReadReq accesses
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-system.cpu.itb_walker_cache.demand_miss_rate::total 0.275561 # miss rate for demand accesses
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-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10963.368580 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10963.368580 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10963.368580 # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40545 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total 40545 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40545 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total 40545 # number of overall (read+write) accesses
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+system.cpu.itb_walker_cache.demand_miss_rate::total 0.275324 # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275324 # miss rate for overall accesses
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+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11032.876467 # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11032.876467 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11032.876467 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 1540 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 1540 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10592 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10592 # number of ReadReq MSHR misses
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-system.cpu.itb_walker_cache.demand_mshr_misses::total 10592 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10592 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 10592 # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94940000 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94940000 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94940000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94940000 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94940000 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275582 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275582 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275561 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275561 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8963.368580 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks 1731 # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total 1731 # number of writebacks
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+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11163 # number of ReadReq MSHR misses
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+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 100834000 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 100834000 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275344 # mshr miss rate for ReadReq accesses
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+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for demand accesses
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+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for overall accesses
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+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9032.876467 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements 107637 # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse 11.991971 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 139374 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs 107653 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs 1.294660 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5096875914000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.991971 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749498 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total 0.749498 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139374 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 139374 # number of ReadReq hits
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-system.cpu.dtb_walker_cache.demand_hits::total 139374 # number of demand (read+write) hits
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-system.cpu.dtb_walker_cache.overall_hits::total 139374 # number of overall hits
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-system.cpu.dtb_walker_cache.ReadReq_misses::total 108671 # number of ReadReq misses
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-system.cpu.dtb_walker_cache.demand_misses::total 108671 # number of demand (read+write) misses
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-system.cpu.dtb_walker_cache.overall_misses::total 108671 # number of overall misses
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-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1362724500 # number of demand (read+write) miss cycles
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-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1362724500 # number of overall miss cycles
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-system.cpu.dtb_walker_cache.demand_accesses::total 248045 # number of demand (read+write) accesses
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-system.cpu.dtb_walker_cache.overall_accesses::total 248045 # number of overall (read+write) accesses
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-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.438110 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.438110 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.438110 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.438110 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.438110 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12539.909451 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12539.909451 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12539.909451 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12539.909451 # average overall miss latency
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+system.cpu.dtb_walker_cache.total_refs 137796 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs 109417 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs 1.259366 # Average number of references to valid blocks.
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+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.859492 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total 0.859492 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137796 # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total 137796 # number of ReadReq hits
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+system.cpu.dtb_walker_cache.ReadReq_misses::total 110443 # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110443 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total 110443 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110443 # number of overall misses
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+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1382584000 # number of overall miss cycles
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+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248239 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total 248239 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248239 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total 248239 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248239 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 248239 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.444906 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.444906 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.444906 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total 0.444906 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.444906 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total 0.444906 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12518.529920 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12518.529920 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12518.529920 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12518.529920 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 32720 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 32720 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108671 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108671 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108671 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total 108671 # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50491.707979 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.673804 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.673804 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38288.169829 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38288.169829 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47107.105814 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41274.047687 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41806.458269 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47107.105814 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41274.047687 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41806.458269 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 5.205007 # Number of seconds simulated
-sim_ticks 5205006924000 # Number of ticks simulated
-final_tick 5205006924000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.205006 # Number of seconds simulated
+sim_ticks 5205006494000 # Number of ticks simulated
+final_tick 5205006494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 143770 # Simulator instruction rate (inst/s)
-host_op_rate 275863 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6917470976 # Simulator tick rate (ticks/s)
-host_mem_usage 505276 # Number of bytes of host memory used
-host_seconds 752.44 # Real time elapsed on the host
-sim_insts 108178578 # Number of instructions simulated
-sim_ops 207571464 # Number of ops (including micro ops) simulated
+host_inst_rate 176611 # Simulator instruction rate (inst/s)
+host_op_rate 338881 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8497542071 # Simulator tick rate (ticks/s)
+host_mem_usage 459536 # Number of bytes of host memory used
+host_seconds 612.53 # Real time elapsed on the host
+sim_insts 108179755 # Number of instructions simulated
+sim_ops 207574747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 173936 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 174032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 86216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 870514880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 69689841 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 49504 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 870539632 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 69693671 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 49472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 20312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 157070368 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 27207776 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1124848049 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 870514880 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 157070368 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1027585248 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 157047256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 27202450 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1124848257 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 870539632 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 157047256 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1027586888 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 48549302 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 21364054 # Number of bytes written to this memory
-system.physmem.bytes_written::total 72904476 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 48549554 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 21360352 # Number of bytes written to this memory
+system.physmem.bytes_written::total 72901026 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 818 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 21742 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 21754 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 10777 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 108814360 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 12175547 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 6188 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 108817454 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 12176562 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 6184 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2539 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 19633796 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 4005942 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 144671709 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 19630907 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 4005282 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 144672277 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 7160367 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 2936343 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 10143448 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 7160394 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 2935820 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 10142952 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 6766 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 33417 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 33436 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 16564 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 167245672 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 13389001 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 9511 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 167250441 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 13389738 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 9505 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 3902 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 30176784 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 5227231 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 216108848 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 167245672 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 30176784 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 197422456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 30172346 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 5226209 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 216108906 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 167250441 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 30172346 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 197422787 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 574659 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 9327423 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 4104520 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 14006605 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 9327472 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 4103809 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 14005943 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 581425 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 33417 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 33436 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 16567 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 167245672 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 22716424 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 9511 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 167250441 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 22717210 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 9505 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 3902 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 30176784 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 9331751 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 230115453 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 30172346 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 9330018 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 230114849 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 818 # Total number of read requests seen
+system.physmem.writeReqs 46736 # Total number of write requests seen
+system.physmem.cpureqs 47248 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 52352 # Total number of bytes read from memory
+system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 35216 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 80 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 64 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 64 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 322 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 3080 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 3056 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 2944 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 2880 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 2912 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 2640 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 2864 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 2816 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 3024 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 2800 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 2800 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 2768 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 2992 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 3152 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 2992 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 3016 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 63209426000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 306 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 512 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 46736 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 336 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 40984666 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 52278666 # Sum of mem lat for all requests
+system.physmem.totBusLat 3272000 # Total cycles spent in databus access
+system.physmem.totBankLat 8022000 # Total cycles spent in bank access
+system.physmem.avgQLat 50103.50 # Average queueing delay per request
+system.physmem.avgBankLat 9806.85 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 63910.35 # Average memory access latency
+system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.57 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.00 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.15 # Average write queue length over time
+system.physmem.readRowHits 695 # Number of row buffer hits during reads
+system.physmem.writeRowHits 45891 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 84.96 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 98.19 # Row buffer hit rate for writes
+system.physmem.avgGap 1329213.65 # Average gap between requests
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.numCycles 10410013848 # number of cpu cycles simulated
+system.cpu0.numCycles 10410012988 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 93129090 # Number of instructions committed
-system.cpu0.committedOps 179514856 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 169447650 # Number of integer alu accesses
+system.cpu0.committedInsts 93132190 # Number of instructions committed
+system.cpu0.committedOps 179521943 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 169453705 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 0 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 16553172 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 169447650 # number of integer instructions
+system.cpu0.num_conditional_control_insts 16554212 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 169453705 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 418656867 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 211655789 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 418670977 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 211662649 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 20197632 # number of memory refs
-system.cpu0.num_load_insts 13022518 # Number of load instructions
-system.cpu0.num_store_insts 7175114 # Number of store instructions
-system.cpu0.num_idle_cycles 9667682114.054142 # Number of idle cycles
-system.cpu0.num_busy_cycles 742331733.945857 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.071309 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.928691 # Percentage of idle cycles
+system.cpu0.num_mem_refs 20198672 # number of memory refs
+system.cpu0.num_load_insts 13023532 # Number of load instructions
+system.cpu0.num_store_insts 7175140 # Number of store instructions
+system.cpu0.num_idle_cycles 9667664508.054142 # Number of idle cycles
+system.cpu0.num_busy_cycles 742348479.945857 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.071311 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.928689 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.numCycles 10407072224 # number of cpu cycles simulated
+system.cpu1.numCycles 10407071288 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 15049488 # Number of instructions committed
-system.cpu1.committedOps 28056608 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 27537877 # Number of integer alu accesses
+system.cpu1.committedInsts 15047565 # Number of instructions committed
+system.cpu1.committedOps 28052804 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 27533880 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 0 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1864532 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 27537877 # number of integer instructions
+system.cpu1.num_conditional_control_insts 1864518 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 27533880 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 71380294 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 31003707 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 71369326 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 30999444 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_mem_refs 6975131 # number of memory refs
-system.cpu1.num_load_insts 4014934 # Number of load instructions
-system.cpu1.num_store_insts 2960197 # Number of store instructions
-system.cpu1.num_idle_cycles 10279839396.425842 # Number of idle cycles
-system.cpu1.num_busy_cycles 127232827.574158 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.012226 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.987774 # Percentage of idle cycles
+system.cpu1.num_mem_refs 6973948 # number of memory refs
+system.cpu1.num_load_insts 4014274 # Number of load instructions
+system.cpu1.num_store_insts 2959674 # Number of store instructions
+system.cpu1.num_idle_cycles 10279858503.692720 # Number of idle cycles
+system.cpu1.num_busy_cycles 127212784.307279 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.012224 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.987776 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 0.271545 # Number of seconds simulated
-sim_ticks 271544682500 # Number of ticks simulated
-final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.271565 # Number of seconds simulated
+sim_ticks 271565222500 # Number of ticks simulated
+final_tick 271565222500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 142205 # Simulator instruction rate (inst/s)
-host_op_rate 142205 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64159611 # Simulator tick rate (ticks/s)
-host_mem_usage 212920 # Number of bytes of host memory used
-host_seconds 4232.33 # Real time elapsed on the host
+host_inst_rate 118122 # Simulator instruction rate (inst/s)
+host_op_rate 118122 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 53298093 # Simulator tick rate (ticks/s)
+host_mem_usage 217868 # Number of bytes of host memory used
+host_seconds 5095.21 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory
system.physmem.num_writes::total 891 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 198214 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 5966694 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6164908 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 198214 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 198214 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 209999 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 209999 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 209999 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 198214 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5966694 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6374907 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 198199 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 5966243 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6164442 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 198199 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 198199 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 209983 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 209983 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 209983 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 198199 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5966243 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6374424 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 26157 # Total number of read requests seen
+system.physmem.writeReqs 891 # Total number of write requests seen
+system.physmem.cpureqs 27048 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1674048 # Total number of bytes read from memory
+system.physmem.bytesWritten 57024 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1674048 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 57024 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 1710 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1723 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1560 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1574 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1699 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1625 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1662 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1653 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1553 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1614 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1596 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1543 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1643 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1645 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1686 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1666 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 58 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 65 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 51 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 65 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 53 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 67 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 71 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 48 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 52 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 41 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 49 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 54 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 60 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 60 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 271565170500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 26157 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 891 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 22499 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 120 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 800 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1522 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 782 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 17 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 11 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 129156577 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 809724577 # Sum of mem lat for all requests
+system.physmem.totBusLat 104608000 # Total cycles spent in databus access
+system.physmem.totBankLat 575960000 # Total cycles spent in bank access
+system.physmem.avgQLat 4938.69 # Average queueing delay per request
+system.physmem.avgBankLat 22023.55 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 30962.24 # Average memory access latency
+system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.21 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.21 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.04 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 7.68 # Average write queue length over time
+system.physmem.readRowHits 17269 # Number of row buffer hits during reads
+system.physmem.writeRowHits 120 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 66.03 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 13.47 # Row buffer hit rate for writes
+system.physmem.avgGap 10040120.18 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114520418 # DTB read accesses
-system.cpu.dtb.write_hits 39661840 # DTB write hits
+system.cpu.dtb.write_hits 39661841 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 39664142 # DTB write accesses
-system.cpu.dtb.data_hits 154179627 # DTB hits
+system.cpu.dtb.write_accesses 39664143 # DTB write accesses
+system.cpu.dtb.data_hits 154179628 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 154184560 # DTB accesses
-system.cpu.itb.fetch_hits 25070818 # ITB hits
+system.cpu.dtb.data_accesses 154184561 # DTB accesses
+system.cpu.itb.fetch_hits 25070821 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 25070840 # ITB accesses
+system.cpu.itb.fetch_accesses 25070843 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 543089366 # number of cpu cycles simulated
+system.cpu.numCycles 543130446 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 86310005 # Number of BP lookups
+system.cpu.branch_predictor.lookups 86310002 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 36354317 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 52694904 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 34317639 # Number of BTB hits
+system.cpu.branch_predictor.condIncorrect 36354316 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 52694902 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 34317638 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 65.125157 # BTB Hit Percentage
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-system.cpu.execution_unit.predicted 26198577 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 58.114383 # Percentage of Incorrect Branches Predicts
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45346.008681 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45346.008681 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38081.871581 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57035.343689 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53822.308002 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42036.475892 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42036.475892 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.133202 # Number of seconds simulated
-sim_ticks 133202081500 # Number of ticks simulated
-final_tick 133202081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.133501 # Number of seconds simulated
+sim_ticks 133501490500 # Number of ticks simulated
+final_tick 133501490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 258977 # Simulator instruction rate (inst/s)
-host_op_rate 258977 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 60995759 # Simulator tick rate (ticks/s)
-host_mem_usage 213944 # Number of bytes of host memory used
-host_seconds 2183.79 # Real time elapsed on the host
+host_inst_rate 263578 # Simulator instruction rate (inst/s)
+host_op_rate 263578 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 62218941 # Simulator tick rate (ticks/s)
+host_mem_usage 217856 # Number of bytes of host memory used
+host_seconds 2145.67 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1627520 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1688832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1627136 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1688448 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 58752 # Number of bytes written to this memory
system.physmem.bytes_written::total 58752 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 25430 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 26388 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 25424 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 26382 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 918 # Number of write requests responded to by this memory
system.physmem.num_writes::total 918 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 460293 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12218428 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12678721 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 460293 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 460293 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 441074 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 441074 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 441074 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 460293 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12218428 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13119795 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 459261 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 12188149 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 12647409 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 459261 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 459261 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 440085 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 440085 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 440085 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 459261 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 12188149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13087494 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 26382 # Total number of read requests seen
+system.physmem.writeReqs 918 # Total number of write requests seen
+system.physmem.cpureqs 27300 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1688448 # Total number of bytes read from memory
+system.physmem.bytesWritten 58752 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1688448 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 58752 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 1716 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1728 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1605 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1629 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1712 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1633 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1672 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1669 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1563 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1626 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1614 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1549 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1659 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1643 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1693 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1668 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 58 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 67 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 55 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 66 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 53 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 67 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 72 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 49 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 52 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 42 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 53 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 54 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 63 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 60 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 133501465500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 26382 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 918 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 5916 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 12948 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5187 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 716 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 422 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 406 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 393 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 382 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 842096821 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1422758821 # Sum of mem lat for all requests
+system.physmem.totBusLat 105516000 # Total cycles spent in databus access
+system.physmem.totBankLat 475146000 # Total cycles spent in bank access
+system.physmem.avgQLat 31923.00 # Average queueing delay per request
+system.physmem.avgBankLat 18012.28 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 53935.28 # Average memory access latency
+system.physmem.avgRdBW 12.65 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.44 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 12.65 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.44 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.08 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.01 # Average read queue length over time
+system.physmem.avgWrQLen 10.07 # Average write queue length over time
+system.physmem.readRowHits 17947 # Number of row buffer hits during reads
+system.physmem.writeRowHits 124 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 68.04 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 13.51 # Row buffer hit rate for writes
+system.physmem.avgGap 4890163.57 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 123824653 # DTB read hits
-system.cpu.dtb.read_misses 18111 # DTB read misses
+system.cpu.dtb.read_hits 123834550 # DTB read hits
+system.cpu.dtb.read_misses 17810 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 123842764 # DTB read accesses
-system.cpu.dtb.write_hits 40832181 # DTB write hits
-system.cpu.dtb.write_misses 27219 # DTB write misses
+system.cpu.dtb.read_accesses 123852360 # DTB read accesses
+system.cpu.dtb.write_hits 40838763 # DTB write hits
+system.cpu.dtb.write_misses 27151 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 40859400 # DTB write accesses
-system.cpu.dtb.data_hits 164656834 # DTB hits
-system.cpu.dtb.data_misses 45330 # DTB misses
+system.cpu.dtb.write_accesses 40865914 # DTB write accesses
+system.cpu.dtb.data_hits 164673313 # DTB hits
+system.cpu.dtb.data_misses 44961 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 164702164 # DTB accesses
-system.cpu.itb.fetch_hits 66456282 # ITB hits
-system.cpu.itb.fetch_misses 39 # ITB misses
+system.cpu.dtb.data_accesses 164718274 # DTB accesses
+system.cpu.itb.fetch_hits 66485884 # ITB hits
+system.cpu.itb.fetch_misses 38 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 66456321 # ITB accesses
+system.cpu.itb.fetch_accesses 66485922 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 266404164 # number of cpu cycles simulated
+system.cpu.numCycles 267002982 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 78470433 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 72835844 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 3045377 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 42694984 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 41620121 # Number of BTB hits
+system.cpu.BPredUnit.lookups 78490289 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 72847815 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 3050228 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 42945683 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 41640479 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1626012 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 68396808 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 710651464 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 78470433 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 43246133 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 119157795 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 12900055 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 68967877 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1025 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 66456282 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 943162 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 266369518 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.667916 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.466169 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1629196 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 68428860 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 710798920 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 78490289 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 43269675 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 119192583 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 12919622 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 69466328 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1179 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 66485884 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 944600 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 266949725 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.662670 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.464655 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 147211723 55.27% 55.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 10361930 3.89% 59.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 11839981 4.44% 63.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10604273 3.98% 67.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 6985851 2.62% 70.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2662888 1.00% 71.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3489906 1.31% 72.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3104255 1.17% 73.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 70108711 26.32% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 147757142 55.35% 55.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 10366639 3.88% 59.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 11845375 4.44% 63.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10612007 3.98% 67.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 6988496 2.62% 70.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2666505 1.00% 71.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3491309 1.31% 72.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3106869 1.16% 73.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 70115383 26.27% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 266369518 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.294554 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.667569 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 85436450 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 53444664 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 104479529 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 13163939 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 9844936 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3905187 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 1152 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 701891597 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 4998 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 9844936 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 93666462 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 10915780 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 985 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 104171147 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 47770208 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 690014062 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 37142293 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4412591 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 527194579 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 906673497 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 906670681 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2816 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 266949725 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.293968 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.662139 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 85457793 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 53956348 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 104522021 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 13153880 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 9859683 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3909548 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 1132 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 702023291 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 5115 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 9859683 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 93690944 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 11427696 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1077 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 104202524 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 47767801 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 690131281 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 37133482 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4417196 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 527277904 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 906836279 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 906833414 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2865 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 63339690 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 89 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 106261883 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 128976533 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 42417035 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 14777590 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 9627827 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 626339991 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 608311695 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 332491 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 60098493 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33347060 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 266369518 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.283714 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.821089 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 63423015 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 100 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 106239657 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 128990605 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 42428237 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 14728779 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 9525532 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 626440684 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 608386027 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 332535 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 60195764 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 33399973 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 74 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 266949725 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.279028 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.823675 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 51762898 19.43% 19.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 53589578 20.12% 39.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 53994858 20.27% 59.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 37661936 14.14% 73.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 31638901 11.88% 85.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 23703533 8.90% 94.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 10074612 3.78% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3319964 1.25% 99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 623238 0.23% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 52346454 19.61% 19.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 53679990 20.11% 39.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 53956371 20.21% 59.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 37644200 14.10% 74.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31434632 11.78% 85.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 23774675 8.91% 94.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 10171294 3.81% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3315844 1.24% 99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 626265 0.23% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 266369518 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 266949725 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2702741 76.36% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 515259 14.56% 90.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 321532 9.08% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2688356 76.19% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 516717 14.64% 90.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 323442 9.17% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 440952184 72.49% 72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7450 0.00% 72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 441007420 72.49% 72.49% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7412 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 126098325 20.73% 93.22% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 41253693 6.78% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 126109044 20.73% 93.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 41262108 6.78% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 608311695 # Type of FU issued
-system.cpu.iq.rate 2.283417 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3539537 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.005819 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1486861080 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 686441117 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 598748300 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3856 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2343 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1699 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 611849296 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1936 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 12174453 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 608386027 # Type of FU issued
+system.cpu.iq.rate 2.278574 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3528520 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.005800 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1487578943 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 686639010 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 598810761 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3891 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2383 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1718 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 611912593 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1954 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 12176241 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 14462491 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 33569 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 4944 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2965714 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 14476563 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 33526 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 4894 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2976916 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 6773 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 155 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 6758 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 144 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 9844936 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 227072 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 16439 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 670244681 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1692417 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 128976533 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 42417035 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6445 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 4188 # Number of times the LSQ has become full, causing a stall
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-system.cpu.iew.predictedTakenIncorrect 1342659 # Number of branches that were predicted taken incorrectly
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system.cpu.iew.exec_swp 0 # number of swp insts executed
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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-system.cpu.commit.committed_per_cycle::0 77999684 30.41% 30.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 72616675 28.31% 58.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 26248532 10.23% 68.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 7743107 3.02% 71.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 10914414 4.25% 76.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 20847110 8.13% 84.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6257952 2.44% 86.79% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::8 30793229 12.00% 100.00% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::5 20794996 8.09% 84.37% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 601856963 # Number of instructions committed
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 30793229 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 30881574 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 895745115 # The number of ROB reads
-system.cpu.rob.rob_writes 1350023504 # The number of ROB writes
-system.cpu.timesIdled 796 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 34646 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 896329047 # The number of ROB reads
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+system.cpu.idleCycles 53257 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
-system.cpu.cpi 0.471051 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.471051 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.122911 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.122911 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 848545483 # number of integer regfile reads
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-system.cpu.fp_regfile_writes 50 # number of floating regfile writes
+system.cpu.cpi 0.472110 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.472110 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 2.118150 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
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-system.cpu.icache.total_refs 66454892 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 67880.379980 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 67910.634321 # Average number of references to valid blocks.
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-system.cpu.icache.occ_percent::total 0.404129 # Average percentage of cache occupancy
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-system.cpu.icache.overall_hits::total 66454892 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 1390 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 1390 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 1390 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 48196500 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 48196500 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 48196500 # number of overall miss cycles
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+system.cpu.icache.occ_percent::total 0.403605 # Average percentage of cache occupancy
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+system.cpu.icache.overall_hits::total 66484511 # number of overall hits
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+system.cpu.icache.ReadReq_misses::total 1373 # number of ReadReq misses
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+system.cpu.icache.overall_misses::total 1373 # number of overall misses
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+system.cpu.icache.ReadReq_miss_latency::total 50434500 # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::total 50434500 # number of overall miss cycles
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34673.741007 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34673.741007 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34673.741007 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34673.741007 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34673.741007 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34673.741007 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36733.066278 # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36733.066278 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36733.066278 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36733.066278 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36733.066278 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 411 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 411 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 411 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 411 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 411 # number of overall MSHR hits
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+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36994000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36228.294178 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36228.294178 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36228.294178 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 36228.294178 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36228.294178 # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37787.538304 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37787.538304 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 460690 # number of replacements
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-system.cpu.dcache.warmup_cycle 135777000 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.LoadLockedReq_hits::total 43 # number of LoadLockedReq hits
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.163008 # Number of seconds simulated
-sim_ticks 163008222000 # Number of ticks simulated
-final_tick 163008222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.163308 # Number of seconds simulated
+sim_ticks 163308075000 # Number of ticks simulated
+final_tick 163308075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 178133 # Simulator instruction rate (inst/s)
-host_op_rate 188229 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 50937760 # Simulator tick rate (ticks/s)
-host_mem_usage 228580 # Number of bytes of host memory used
-host_seconds 3200.15 # Real time elapsed on the host
+host_inst_rate 134720 # Simulator instruction rate (inst/s)
+host_op_rate 142356 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38594530 # Simulator tick rate (ticks/s)
+host_mem_usage 233164 # Number of bytes of host memory used
+host_seconds 4231.38 # Real time elapsed on the host
sim_insts 570052710 # Number of instructions simulated
sim_ops 602360916 # Number of ops (including micro ops) simulated
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-system.physmem.num_writes::writebacks 3193 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 3193 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 294856 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 294856 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::total 1253630 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1253630 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu.inst 297058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 10847326 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 12398848 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 28438 # Total number of read requests seen
+system.physmem.writeReqs 3201 # Total number of write requests seen
+system.physmem.cpureqs 31639 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1819968 # Total number of bytes read from memory
+system.physmem.bytesWritten 204864 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1819968 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 204864 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 110 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 1839 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1814 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1804 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1805 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1784 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1796 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1898 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1731 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1752 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1846 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1712 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1720 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1677 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 264 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 255 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 220 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 240 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 223 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 185 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 230 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 204 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 229 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 177 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 166 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 173 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 163308062000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 28438 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 3201 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 10296 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 6854 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 8194 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 743 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1313 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 615 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 66 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 94 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 83 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 126 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 139 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 47 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 35 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 1146806136 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1807266136 # Sum of mem lat for all requests
+system.physmem.totBusLat 113312000 # Total cycles spent in databus access
+system.physmem.totBankLat 547148000 # Total cycles spent in bank access
+system.physmem.avgQLat 40483.13 # Average queueing delay per request
+system.physmem.avgBankLat 19314.74 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 63797.87 # Average memory access latency
+system.physmem.avgRdBW 11.14 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 1.25 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 11.14 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.25 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.08 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.01 # Average read queue length over time
+system.physmem.avgWrQLen 8.45 # Average write queue length over time
+system.physmem.readRowHits 18527 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1851 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 65.40 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes
+system.physmem.avgGap 5161606.31 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 326016445 # number of cpu cycles simulated
+system.cpu.numCycles 326616151 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 85521826 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 80321411 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2409005 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 47176245 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 46862526 # Number of BTB hits
+system.cpu.BPredUnit.lookups 85529383 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 80327419 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 2411594 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 47239817 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 46868068 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1438689 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 908 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 68838729 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 669384047 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 85521826 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 48301215 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 130014225 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 13401210 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 116068554 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 67395150 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 787497 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 325897750 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.188570 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.203934 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1438897 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 976 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 68850265 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 669456795 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 85529383 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 48306965 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 130031029 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 13412588 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 115987741 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 596 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 67404301 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 787271 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 325854018 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.189155 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.204154 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 195883756 60.11% 60.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 20926266 6.42% 66.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 4973061 1.53% 68.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 14397687 4.42% 72.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8914249 2.74% 75.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 9438407 2.90% 78.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4391608 1.35% 79.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 5795696 1.78% 81.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 61177020 18.77% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 195823205 60.10% 60.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 20926796 6.42% 66.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 4974411 1.53% 68.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 14401150 4.42% 72.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8914958 2.74% 75.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 9439818 2.90% 78.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4393851 1.35% 79.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 5794662 1.78% 81.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 61185167 18.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 325897750 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.262324 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.053222 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 92928440 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 93325217 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 108744555 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 19925503 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 10974035 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4721193 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 1619 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 705690133 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 6091 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 10974035 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 107218931 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 12903831 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 39750 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 114312743 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 80448460 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 696999769 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 59211261 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 18958262 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 603 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 723690859 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3240622549 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3240622421 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 325854018 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.261865 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.049674 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 92909986 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 93274931 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 108737205 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 19949035 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10982861 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4721514 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 1634 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 705778363 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 5683 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 10982861 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 107200735 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 12803432 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 41316 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 114329497 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 80496177 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 697076108 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 75 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 59278982 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 18940548 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 607 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 723768936 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3240980671 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3240980543 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 627419173 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 96271686 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2053 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2007 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 169155311 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 172874803 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 80609628 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 21505343 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 28086060 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 681842513 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3260 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 646713779 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1407547 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 79314162 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 197591004 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 331 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 325897750 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.984407 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.742434 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 96349763 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2017 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1967 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 169248841 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 172890049 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 80617622 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 21466789 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 27949042 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 681898631 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 3279 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 646738917 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1408601 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 79369513 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 197745870 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 350 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 325854018 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.984750 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.743125 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 67307339 20.65% 20.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 84522408 25.94% 46.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 74985673 23.01% 69.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 40267786 12.36% 81.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 28844208 8.85% 90.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15117912 4.64% 95.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 5722755 1.76% 97.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 6923607 2.12% 99.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2206062 0.68% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 67303060 20.65% 20.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 84497277 25.93% 46.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 74959252 23.00% 69.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 40290304 12.36% 81.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 28820123 8.84% 90.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15118844 4.64% 95.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 5732215 1.76% 97.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 6879322 2.11% 99.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2253621 0.69% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 325897750 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 325854018 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 205384 5.40% 5.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 205105 5.40% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2833511 74.46% 79.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 766298 20.14% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2822579 74.31% 79.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 770924 20.29% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 403852803 62.45% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 6571 0.00% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 403867506 62.45% 62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 166065084 25.68% 88.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 76789318 11.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 166069409 25.68% 88.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 76795433 11.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 646713779 # Type of FU issued
-system.cpu.iq.rate 1.983685 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3805193 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.005884 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1624538012 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 761171255 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 638446114 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 646738917 # Type of FU issued
+system.cpu.iq.rate 1.980119 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3798608 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.005873 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1624539025 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 761282766 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 638466372 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 650518952 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 650537505 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 30376789 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 30381283 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 23921985 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 123764 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11533 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 10388390 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 23937231 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 124667 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11589 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 10396384 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 12747 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 17143 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 12749 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 16530 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 10974035 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 319837 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 41126 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 681848951 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 703596 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 172874803 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 80609628 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1912 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 10996 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 4141 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11533 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1387510 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1519308 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2906818 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 642524921 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 163926120 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4188858 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 10982861 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 283658 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 42314 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 681905072 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 702708 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 172890049 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 80617622 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1929 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 10939 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 4841 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11589 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1389637 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1521620 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 2911257 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 642548978 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 163933240 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4189939 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3178 # number of nop insts executed
-system.cpu.iew.exec_refs 239918745 # number of memory reference insts executed
-system.cpu.iew.exec_branches 74716876 # Number of branches executed
-system.cpu.iew.exec_stores 75992625 # Number of stores executed
-system.cpu.iew.exec_rate 1.970836 # Inst execution rate
-system.cpu.iew.wb_sent 639915699 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 638446130 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 420790055 # num instructions producing a value
-system.cpu.iew.wb_consumers 656091526 # num instructions consuming a value
+system.cpu.iew.exec_nop 3162 # number of nop insts executed
+system.cpu.iew.exec_refs 239931847 # number of memory reference insts executed
+system.cpu.iew.exec_branches 74717690 # Number of branches executed
+system.cpu.iew.exec_stores 75998607 # Number of stores executed
+system.cpu.iew.exec_rate 1.967291 # Inst execution rate
+system.cpu.iew.wb_sent 639936452 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 638466388 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 420738662 # num instructions producing a value
+system.cpu.iew.wb_consumers 656063471 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.958325 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.641359 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.954791 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.641308 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 79497382 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 79553511 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2929 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2407463 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 314923716 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.912720 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.240103 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 2410069 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 314871158 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.913040 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.240132 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 91160511 28.95% 28.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 103755163 32.95% 61.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 42928794 13.63% 75.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 8971951 2.85% 78.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25547635 8.11% 86.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 13484569 4.28% 90.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 7640580 2.43% 93.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1100606 0.35% 93.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 20333907 6.46% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 91119458 28.94% 28.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 103740730 32.95% 61.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 42921464 13.63% 75.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 8973909 2.85% 78.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 25553482 8.12% 86.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13492783 4.29% 90.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7636973 2.43% 93.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1102971 0.35% 93.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 20329388 6.46% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 314923716 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 314871158 # Number of insts commited each cycle
system.cpu.commit.committedInsts 570052761 # Number of instructions committed
system.cpu.commit.committedOps 602360967 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 533523531 # Number of committed integer instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 20333907 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 20329388 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 976447546 # The number of ROB reads
-system.cpu.rob.rob_writes 1374722217 # The number of ROB writes
-system.cpu.timesIdled 15150 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 118695 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 976455636 # The number of ROB reads
+system.cpu.rob.rob_writes 1374843243 # The number of ROB writes
+system.cpu.timesIdled 13781 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 762133 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 570052710 # Number of Instructions Simulated
system.cpu.committedOps 602360916 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 570052710 # Number of Instructions Simulated
-system.cpu.cpi 0.571906 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.571906 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.748540 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.748540 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3209706655 # number of integer regfile reads
-system.cpu.int_regfile_writes 664060053 # number of integer regfile writes
+system.cpu.cpi 0.572958 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.572958 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.745329 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.745329 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3209817028 # number of integer regfile reads
+system.cpu.int_regfile_writes 664078534 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 904689637 # number of misc regfile reads
+system.cpu.misc_regfile_reads 904771120 # number of misc regfile reads
system.cpu.misc_regfile_writes 3106 # number of misc regfile writes
-system.cpu.icache.replacements 58 # number of replacements
-system.cpu.icache.tagsinuse 694.540428 # Cycle average of tags in use
-system.cpu.icache.total_refs 67394031 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 818 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 82388.790954 # Average number of references to valid blocks.
+system.cpu.icache.replacements 68 # number of replacements
+system.cpu.icache.tagsinuse 692.511005 # Cycle average of tags in use
+system.cpu.icache.total_refs 67403190 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 831 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 81110.938628 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 694.540428 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.339131 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.339131 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 67394031 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 67394031 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 67394031 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 67394031 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 67394031 # number of overall hits
-system.cpu.icache.overall_hits::total 67394031 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1119 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1119 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1119 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1119 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1119 # number of overall misses
-system.cpu.icache.overall_misses::total 1119 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 37389000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 37389000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 37389000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 37389000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 37389000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 37389000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 67395150 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 67395150 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 67395150 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 67395150 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 67395150 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 67395150 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33412.868633 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 33412.868633 # average ReadReq miss latency
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 3193 # number of writebacks
-system.cpu.l2cache.writebacks::total 3193 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 3201 # number of writebacks
+system.cpu.l2cache.writebacks::total 3201 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5494 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 6245 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22188 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 22188 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 27682 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 28433 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 27682 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 28433 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24797500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172259500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197057000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899948500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899948500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24797500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1072208000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 1097005500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24797500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1072208000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 1097005500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027839 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031513 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089785 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089785 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062280 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.063852 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062280 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.063852 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33019.307590 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.113578 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31554.363491 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40560.145123 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40560.145123 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38733.039520 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38582.122885 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38733.039520 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38582.122885 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5500 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 6258 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22180 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 22180 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 27680 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 28438 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 27680 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 28438 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25719146 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 701873552 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 727592698 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1275833198 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1275833198 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25719146 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1977706750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 2003425896 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25719146 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1977706750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 2003425896 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027844 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031549 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089750 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089750 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062250 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.063835 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062250 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.063835 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33930.271768 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 127613.373091 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 116266.011186 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57521.785302 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57521.785302 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33930.271768 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71448.943280 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70448.902736 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33930.271768 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71448.943280 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70448.902736 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.386987 # Number of seconds simulated
-sim_ticks 386986985000 # Number of ticks simulated
-final_tick 386986985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.387215 # Number of seconds simulated
+sim_ticks 387214915500 # Number of ticks simulated
+final_tick 387214915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 190632 # Simulator instruction rate (inst/s)
-host_op_rate 191233 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52649747 # Simulator tick rate (ticks/s)
-host_mem_usage 217240 # Number of bytes of host memory used
-host_seconds 7350.22 # Real time elapsed on the host
+host_inst_rate 118034 # Simulator instruction rate (inst/s)
+host_op_rate 118406 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32618299 # Simulator tick rate (ticks/s)
+host_mem_usage 226848 # Number of bytes of host memory used
+host_seconds 11871.09 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1679104 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1757888 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 78784 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 78784 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 163264 # Number of bytes written to this memory
-system.physmem.bytes_written::total 163264 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1231 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26236 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27467 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 2551 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 2551 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 203583 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4338916 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4542499 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 203583 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 203583 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 421885 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 421885 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 421885 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 203583 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4338916 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4964384 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 78656 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1678976 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1757632 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 78656 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 78656 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 163392 # Number of bytes written to this memory
+system.physmem.bytes_written::total 163392 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1229 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26234 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27463 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 2553 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2553 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 203133 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 4336031 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4539164 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 203133 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 203133 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 421967 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 421967 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 421967 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 203133 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4336031 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4961131 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27464 # Total number of read requests seen
+system.physmem.writeReqs 2553 # Total number of write requests seen
+system.physmem.cpureqs 30017 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1757632 # Total number of bytes read from memory
+system.physmem.bytesWritten 163392 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1757632 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 163392 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 4 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 1703 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1746 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1716 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1734 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1804 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1768 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1668 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1679 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1758 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1623 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 172 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 165 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 155 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 387214887500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 27464 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 2553 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 6398 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 12553 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 6348 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 625 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 392 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 391 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 380 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 371 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 916617704 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1530569704 # Sum of mem lat for all requests
+system.physmem.totBusLat 109840000 # Total cycles spent in databus access
+system.physmem.totBankLat 504112000 # Total cycles spent in bank access
+system.physmem.avgQLat 33380.11 # Average queueing delay per request
+system.physmem.avgBankLat 18358.05 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 55738.15 # Average memory access latency
+system.physmem.avgRdBW 4.54 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 4.54 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 12.78 # Average write queue length over time
+system.physmem.readRowHits 18350 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1423 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 66.82 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 55.74 # Row buffer hit rate for writes
+system.physmem.avgGap 12899853.00 # Average gap between requests
system.cpu.workload.num_syscalls 49 # Number of system calls
-system.cpu.numCycles 773973971 # number of cpu cycles simulated
+system.cpu.numCycles 774429832 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 98196903 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 88415122 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 3785922 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 66048945 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 65663541 # Number of BTB hits
+system.cpu.BPredUnit.lookups 98185573 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 88408048 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 3782090 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 66047653 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 65662573 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1365 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 165893347 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1648920679 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 98196903 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 65664906 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 330423745 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 21687705 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 259909474 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2700 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 162828772 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 752135 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 773928223 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.136454 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.151019 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1362 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 165872466 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1648691883 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 98185573 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 65663935 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 330391084 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 21655373 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 260441698 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2775 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 162813824 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 754521 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 774378524 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.134915 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.150373 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 443504478 57.31% 57.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 74374556 9.61% 66.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 37974673 4.91% 71.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 9085275 1.17% 73.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 28162152 3.64% 76.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18827829 2.43% 79.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 11514662 1.49% 80.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3870211 0.50% 81.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 146614387 18.94% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 443987440 57.33% 57.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 74371964 9.60% 66.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 37979457 4.90% 71.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 9083058 1.17% 73.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 28156651 3.64% 76.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18823006 2.43% 79.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 11516280 1.49% 80.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3872547 0.50% 81.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 146588121 18.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 773928223 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.126874 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.130460 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 216918337 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 211126972 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 285339114 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 42844971 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 17698829 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 1642655288 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 17698829 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 240878845 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 33665029 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 51866735 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 303087743 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 126731042 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1631322359 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 30917915 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 73728979 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 3098650 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1360964482 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2755920727 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 2722080159 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 33840568 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 774378524 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.126784 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.128911 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 216878479 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 211680769 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 285325834 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 42823062 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 17670380 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 1642440106 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 17670380 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 240852826 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 34201656 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 51873963 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 303043152 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 126736547 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1631096404 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 30920192 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 73688032 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 3125584 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1360785655 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2755532793 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 2721694232 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 33838561 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 116194043 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2680701 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2696386 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 272557720 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 438727279 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 180254007 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 255223658 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 82981799 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1517066880 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2635302 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1460886365 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 45400 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 113758577 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 136602100 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 391631 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 773928223 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.887625 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.429425 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 116015216 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2681563 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2696177 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 272664149 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 438656145 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 180228164 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 255185830 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 83164069 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1516867754 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2636658 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1460784709 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 45870 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 113563441 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 136393501 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 392987 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 774378524 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.886396 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.429689 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 144009666 18.61% 18.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 185251464 23.94% 42.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 210317974 27.18% 69.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 131221648 16.96% 86.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 70752732 9.14% 95.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 20294392 2.62% 98.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 7875333 1.02% 99.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 4040989 0.52% 99.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 164025 0.02% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 144522601 18.66% 18.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 185174960 23.91% 42.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 210422651 27.17% 69.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 131027562 16.92% 86.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 70858421 9.15% 95.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 20344015 2.63% 98.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 7836220 1.01% 99.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 4026070 0.52% 99.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 166024 0.02% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 773928223 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 774378524 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 90190 5.49% 5.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 99214 6.04% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1093274 66.56% 78.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 359776 21.90% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 112088 6.69% 6.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 98938 5.90% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1079860 64.44% 77.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 384872 22.97% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 867180921 59.36% 59.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 867100758 59.36% 59.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2647347 0.18% 59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2647457 0.18% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 419785067 28.73% 88.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 171273030 11.72% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 419766221 28.74% 88.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 171270273 11.72% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1460886365 # Type of FU issued
-system.cpu.iq.rate 1.887514 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1642454 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001124 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 3679668823 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1624597420 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1444476565 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 17719984 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 9099813 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 8555773 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1453469070 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 9059749 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 215381487 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1460784709 # Type of FU issued
+system.cpu.iq.rate 1.886271 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1675758 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001147 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 3679920663 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1624205262 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1444366362 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 17748907 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 9099237 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 8557399 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1453373806 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 9086661 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 215387676 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 36214436 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 54352 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 244694 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 13405865 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 36143302 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 55137 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 245231 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 13380022 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3598 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3602 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 17698829 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 443700 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 14828 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1613898358 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 4123447 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 438727279 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 180254007 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2549639 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 8198 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1497 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 244694 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 2356359 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1563564 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3919923 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1455334067 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 417065579 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 5552298 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 17670380 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1032740 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 13152 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1613687741 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 4121479 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 438656145 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 180228164 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2550792 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 8203 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 245231 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 2357183 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1559022 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3916205 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1455236393 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 417044165 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 5548316 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 94196176 # number of nop insts executed
-system.cpu.iew.exec_refs 587643036 # number of memory reference insts executed
-system.cpu.iew.exec_branches 89109340 # Number of branches executed
-system.cpu.iew.exec_stores 170577457 # Number of stores executed
-system.cpu.iew.exec_rate 1.880340 # Inst execution rate
-system.cpu.iew.wb_sent 1453944636 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1453032338 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1154452527 # num instructions producing a value
-system.cpu.iew.wb_consumers 1205669839 # num instructions consuming a value
+system.cpu.iew.exec_nop 94183329 # number of nop insts executed
+system.cpu.iew.exec_refs 587622922 # number of memory reference insts executed
+system.cpu.iew.exec_branches 89108958 # Number of branches executed
+system.cpu.iew.exec_stores 170578757 # Number of stores executed
+system.cpu.iew.exec_rate 1.879107 # Inst execution rate
+system.cpu.iew.wb_sent 1453841644 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1452923761 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1154329978 # num instructions producing a value
+system.cpu.iew.wb_consumers 1205560357 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.877366 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.957520 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.876121 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.957505 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 124266701 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 124055997 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 3785922 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 756230005 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.969670 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.506799 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 3782090 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 756708755 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.968423 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.506505 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 237695032 31.43% 31.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 276589849 36.57% 68.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 43049426 5.69% 73.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 54802104 7.25% 80.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 19618852 2.59% 83.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 13377170 1.77% 85.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 30585382 4.04% 89.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10542801 1.39% 90.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 69969389 9.25% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 238213555 31.48% 31.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 276540536 36.55% 68.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 43021375 5.69% 73.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 54822808 7.24% 80.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 19645378 2.60% 83.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13385764 1.77% 85.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 30553973 4.04% 89.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10565526 1.40% 90.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 69959840 9.25% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 756230005 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 756708755 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1485108088 # Number of instructions committed
system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions.
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 69969389 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 69959840 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2299985729 # The number of ROB reads
-system.cpu.rob.rob_writes 3245302839 # The number of ROB writes
-system.cpu.timesIdled 3314 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 45748 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2300263324 # The number of ROB reads
+system.cpu.rob.rob_writes 3244852707 # The number of ROB writes
+system.cpu.timesIdled 1017 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 51308 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1401188945 # Number of Instructions Simulated
system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated
-system.cpu.cpi 0.552369 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.552369 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.810383 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.810383 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1980648344 # number of integer regfile reads
-system.cpu.int_regfile_writes 1276312589 # number of integer regfile writes
-system.cpu.fp_regfile_reads 16966196 # number of floating regfile reads
-system.cpu.fp_regfile_writes 10497856 # number of floating regfile writes
-system.cpu.misc_regfile_reads 593314657 # number of misc regfile reads
+system.cpu.cpi 0.552695 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.552695 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.809317 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.809317 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1980527314 # number of integer regfile reads
+system.cpu.int_regfile_writes 1276211568 # number of integer regfile writes
+system.cpu.fp_regfile_reads 16969770 # number of floating regfile reads
+system.cpu.fp_regfile_writes 10498210 # number of floating regfile writes
+system.cpu.misc_regfile_reads 593297660 # number of misc regfile reads
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
-system.cpu.icache.replacements 209 # number of replacements
-system.cpu.icache.tagsinuse 1046.532429 # Cycle average of tags in use
-system.cpu.icache.total_refs 162826872 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1358 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 119901.967599 # Average number of references to valid blocks.
+system.cpu.icache.replacements 217 # number of replacements
+system.cpu.icache.tagsinuse 1045.896866 # Cycle average of tags in use
+system.cpu.icache.total_refs 162811965 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1366 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 119188.846999 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1046.532429 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.511002 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.511002 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 162826872 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 162826872 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 162826872 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 162826872 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 162826872 # number of overall hits
-system.cpu.icache.overall_hits::total 162826872 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1900 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1900 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1900 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1900 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1900 # number of overall misses
-system.cpu.icache.overall_misses::total 1900 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 60525500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 60525500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 60525500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 60525500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 60525500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 60525500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 162828772 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 162828772 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 162828772 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 162828772 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 162828772 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 162828772 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31855.526316 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 31855.526316 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 31855.526316 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 31855.526316 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 31855.526316 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 31855.526316 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1045.896866 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.510692 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.510692 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 162811965 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 162811965 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 162811965 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 162811965 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1859 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1859 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1859 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1859 # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::total 1859 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 53339000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 53339000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 53339000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 53339000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 53339000 # number of overall miss cycles
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.905813 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056740 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.059228 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31701.868400 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31254.952724 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31351.930196 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35657.910434 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35657.910434 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31701.868400 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34912.448544 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34768.558634 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31701.868400 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34912.448544 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34768.558634 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 2553 # number of writebacks
+system.cpu.l2cache.writebacks::total 2553 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1230 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4433 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 5663 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21801 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 21801 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1230 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 26234 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 27464 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1230 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 26234 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 27464 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34143480 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430451654 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 464595134 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1217504185 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1217504185 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34143480 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1647955839 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 1682099319 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34143480 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1647955839 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 1682099319 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022140 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028091 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083174 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083174 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056742 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.059227 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056742 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.059227 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 27758.926829 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 97101.658922 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 82040.461593 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55846.254071 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55846.254071 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 27758.926829 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62817.558855 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61247.426413 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 27758.926829 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62817.558855 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61247.426413 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.609798 # Number of seconds simulated
-sim_ticks 609797568500 # Number of ticks simulated
-final_tick 609797568500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.609434 # Number of seconds simulated
+sim_ticks 609433847500 # Number of ticks simulated
+final_tick 609433847500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 67150 # Simulator instruction rate (inst/s)
-host_op_rate 123728 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 46530668 # Simulator tick rate (ticks/s)
-host_mem_usage 230840 # Number of bytes of host memory used
-host_seconds 13105.28 # Real time elapsed on the host
+host_inst_rate 61609 # Simulator instruction rate (inst/s)
+host_op_rate 113518 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42665232 # Simulator tick rate (ticks/s)
+host_mem_usage 229588 # Number of bytes of host memory used
+host_seconds 14284.09 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493925 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 58112 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1694784 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1752896 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 58112 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 58112 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 58176 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1694272 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1752448 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 58176 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 58176 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 162816 # Number of bytes written to this memory
system.physmem.bytes_written::total 162816 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 908 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26481 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27389 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 909 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26473 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27382 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2544 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2544 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 95297 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2779257 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2874554 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 95297 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 95297 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 267000 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 267000 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 267000 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 95297 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2779257 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3141554 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 95459 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2780075 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2875534 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 95459 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 95459 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 267159 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 267159 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 267159 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 95459 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2780075 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3142694 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27384 # Total number of read requests seen
+system.physmem.writeReqs 2544 # Total number of write requests seen
+system.physmem.cpureqs 29928 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1752448 # Total number of bytes read from memory
+system.physmem.bytesWritten 162816 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1752448 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 162816 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 13 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 1753 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1689 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1673 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1754 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1781 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1776 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1809 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1711 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1665 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1670 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1694 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 165 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 162 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 163 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 162 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 166 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 153 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 155 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 609433834000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 27384 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 2544 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 26904 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 95 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 56299249 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 811057249 # Sum of mem lat for all requests
+system.physmem.totBusLat 109484000 # Total cycles spent in databus access
+system.physmem.totBankLat 645274000 # Total cycles spent in bank access
+system.physmem.avgQLat 2056.89 # Average queueing delay per request
+system.physmem.avgBankLat 23575.10 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 29631.99 # Average memory access latency
+system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 8.89 # Average write queue length over time
+system.physmem.readRowHits 17700 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1376 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 64.67 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 54.09 # Row buffer hit rate for writes
+system.physmem.avgGap 20363333.13 # Average gap between requests
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 1219595138 # number of cpu cycles simulated
+system.cpu.numCycles 1218867696 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 153419281 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 153419281 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 26709105 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 75190754 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 74807048 # Number of BTB hits
+system.cpu.BPredUnit.lookups 154233173 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 154233173 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 26682976 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 75825299 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 75424108 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 180231048 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1488409356 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 153419281 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 74807048 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 400557825 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 92407802 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 573234633 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 185924931 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 9228337 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1219569114 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.084484 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.278873 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 180166559 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1483545531 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 154233173 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 75424108 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 400496189 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 91879143 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 573121383 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 424 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 185204471 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 8524885 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1218826768 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.080610 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.274340 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 826230375 67.75% 67.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 23815932 1.95% 69.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 15671088 1.28% 70.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 17469051 1.43% 72.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 26718016 2.19% 74.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18180169 1.49% 76.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 27807273 2.28% 78.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 39426907 3.23% 81.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 224250303 18.39% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 825549489 67.73% 67.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 24308401 1.99% 69.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 15365270 1.26% 70.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 17994568 1.48% 72.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 26708645 2.19% 74.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18181975 1.49% 76.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 28608277 2.35% 78.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 39394925 3.23% 81.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 222715218 18.27% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1219569114 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.125795 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.220413 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 289356881 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 496684656 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 275171365 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 92810894 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 65545318 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2357736314 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 65545318 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 337721602 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 122595128 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1576 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 305744833 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 387960657 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2261287899 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 242284686 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 120945759 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2627574208 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5773835618 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5773831438 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4180 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1218826768 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.126538 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.217151 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 289191573 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 496681660 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 275162301 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 92749072 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 65042162 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2356227760 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 65042162 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 337598744 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 122716382 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1927 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 305616336 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 387851217 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2259951612 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 313 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 242131587 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 121014894 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2627036833 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5767802630 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5767798158 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4472 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 740678951 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 84 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 84 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 730447231 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 543232760 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 220439884 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 349480208 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 144920713 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2014741693 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 481 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1784164311 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 260366 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 392823529 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 821144040 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1219569114 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.462946 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.418593 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 740141576 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 82 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 730432949 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 541717387 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 220348120 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 348120905 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 144711749 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2012299347 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1784417764 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 261262 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 390397150 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 813518141 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 472 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1218826768 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.464045 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.419425 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 363999611 29.85% 29.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 365670586 29.98% 59.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 234855592 19.26% 79.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 140866108 11.55% 90.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 60913141 4.99% 95.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 40023537 3.28% 98.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 10789680 0.88% 99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1930984 0.16% 99.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 519875 0.04% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 363571086 29.83% 29.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 365294377 29.97% 59.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 234631055 19.25% 79.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 141184624 11.58% 90.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 60758407 4.98% 95.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 40069639 3.29% 98.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 10832423 0.89% 99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1950212 0.16% 99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 534945 0.04% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1219569114 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1218826768 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 467350 16.09% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2184649 75.23% 91.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 251796 8.67% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 467444 16.32% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2152766 75.14% 91.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 244877 8.55% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 46816435 2.62% 2.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1065676196 59.73% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 478957046 26.84% 89.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 192714634 10.80% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 46817146 2.62% 2.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1065882672 59.73% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 479009051 26.84% 89.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 192708895 10.80% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1784164311 # Type of FU issued
-system.cpu.iq.rate 1.462915 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2903795 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001628 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4791061390 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2407739950 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1725073479 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 507 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1436 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1740251451 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 220 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 209520869 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1784417764 # Type of FU issued
+system.cpu.iq.rate 1.463996 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2865087 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001606 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4790788107 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2402871988 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1725236233 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 538 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1508 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1740465474 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 209679766 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 124190639 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 36910 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 180735 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 32253827 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 122675266 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 38585 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 181440 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 32162063 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2057 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 2083 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 65545318 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 120938 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 15130 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2014742174 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 63913352 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 543232760 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 220439884 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 7621 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 7 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 180735 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 2120344 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 24738064 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 26858408 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1766248435 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 474148133 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 17915876 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 65042162 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 152720 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 14367 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2012299869 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 63596984 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 541717387 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 220348120 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 6821 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 181440 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 2121622 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 24710303 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 26831925 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1766440348 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 474226114 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 17977416 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 665987460 # number of memory reference insts executed
-system.cpu.iew.exec_branches 110190116 # Number of branches executed
-system.cpu.iew.exec_stores 191839327 # Number of stores executed
-system.cpu.iew.exec_rate 1.448225 # Inst execution rate
-system.cpu.iew.wb_sent 1726426595 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1725073583 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1267591282 # num instructions producing a value
-system.cpu.iew.wb_consumers 1828482722 # num instructions consuming a value
+system.cpu.iew.exec_refs 666063645 # number of memory reference insts executed
+system.cpu.iew.exec_branches 110217721 # Number of branches executed
+system.cpu.iew.exec_stores 191837531 # Number of stores executed
+system.cpu.iew.exec_rate 1.449247 # Inst execution rate
+system.cpu.iew.wb_sent 1726559885 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1725236341 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1267696731 # num instructions producing a value
+system.cpu.iew.wb_consumers 1828647298 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.414464 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.693248 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.415442 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.693243 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 393250539 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 390808265 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 26709142 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1154023796 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.405078 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.832959 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 26683034 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1153784606 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.405370 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.832544 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 421087806 36.49% 36.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 412894237 35.78% 72.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 87424698 7.58% 79.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 122293813 10.60% 90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 24525346 2.13% 92.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 22502511 1.95% 94.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 19027826 1.65% 96.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 12052514 1.04% 97.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 32215045 2.79% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 420543726 36.45% 36.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 413309390 35.82% 72.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 87337007 7.57% 79.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 122231111 10.59% 90.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 24478385 2.12% 92.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 22989251 1.99% 94.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 18567232 1.61% 96.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 12074031 1.05% 97.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 32254473 2.80% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1154023796 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1153784606 # Number of insts commited each cycle
system.cpu.commit.committedInsts 880025277 # Number of instructions committed
system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 32215045 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 32254473 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3136553215 # The number of ROB reads
-system.cpu.rob.rob_writes 4095072141 # The number of ROB writes
-system.cpu.timesIdled 539 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 26024 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3133832323 # The number of ROB reads
+system.cpu.rob.rob_writes 4089684452 # The number of ROB writes
+system.cpu.timesIdled 614 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 40928 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 880025277 # Number of Instructions Simulated
system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated
-system.cpu.cpi 1.385864 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.385864 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.721572 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.721572 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3541346034 # number of integer regfile reads
-system.cpu.int_regfile_writes 1975100349 # number of integer regfile writes
-system.cpu.fp_regfile_reads 104 # number of floating regfile reads
-system.cpu.misc_regfile_reads 910400266 # number of misc regfile reads
+system.cpu.cpi 1.385037 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.385037 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.722002 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.722002 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3541814029 # number of integer regfile reads
+system.cpu.int_regfile_writes 1975313076 # number of integer regfile writes
+system.cpu.fp_regfile_reads 108 # number of floating regfile reads
+system.cpu.misc_regfile_reads 910517303 # number of misc regfile reads
system.cpu.icache.replacements 21 # number of replacements
-system.cpu.icache.tagsinuse 820.177123 # Cycle average of tags in use
-system.cpu.icache.total_refs 185923597 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 817.668717 # Cycle average of tags in use
+system.cpu.icache.total_refs 185203176 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 202310.769314 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 201526.850925 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 820.177123 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.400477 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.400477 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 185923597 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 185923597 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 185923597 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 185923597 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 185923597 # number of overall hits
-system.cpu.icache.overall_hits::total 185923597 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1334 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1334 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1334 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1334 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1334 # number of overall misses
-system.cpu.icache.overall_misses::total 1334 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 44859000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 44859000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 44859000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 44859000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 44859000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 44859000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 185924931 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 185924931 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 185924931 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 185924931 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 185924931 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 185924931 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 817.668717 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.399252 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.399252 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 185203176 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 185203176 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 185203176 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 185203176 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 185203176 # number of overall hits
+system.cpu.icache.overall_hits::total 185203176 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses
+system.cpu.icache.overall_misses::total 1295 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 39388000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 39388000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 39388000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 39388000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 39388000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 39388000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 185204471 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 185204471 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 185204471 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 185204471 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 185204471 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 185204471 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33627.436282 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 33627.436282 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 33627.436282 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 33627.436282 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 33627.436282 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 33627.436282 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30415.444015 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 30415.444015 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 30415.444015 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 30415.444015 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 30415.444015 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 30415.444015 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
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-sim_ticks 25432499000 # Number of ticks simulated
-final_tick 25432499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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+final_tick 25283397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 191631 # Simulator instruction rate (inst/s)
-host_op_rate 193007 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53793580 # Simulator tick rate (ticks/s)
-host_mem_usage 361656 # Number of bytes of host memory used
-host_seconds 472.78 # Real time elapsed on the host
+host_inst_rate 115178 # Simulator instruction rate (inst/s)
+host_op_rate 116005 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32142506 # Simulator tick rate (ticks/s)
+host_mem_usage 365228 # Number of bytes of host memory used
+host_seconds 786.60 # Real time elapsed on the host
sim_insts 90599358 # Number of instructions simulated
sim_ops 91249911 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 45760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992960 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 993280 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 45760 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 45760 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 715 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1786690 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 37256268 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 39042958 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1786690 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1786690 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1786690 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 37256268 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 39042958 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1809883 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 37475976 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 39285859 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1809883 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1809883 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1809883 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 37475976 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 39285859 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15520 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 993280 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 993280 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 1013 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 998 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 967 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 878 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 938 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1013 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 931 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 934 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1022 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 977 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 25283243500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 15520 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 9030 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 6257 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 196 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 43058501 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 270142501 # Sum of mem lat for all requests
+system.physmem.totBusLat 62080000 # Total cycles spent in databus access
+system.physmem.totBankLat 165004000 # Total cycles spent in bank access
+system.physmem.avgQLat 2774.39 # Average queueing delay per request
+system.physmem.avgBankLat 10631.70 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 17406.09 # Average memory access latency
+system.physmem.avgRdBW 39.29 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 39.29 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.25 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.01 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 15094 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 1629074.97 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 50864999 # number of cpu cycles simulated
+system.cpu.numCycles 50566796 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 26815832 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 22064400 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 887268 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11482840 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 11353380 # Number of BTB hits
+system.cpu.BPredUnit.lookups 26827710 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 22074051 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 888543 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 11563656 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 11363946 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 72941 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 493 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 14339573 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 128641990 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26815832 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11426321 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24202315 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4802086 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 8372764 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 71231 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 482 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 14348377 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 128701471 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 26827710 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11435177 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 24213451 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4809546 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 8060195 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 14019260 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 376949 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 50826068 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.549806 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.252225 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 14028280 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 377661 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 50539595 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.565225 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.255897 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 26661639 52.46% 52.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3429294 6.75% 59.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2034587 4.00% 63.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1568872 3.09% 66.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1675049 3.30% 69.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2962794 5.83% 75.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1484032 2.92% 78.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1105241 2.17% 80.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9904560 19.49% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 26364164 52.17% 52.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3431492 6.79% 58.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2034951 4.03% 62.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1571856 3.11% 66.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1677128 3.32% 69.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2962722 5.86% 75.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1482816 2.93% 78.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1106293 2.19% 80.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9908173 19.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 50826068 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.527196 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.529087 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16897392 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 6458273 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22716084 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 851770 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3902549 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4473858 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8976 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126855886 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42929 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3902549 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18614164 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1601921 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 162955 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21830794 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4713685 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123685119 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 281691 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3991082 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 144136379 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 538783715 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 538776344 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 7371 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 50539595 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.530540 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.545177 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16886092 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 6166490 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 22746907 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 831459 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3908647 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4474881 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 9055 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 126903101 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 43084 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3908647 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 18602269 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1370571 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 152009 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 21842488 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4663611 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 123722180 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 282360 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3941818 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 144182082 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 538941570 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 538934983 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 6587 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36706897 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 6470 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 6468 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 10859255 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29577544 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5541374 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2075747 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1267218 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118433426 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 10344 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105554764 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 73541 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26995758 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 66330940 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 214 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 50826068 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.076784 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.959181 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 36752600 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 6474 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 6472 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 10800172 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29574364 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5545202 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2016944 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1216593 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 118465493 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 10340 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 105556460 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 69311 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 27028341 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 66448905 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 210 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 50539595 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.088589 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.960694 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 13833219 27.22% 27.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10749724 21.15% 48.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7931783 15.61% 63.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6457025 12.70% 76.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4857915 9.56% 86.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3493885 6.87% 93.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2371067 4.67% 97.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 608688 1.20% 98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 522762 1.03% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 13663948 27.04% 27.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10566811 20.91% 47.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7991493 15.81% 63.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6436117 12.73% 76.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4858269 9.61% 86.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3518110 6.96% 93.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2381435 4.71% 97.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 601220 1.19% 98.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 522192 1.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 50826068 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 50539595 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 142420 18.36% 18.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 354766 45.74% 64.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 278332 35.89% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 142805 18.40% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 27 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 357317 46.04% 64.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 276029 35.56% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74645911 70.72% 70.72% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10962 0.01% 70.73% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 74650431 70.72% 70.72% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 10952 0.01% 70.73% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 239 0.00% 70.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 213 0.00% 70.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 298 0.00% 70.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 258 0.00% 70.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.73% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25762945 24.41% 95.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5134404 4.86% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 25757662 24.40% 95.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5136941 4.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105554764 # Type of FU issued
-system.cpu.iq.rate 2.075194 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 775545 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007347 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 262783539 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 145440732 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102807034 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1143 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1553 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 495 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 106329739 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 570 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 435536 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 105556460 # Type of FU issued
+system.cpu.iq.rate 2.087466 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 776178 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.007353 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 262497002 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 145505542 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 102811583 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1002 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1425 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 429 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 106332135 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 503 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 448933 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 7001666 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7849 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 3639 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 794618 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6998486 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7563 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 3836 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 798446 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 13641 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 13664 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3902549 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 96175 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 18780 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 118456487 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 345131 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29577544 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5541374 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 6439 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 4987 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 4015 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 3639 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 474441 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 478533 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 952974 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104393226 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25307547 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1161538 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3908647 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 40058 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 10147 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 118488563 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 346139 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 29574364 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 5545202 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 6435 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 4999 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 113 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 3836 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 475714 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 478249 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 953963 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 104402584 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25308083 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1153876 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12717 # number of nop insts executed
-system.cpu.iew.exec_refs 30377969 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21353332 # Number of branches executed
-system.cpu.iew.exec_stores 5070422 # Number of stores executed
-system.cpu.iew.exec_rate 2.052359 # Inst execution rate
-system.cpu.iew.wb_sent 103118433 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102807529 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62180383 # num instructions producing a value
-system.cpu.iew.wb_consumers 104132992 # num instructions consuming a value
+system.cpu.iew.exec_nop 12730 # number of nop insts executed
+system.cpu.iew.exec_refs 30381749 # number of memory reference insts executed
+system.cpu.iew.exec_branches 21354330 # Number of branches executed
+system.cpu.iew.exec_stores 5073666 # Number of stores executed
+system.cpu.iew.exec_rate 2.064647 # Inst execution rate
+system.cpu.iew.wb_sent 103125475 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 102812012 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 62190160 # num instructions producing a value
+system.cpu.iew.wb_consumers 104171478 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.021184 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.597125 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.033192 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.596998 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 27194508 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 27226534 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 878429 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 46923520 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.944921 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.520501 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 879646 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 46630949 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.957123 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.526822 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 16620645 35.42% 35.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13501207 28.77% 64.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4487454 9.56% 73.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3864489 8.24% 81.99% # Number of insts commited each cycle
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31141.371158 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.061487 # Number of seconds simulated
-sim_ticks 61487437500 # Number of ticks simulated
-final_tick 61487437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.061268 # Number of seconds simulated
+sim_ticks 61267871000 # Number of ticks simulated
+final_tick 61267871000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86290 # Simulator instruction rate (inst/s)
-host_op_rate 151942 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 33582980 # Simulator tick rate (ticks/s)
-host_mem_usage 365956 # Number of bytes of host memory used
-host_seconds 1830.91 # Real time elapsed on the host
+host_inst_rate 120787 # Simulator instruction rate (inst/s)
+host_op_rate 212686 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 46841085 # Simulator tick rate (ticks/s)
+host_mem_usage 363680 # Number of bytes of host memory used
+host_seconds 1307.99 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192462 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1893056 # Number of bytes read from this memory
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-system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 20288 # Number of bytes written to this memory
-system.physmem.bytes_written::total 20288 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29579 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30647 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 317 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 317 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1111642 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 30787687 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::cpu.inst 1111642 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1111642 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 329954 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 329954 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 329954 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1111642 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 30787687 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 32229283 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_read::cpu.inst 1122938 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 1122938 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 336359 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 336359 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 336359 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1122938 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 30901155 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 32360452 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 30662 # Total number of read requests seen
+system.physmem.writeReqs 322 # Total number of write requests seen
+system.physmem.cpureqs 30989 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1962048 # Total number of bytes read from memory
+system.physmem.bytesWritten 20608 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1962048 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 20608 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 28 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 1936 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1969 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 2038 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 2024 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1986 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1872 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1877 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1862 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1926 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1900 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1830 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1883 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1923 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1961 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1876 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1771 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 18 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 14 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 124 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 18 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 19 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 2 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 4 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 18 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 11 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 8 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 12 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 55 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 3 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 61267857000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 30662 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 322 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 5 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 29991 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 477 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 129 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 14166089 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 582752089 # Sum of mem lat for all requests
+system.physmem.totBusLat 122532000 # Total cycles spent in databus access
+system.physmem.totBankLat 446054000 # Total cycles spent in bank access
+system.physmem.avgQLat 462.43 # Average queueing delay per request
+system.physmem.avgBankLat 14560.75 # Average bank access latency per request
+system.physmem.avgBusLat 3999.87 # Average bus latency per request
+system.physmem.avgMemAccLat 19023.05 # Average memory access latency
+system.physmem.avgRdBW 32.02 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.34 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 32.02 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.34 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.20 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.01 # Average read queue length over time
+system.physmem.avgWrQLen 4.97 # Average write queue length over time
+system.physmem.readRowHits 29782 # Number of row buffer hits during reads
+system.physmem.writeRowHits 175 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 97.22 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 54.35 # Row buffer hit rate for writes
+system.physmem.avgGap 1977403.08 # Average gap between requests
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 122974876 # number of cpu cycles simulated
+system.cpu.numCycles 122535743 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 35563581 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 35563581 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1083908 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 25421016 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 25287599 # Number of BTB hits
+system.cpu.BPredUnit.lookups 35570832 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 35570832 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1084026 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 25425275 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 25293552 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 27814300 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 193613700 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 35563581 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 25287599 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 58598336 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 7345607 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 30298263 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 223 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 27172491 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 322176 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 122946211 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.768410 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.402032 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27817646 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 193664357 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 35570832 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 25293552 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 58615511 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 7353362 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 29831602 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 154 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 27179590 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 325172 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 122507486 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.779073 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.404197 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 67085101 54.56% 54.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2067083 1.68% 56.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2985500 2.43% 58.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 3997651 3.25% 61.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7978379 6.49% 68.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 5028202 4.09% 72.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2861375 2.33% 74.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1431598 1.16% 76.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 29511322 24.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 66630267 54.39% 54.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2068884 1.69% 56.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2984971 2.44% 58.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3999258 3.26% 61.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7980935 6.51% 68.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 5030075 4.11% 72.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2863623 2.34% 74.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1430988 1.17% 75.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 29518485 24.10% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 122946211 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.289194 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.574417 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 38912587 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 22600530 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 48050125 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 7147919 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 6235050 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 336030812 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 6235050 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 43304200 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3170225 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 8978 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 50645325 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 19582433 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 332156996 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3311 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 17907327 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 182 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 334503257 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 881229115 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 881227036 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2079 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 122507486 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.290289 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.580472 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 38875412 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 22176556 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 48070998 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 7141971 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 6242549 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 336118074 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 6242549 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 43268905 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2886935 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 6989 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 50676752 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 19425356 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 332235244 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 9392 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 17753597 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 139 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 334580463 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 881428154 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 881426042 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2112 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 55290513 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 484 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 44388140 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 104937995 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 36474446 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 41500364 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5836392 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 323873529 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1758 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 307729409 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 216713 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 45479887 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 66424397 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1312 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 122946211 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.502960 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.799833 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 55367719 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 486 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 482 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 44129062 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 104954101 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 36485312 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 41562946 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5830806 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 323945312 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1773 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 307769548 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 217281 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 45552285 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 66549913 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1327 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 122507486 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.512251 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.799024 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 21631935 17.59% 17.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 17051158 13.87% 31.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 24526773 19.95% 51.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 23966381 19.49% 70.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 19143829 15.57% 86.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 9189049 7.47% 93.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 5012385 4.08% 98.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2266917 1.84% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 157784 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 21268867 17.36% 17.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 16938160 13.83% 31.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 24590210 20.07% 51.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 23966706 19.56% 70.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 19077143 15.57% 86.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 9190745 7.50% 93.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4997191 4.08% 97.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 2322305 1.90% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 156159 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 122946211 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 122507486 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 50945 1.97% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1871750 72.23% 74.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 668572 25.80% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 51278 1.98% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1865528 72.01% 73.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 673849 26.01% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 33168 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 174887442 56.83% 56.84% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 174913911 56.83% 56.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 52 0.00% 56.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 42 0.00% 56.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 98817076 32.11% 88.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 33991671 11.05% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 98825778 32.11% 88.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 33996476 11.05% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 307729409 # Type of FU issued
-system.cpu.iq.rate 2.502376 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2591267 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008421 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 741212334 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 369384855 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 304533759 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 675 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 209 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 310287186 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 322 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 52324197 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 307769548 # Type of FU issued
+system.cpu.iq.rate 2.511672 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2590655 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.008418 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 740853926 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 369529188 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 304569650 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 592 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1017 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 310326577 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 285 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 52294659 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 14158611 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 53020 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 31592 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 5034695 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 14174717 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 50650 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 31690 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 5045561 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3174 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3163 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 6235050 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 247932 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 19449 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 323875287 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 344865 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 104937995 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 36474446 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 477 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 247 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 894 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 31592 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 595265 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 583416 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1178681 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 305536893 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 98199399 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2192516 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 6242549 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 128946 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 5786 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 323947085 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 341652 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 104954101 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 36485312 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 376 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 886 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 31690 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 595739 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 583103 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1178842 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 305571382 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 98206856 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2198166 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 131640830 # number of memory reference insts executed
-system.cpu.iew.exec_branches 31219911 # Number of branches executed
-system.cpu.iew.exec_stores 33441431 # Number of stores executed
-system.cpu.iew.exec_rate 2.484547 # Inst execution rate
-system.cpu.iew.wb_sent 304949933 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 304533968 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 225863686 # num instructions producing a value
-system.cpu.iew.wb_consumers 311805704 # num instructions consuming a value
+system.cpu.iew.exec_refs 131649773 # number of memory reference insts executed
+system.cpu.iew.exec_branches 31223750 # Number of branches executed
+system.cpu.iew.exec_stores 33442917 # Number of stores executed
+system.cpu.iew.exec_rate 2.493733 # Inst execution rate
+system.cpu.iew.wb_sent 304986534 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 304569837 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 226002140 # num instructions producing a value
+system.cpu.iew.wb_consumers 312068538 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.476392 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.724373 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.485559 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.724207 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 45684582 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 45756293 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1083935 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 116711161 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.383598 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.781080 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1084042 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 116264937 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.392746 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.783730 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 38716768 33.17% 33.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 22386952 19.18% 52.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 17053265 14.61% 66.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 13105313 11.23% 78.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2048873 1.76% 79.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 3220721 2.76% 82.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1361336 1.17% 83.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 627536 0.54% 84.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 18190397 15.59% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 38380575 33.01% 33.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 22255868 19.14% 52.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 17068651 14.68% 66.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 13099730 11.27% 78.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2025175 1.74% 79.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 3235783 2.78% 82.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1359435 1.17% 83.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 653883 0.56% 84.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 18185837 15.64% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 116711161 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 116264937 # Number of insts commited each cycle
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.int_insts 278186170 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 18190397 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 18185837 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 422397808 # The number of ROB reads
-system.cpu.rob.rob_writes 653994696 # The number of ROB writes
-system.cpu.timesIdled 646 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 28665 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 422027855 # The number of ROB reads
+system.cpu.rob.rob_writes 654145762 # The number of ROB writes
+system.cpu.timesIdled 622 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 28257 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
-system.cpu.cpi 0.778378 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.778378 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.284722 # IPC: Instructions Per Cycle
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+system.cpu.l2cache.ReadExReq_miss_rate::total 0.352893 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992620 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.014251 # miss rate for demand accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992620 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.014251 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.014761 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32558.085502 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34987.352445 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 33421.210306 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 23318.318215 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 23318.318215 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32558.085502 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 23552.203745 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 23868.240819 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32558.085502 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 23552.203745 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 23868.240819 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 317 # number of writebacks
-system.cpu.l2cache.writebacks::total 317 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 586 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1654 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks 322 # number of writebacks
+system.cpu.l2cache.writebacks::total 322 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 593 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1669 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 29579 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 30647 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 29579 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 30647 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34670500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19225500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53896000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 62000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 62000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899128500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899128500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34670500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918354000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 953024500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34670500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918354000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 953024500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000294 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000829 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 29586 # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18631896 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5005 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5005 # number of UpgradeReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 584733766 # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31175128 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 584733766 # number of overall MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992620 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000837 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352979 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352979 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.014755 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993488 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32463.014981 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32808.020478 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32585.247884 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.916670 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.916670 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32463.014981 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31047.499915 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31096.828401 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352893 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352893 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992620 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014251 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.014761 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992620 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014251 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.014761 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28973.167286 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31419.723440 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29842.434991 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 19525.467182 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 19525.467182 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28973.167286 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 19763.866897 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 20087.042398 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28973.167286 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 19763.866897 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 20087.042398 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.201852 # Number of seconds simulated
-sim_ticks 201852280500 # Number of ticks simulated
-final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.201821 # Number of seconds simulated
+sim_ticks 201820850500 # Number of ticks simulated
+final_tick 201820850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 135871 # Simulator instruction rate (inst/s)
-host_op_rate 153059 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53886430 # Simulator tick rate (ticks/s)
-host_mem_usage 232836 # Number of bytes of host memory used
-host_seconds 3745.88 # Real time elapsed on the host
-sim_insts 508955133 # Number of instructions simulated
-sim_ops 573341693 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10015872 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10234688 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 218816 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 218816 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6679360 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6679360 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3419 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 156498 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 159917 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 104365 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 104365 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1084040 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 49619811 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50703851 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1084040 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1084040 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 33090337 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 33090337 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 33090337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1084040 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 49619811 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 83794188 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 158073 # Simulator instruction rate (inst/s)
+host_op_rate 178071 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 62682331 # Simulator tick rate (ticks/s)
+host_mem_usage 261124 # Number of bytes of host memory used
+host_seconds 3219.74 # Real time elapsed on the host
+sim_insts 508955148 # Number of instructions simulated
+sim_ops 573341708 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 219776 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10015744 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10235520 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 219776 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 219776 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6680640 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6680640 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3434 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 156496 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 159930 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 104385 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 104385 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1088966 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 49626904 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50715870 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1088966 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1088966 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 33101833 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 33101833 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 33101833 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1088966 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 49626904 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 83817702 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 159931 # Total number of read requests seen
+system.physmem.writeReqs 104385 # Total number of write requests seen
+system.physmem.cpureqs 264320 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 10235520 # Total number of bytes read from memory
+system.physmem.bytesWritten 6680640 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 10235520 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6680640 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 186 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 9715 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 10028 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 9563 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 9185 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 9586 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 9626 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 9845 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 10204 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 9902 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 11404 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 10776 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 10740 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 9984 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 9763 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 9956 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 9468 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 6164 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 6588 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6206 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6224 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6375 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6383 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6446 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6854 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 6435 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7038 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 6926 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6925 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 6680 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 6603 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 6451 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 6087 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 201820829500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 159931 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 104385 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 148144 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 10717 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 754 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 102 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4524 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 4539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 4539 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 1228593768 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4610173768 # Sum of mem lat for all requests
+system.physmem.totBusLat 638980000 # Total cycles spent in databus access
+system.physmem.totBankLat 2742600000 # Total cycles spent in bank access
+system.physmem.avgQLat 7690.97 # Average queueing delay per request
+system.physmem.avgBankLat 17168.61 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 28859.58 # Average memory access latency
+system.physmem.avgRdBW 50.72 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 33.10 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 50.72 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 33.10 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.52 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.02 # Average read queue length over time
+system.physmem.avgWrQLen 8.69 # Average write queue length over time
+system.physmem.readRowHits 136302 # Number of row buffer hits during reads
+system.physmem.writeRowHits 64360 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 85.32 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 61.66 # Row buffer hit rate for writes
+system.physmem.avgGap 763558.88 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 403704562 # number of cpu cycles simulated
+system.cpu.numCycles 403641702 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 183613146 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 143294212 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 7789120 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 98042390 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 90143773 # Number of BTB hits
+system.cpu.BPredUnit.lookups 183652385 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 143319168 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 7791559 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 98117243 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 90149856 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 12795154 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 116199 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 119018383 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 771038085 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 183613146 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 102938927 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 173093371 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 37034444 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 81728576 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 114776707 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2639607 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 402291353 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.154621 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.975773 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 12789076 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 115438 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 119026376 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 771196614 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 183652385 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 102938932 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 173108927 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 37044032 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 80186575 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 394 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 114778688 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2637185 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 400780006 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.162952 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.978630 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 229210831 56.98% 56.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 14330362 3.56% 60.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 23398991 5.82% 66.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22962860 5.71% 72.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 20943651 5.21% 77.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 13279878 3.30% 80.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13299573 3.31% 83.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 12124758 3.01% 86.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 52740449 13.11% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 227683870 56.81% 56.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 14342886 3.58% 60.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 23399081 5.84% 66.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22963566 5.73% 71.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 20939416 5.22% 77.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 13281175 3.31% 80.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13284797 3.31% 83.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 12117870 3.02% 86.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 52767345 13.17% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 402291353 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.454821 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.909907 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 129139991 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 76355942 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 163648868 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 4771100 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 28375452 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 26593121 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 78321 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 842377409 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 313716 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 28375452 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 137010485 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 5387793 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 57527480 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 160406240 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 13583903 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 812203916 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 883 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2847047 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 7163226 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 116 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 967528997 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3555884446 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3555882861 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 400780006 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.454989 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.910597 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 129077693 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 74884830 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 163721203 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 4713887 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 28382393 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 26602700 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 78428 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 842461319 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 313133 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 28382393 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 136940970 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4647966 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 57066662 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 160444938 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 13297077 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 812260436 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 946 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2860927 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 6878465 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 58 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 967590618 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3556107711 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3556106126 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1585 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 672200147 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 295328850 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3042535 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 3042531 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 44411709 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 172477044 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 75019988 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 27139166 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 14058077 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 762853534 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 4467400 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 672309193 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1597303 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 191893802 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 493277148 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 746286 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 402291353 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps 672200171 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 295390447 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 3042631 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 3042626 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 43966533 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 172435046 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 75040987 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 27084528 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 14183257 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 762885569 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4467405 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 672287055 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1597234 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 191943939 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 493452075 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 746288 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 400780006 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.677447 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.741326 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 143645798 35.71% 35.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 74204622 18.45% 54.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 68520864 17.03% 71.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 9421817 2.34% 98.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3434032 0.85% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1296489 0.32% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 142470034 35.55% 35.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 73884527 18.44% 53.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 68392945 17.06% 71.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 53248174 13.29% 84.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 32249720 8.05% 92.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16393621 4.09% 96.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 9384825 2.34% 98.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3453099 0.86% 99.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1303061 0.33% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 402291353 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 400780006 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 436530 4.38% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6785214 68.04% 72.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2750735 27.58% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 434732 4.35% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6807090 68.10% 72.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2754377 27.55% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 451600936 67.17% 67.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 386071 0.06% 67.23% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 451597333 67.17% 67.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 385890 0.06% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 155208445 23.09% 90.31% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 65113622 9.69% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 155180120 23.08% 90.31% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 65123593 9.69% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 672309193 # Type of FU issued
-system.cpu.iq.rate 1.665350 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9972479 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014833 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1758479254 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 960016621 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 651381097 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 672287055 # Type of FU issued
+system.cpu.iq.rate 1.665554 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9996199 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014869 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1756947282 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 960099456 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 651370563 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 682281537 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 682283119 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8428766 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 8423591 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 45704007 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 43585 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 806080 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 17416029 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 45662006 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 43583 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 806705 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 17437025 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19464 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1080 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19460 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 28375452 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1989251 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 96453 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 768887058 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1243291 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 172477044 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 75019988 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2978672 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 38122 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 5312 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 806080 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4756345 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4163931 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8920276 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 661932492 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 151574229 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10376701 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 28382393 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1656439 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 73515 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 768921673 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1234448 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 172435046 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 75040987 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2978685 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 37777 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 4191 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 806705 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4752820 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4170938 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8923758 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 661908420 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 151549628 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 10378635 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1566124 # number of nop insts executed
-system.cpu.iew.exec_refs 215230219 # number of memory reference insts executed
-system.cpu.iew.exec_branches 139385144 # Number of branches executed
-system.cpu.iew.exec_stores 63655990 # Number of stores executed
-system.cpu.iew.exec_rate 1.639646 # Inst execution rate
-system.cpu.iew.wb_sent 656632887 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 651381113 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 375930281 # num instructions producing a value
-system.cpu.iew.wb_consumers 649035735 # num instructions consuming a value
+system.cpu.iew.exec_nop 1568699 # number of nop insts executed
+system.cpu.iew.exec_refs 215209256 # number of memory reference insts executed
+system.cpu.iew.exec_branches 139387977 # Number of branches executed
+system.cpu.iew.exec_stores 63659628 # Number of stores executed
+system.cpu.iew.exec_rate 1.639842 # Inst execution rate
+system.cpu.iew.wb_sent 656622179 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 651370579 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 376034680 # num instructions producing a value
+system.cpu.iew.wb_consumers 649424114 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.613509 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.579214 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.613735 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.579028 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 194215600 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 3721114 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7713933 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 373915902 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.536938 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.196487 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 194250034 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 3721117 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 7716233 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 372397614 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.543204 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.198347 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 161102013 43.09% 43.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 102670077 27.46% 70.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 34449601 9.21% 79.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 18433917 4.93% 84.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 17480337 4.67% 89.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7750601 2.07% 91.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6975147 1.87% 93.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3144360 0.84% 94.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 21909849 5.86% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 159514435 42.83% 42.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 102731237 27.59% 70.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 34442629 9.25% 79.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 18453291 4.96% 84.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 17522832 4.71% 89.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7762690 2.08% 91.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6910466 1.86% 93.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3138622 0.84% 94.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 21921412 5.89% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 373915902 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 510299017 # Number of instructions committed
-system.cpu.commit.committedOps 574685577 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 372397614 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 510299032 # Number of instructions committed
+system.cpu.commit.committedOps 574685592 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 184376996 # Number of memory references committed
-system.cpu.commit.loads 126773037 # Number of loads committed
+system.cpu.commit.refs 184377002 # Number of memory references committed
+system.cpu.commit.loads 126773040 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
-system.cpu.commit.branches 122291783 # Number of branches committed
+system.cpu.commit.branches 122291786 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 473701621 # Number of committed integer instructions.
+system.cpu.commit.int_insts 473701633 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 21909849 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 21921412 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1120900092 # The number of ROB reads
-system.cpu.rob.rob_writes 1566319482 # The number of ROB writes
-system.cpu.timesIdled 51224 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 1413209 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 508955133 # Number of Instructions Simulated
-system.cpu.committedOps 573341693 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 508955133 # Number of Instructions Simulated
-system.cpu.cpi 0.793203 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.793203 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.260712 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.260712 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3088645957 # number of integer regfile reads
-system.cpu.int_regfile_writes 759574381 # number of integer regfile writes
+system.cpu.rob.rob_reads 1119404690 # The number of ROB reads
+system.cpu.rob.rob_writes 1566395163 # The number of ROB writes
+system.cpu.timesIdled 33245 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 2861696 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 508955148 # Number of Instructions Simulated
+system.cpu.committedOps 573341708 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 508955148 # Number of Instructions Simulated
+system.cpu.cpi 0.793079 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.793079 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.260908 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.260908 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3088491950 # number of integer regfile reads
+system.cpu.int_regfile_writes 759517885 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 999041226 # number of misc regfile reads
-system.cpu.misc_regfile_writes 4464048 # number of misc regfile writes
-system.cpu.icache.replacements 15551 # number of replacements
-system.cpu.icache.tagsinuse 1091.493459 # Cycle average of tags in use
-system.cpu.icache.total_refs 114757583 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 17412 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 6590.718068 # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads 999182003 # number of misc regfile reads
+system.cpu.misc_regfile_writes 4464054 # number of misc regfile writes
+system.cpu.icache.replacements 15774 # number of replacements
+system.cpu.icache.tagsinuse 1094.155149 # Cycle average of tags in use
+system.cpu.icache.total_refs 114759358 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 17633 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 6508.215165 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1091.493459 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.532956 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.532956 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 114757583 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 114757583 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 114757583 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 114757583 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 114757583 # number of overall hits
-system.cpu.icache.overall_hits::total 114757583 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 19124 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 19124 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 19124 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 19124 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 19124 # number of overall misses
-system.cpu.icache.overall_misses::total 19124 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 228709500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 228709500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 228709500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 228709500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 228709500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 228709500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 114776707 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 114776707 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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+system.cpu.l2cache.ReadReq_accesses::total 860190 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1101655 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1101655 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 49 # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.ReadExReq_accesses::total 348691 # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38767.870941 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 38847.361342 # average ReadReq miss latency
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1125 # average UpgradeReq miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 31601.033290 # average ReadExReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::total 34160.772558 # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 34160.772558 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 104365 # number of writebacks
-system.cpu.l2cache.writebacks::total 104365 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
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+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits
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-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53056 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_misses::total 56475 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103442 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 103442 # number of ReadExReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111443000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1678392000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1789835000 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 124000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3216081000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3216081000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111443000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4894473000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 5005916000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4894473000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 5005916000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.062972 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065673 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.102564 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.102564 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296724 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296724 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131385 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.132321 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131385 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.132321 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32595.203276 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31634.348613 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31692.518814 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31090.669167 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31090.669167 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32595.203276 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31274.987540 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31303.213542 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32595.203276 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31274.987540 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31303.213542 # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1856378132 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4004 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4004 # number of UpgradeReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4739811755 # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4739811755 # number of overall MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.062951 # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194805 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131371 # mshr miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34999.587707 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35086.327791 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27871.110646 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36425.685590 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 30287.111204 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36425.685590 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 30287.111204 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30418.955581 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.427481 # Number of seconds simulated
-sim_ticks 427481054500 # Number of ticks simulated
-final_tick 427481054500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.425005 # Number of seconds simulated
+sim_ticks 425004962000 # Number of ticks simulated
+final_tick 425004962000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86006 # Simulator instruction rate (inst/s)
-host_op_rate 159036 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44463827 # Simulator tick rate (ticks/s)
-host_mem_usage 261156 # Number of bytes of host memory used
-host_seconds 9614.13 # Real time elapsed on the host
+host_inst_rate 69307 # Simulator instruction rate (inst/s)
+host_op_rate 128157 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 35623080 # Simulator tick rate (ticks/s)
+host_mem_usage 342928 # Number of bytes of host memory used
+host_seconds 11930.61 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988699 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 222080 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 27608960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 27831040 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 222080 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 222080 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 20798528 # Number of bytes written to this memory
-system.physmem.bytes_written::total 20798528 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3470 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 431390 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 434860 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 324977 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 324977 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 519508 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 64585225 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 65104733 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 519508 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 519508 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 48653684 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 48653684 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 48653684 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 519508 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 64585225 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 113758417 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 27603520 # Number of bytes read from this memory
+system.physmem.bytes_read::total 27828864 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 20794944 # Number of bytes written to this memory
+system.physmem.bytes_written::total 20794944 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 431305 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 434826 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 324921 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 324921 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 530215 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 64948701 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 65478916 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 530215 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 530215 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 48928709 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 48928709 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 48928709 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 530215 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 64948701 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 114407624 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 434829 # Total number of read requests seen
+system.physmem.writeReqs 324921 # Total number of write requests seen
+system.physmem.cpureqs 946181 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 27828864 # Total number of bytes read from memory
+system.physmem.bytesWritten 20794944 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 27828864 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 20794944 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 530 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 186431 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28468 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 25473 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28312 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 28794 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 28169 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27724 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27247 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 26795 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 25192 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 26852 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 26027 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 26097 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27939 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 27190 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27326 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 26694 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 21362 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 19642 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 20883 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 21132 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 20800 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 20650 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 19810 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 19986 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 19177 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 20342 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 19625 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 19675 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 20834 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 20387 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 20379 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 20237 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 425004950500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 434829 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 324921 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 186431 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 423801 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 9380 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 992 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 101 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 14107 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 14125 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 14127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 2315570683 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11699376683 # Sum of mem lat for all requests
+system.physmem.totBusLat 1737188000 # Total cycles spent in databus access
+system.physmem.totBankLat 7646618000 # Total cycles spent in bank access
+system.physmem.avgQLat 5331.74 # Average queueing delay per request
+system.physmem.avgBankLat 17606.81 # Average bank access latency per request
+system.physmem.avgBusLat 3999.98 # Average bus latency per request
+system.physmem.avgMemAccLat 26938.53 # Average memory access latency
+system.physmem.avgRdBW 65.48 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 48.93 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 65.48 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 48.93 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.72 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.03 # Average read queue length over time
+system.physmem.avgWrQLen 10.61 # Average write queue length over time
+system.physmem.readRowHits 372606 # Number of row buffer hits during reads
+system.physmem.writeRowHits 225570 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 85.79 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 69.42 # Row buffer hit rate for writes
+system.physmem.avgGap 559401.05 # Average gap between requests
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 854962110 # number of cpu cycles simulated
+system.cpu.numCycles 850009925 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 221542687 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 221542687 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 14424166 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 156350035 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 152734220 # Number of BTB hits
+system.cpu.BPredUnit.lookups 221647941 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 221647941 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 14406573 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 156865582 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 152803842 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 186980274 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1231567115 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 221542687 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 152734220 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 382634785 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 91865959 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 200356865 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 29611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 292723 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 179385748 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 4126859 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 847490245 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.698073 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.416409 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 187050304 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1232910947 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 221647941 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 152803842 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 383000973 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 91957921 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 194367409 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 27532 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 281947 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 179514226 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 4153507 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 842043655 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.718190 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.421187 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 469274168 55.37% 55.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 25456463 3.00% 58.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 28089429 3.31% 61.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 29452206 3.48% 65.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 18977949 2.24% 67.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 25085896 2.96% 70.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 31632952 3.73% 74.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 30710148 3.62% 77.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 188811034 22.28% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 463448237 55.04% 55.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 25479263 3.03% 58.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 28153869 3.34% 61.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 29472837 3.50% 64.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 19000698 2.26% 67.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 25093035 2.98% 70.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 31632323 3.76% 73.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 30740236 3.65% 77.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 189023157 22.45% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 847490245 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.259126 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.440493 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 242064219 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 159033007 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 325519019 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 43678013 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 77195987 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2233248714 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 77195987 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 275570857 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 34110306 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 14758 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 334015692 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 126582645 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2180982884 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 23384 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 17625674 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 93760649 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 161 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2280809501 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5515289668 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5515055744 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 233924 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 842043655 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.260759 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.450467 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 241549987 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 153599929 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 326439638 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 43138611 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 77315490 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2235464595 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 77315490 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 274523548 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 31537330 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 13263 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 335098725 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 123555299 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2183717460 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4657 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 17805168 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 90736739 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 132 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2283770499 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5522648237 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5522400911 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 247326 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 666768650 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1407 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1265 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 312542490 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 527887651 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 210543369 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 206203596 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 60708248 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2086420498 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 33397 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1834774344 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 951947 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 551393168 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 912351431 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 32844 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 847490245 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.164950 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.897317 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 669729648 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1332 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1314 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 306041131 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 528315963 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 210729777 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 206411035 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 60542315 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2088035741 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 33633 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1834967448 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 958048 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 553034175 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 917867353 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 33080 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 842043655 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.179183 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.902262 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 226384734 26.71% 26.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 141456799 16.69% 43.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 133569524 15.76% 59.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 133051620 15.70% 74.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 103773872 12.24% 87.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 59584692 7.03% 94.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 35598450 4.20% 98.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12150443 1.43% 99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1920111 0.23% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 224002778 26.60% 26.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 138530201 16.45% 43.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 132512875 15.74% 58.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 132981805 15.79% 74.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 103723627 12.32% 86.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 60327569 7.16% 94.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 35793527 4.25% 98.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 12197617 1.45% 99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1973656 0.23% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 847490245 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 842043655 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 5020198 29.82% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9164809 54.44% 84.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2648245 15.73% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 5036793 29.93% 29.93% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 9138103 54.31% 84.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2651049 15.76% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2709053 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1209921951 65.94% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 444260889 24.21% 90.30% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 177882451 9.70% 100.00% # Type of FU issued
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+system.cpu.iq.FU_type_0::IntAlu 1209906674 65.94% 66.08% # Type of FU issued
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+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued
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+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued
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+system.cpu.iq.FU_type_0::MemWrite 177956437 9.70% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1834774344 # Type of FU issued
-system.cpu.iq.rate 2.146030 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 16833252 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.009175 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4534784459 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2638023268 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1791909670 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 39673 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 77216 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 9185 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1848880362 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 18181 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 169562147 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1834967448 # Type of FU issued
+system.cpu.iq.rate 2.158760 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 16825945 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.009170 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4529719072 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2641264974 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1791788720 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 43472 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 82738 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10238 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1849062833 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 20179 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 168239222 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 143785495 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 532532 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 265743 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 61383726 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 144213807 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 600713 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 256350 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 61570124 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 10593 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 8445 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 77195987 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3929040 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 530860 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2086453895 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 2572498 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 527887651 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 210543911 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 5247 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 306238 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 13529 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 265743 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 10035586 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4925818 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 14961404 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1804635725 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 435893328 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 30138619 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 77315490 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 4278866 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 415483 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2088069374 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 2542491 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 528315963 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 210730309 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 5324 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 253060 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 9562 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 256350 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 10027874 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4925644 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 14953518 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1804855171 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 436117290 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 30112277 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 608398138 # number of memory reference insts executed
-system.cpu.iew.exec_branches 171115964 # Number of branches executed
-system.cpu.iew.exec_stores 172504810 # Number of stores executed
-system.cpu.iew.exec_rate 2.110779 # Inst execution rate
-system.cpu.iew.wb_sent 1799306282 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1791918855 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1361399176 # num instructions producing a value
-system.cpu.iew.wb_consumers 1998222448 # num instructions consuming a value
+system.cpu.iew.exec_refs 608678492 # number of memory reference insts executed
+system.cpu.iew.exec_branches 171062939 # Number of branches executed
+system.cpu.iew.exec_stores 172561202 # Number of stores executed
+system.cpu.iew.exec_rate 2.123334 # Inst execution rate
+system.cpu.iew.wb_sent 1799249201 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1791798958 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1362830081 # num instructions producing a value
+system.cpu.iew.wb_consumers 2000862713 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.095904 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.681305 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.107974 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.681121 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 557495358 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 559102384 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 14453256 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 770294258 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.984941 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.459206 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 14433850 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 764728165 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.999389 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.465219 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 276893910 35.95% 35.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 195328257 25.36% 61.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 61767064 8.02% 69.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 90267747 11.72% 81.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 27669896 3.59% 84.63% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::6 10477535 1.36% 89.76% # Number of insts commited each cycle
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 324977 # number of writebacks
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.141181 # Number of seconds simulated
-sim_ticks 141180939500 # Number of ticks simulated
-final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.141149 # Number of seconds simulated
+sim_ticks 141148809500 # Number of ticks simulated
+final_tick 141148809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 139974 # Simulator instruction rate (inst/s)
-host_op_rate 139974 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49569488 # Simulator tick rate (ticks/s)
-host_mem_usage 218836 # Number of bytes of host memory used
-host_seconds 2848.14 # Real time elapsed on the host
+host_inst_rate 76319 # Simulator instruction rate (inst/s)
+host_op_rate 76319 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27020959 # Simulator tick rate (ticks/s)
+host_mem_usage 222760 # Number of bytes of host memory used
+host_seconds 5223.68 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1519979 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1799223 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3319202 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1519979 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1519979 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1519979 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1799223 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3319202 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1520325 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1799633 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3319957 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1520325 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1520325 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1520325 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1799633 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3319957 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7322 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 7322 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 468608 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 468608 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 397 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 443 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 395 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 487 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 141148757500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 7322 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 5336 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1506 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 124 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 28738807 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 171664807 # Sum of mem lat for all requests
+system.physmem.totBusLat 29288000 # Total cycles spent in databus access
+system.physmem.totBankLat 113638000 # Total cycles spent in bank access
+system.physmem.avgQLat 3924.99 # Average queueing delay per request
+system.physmem.avgBankLat 15520.08 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 23445.07 # Average memory access latency
+system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 6437 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 19277350.11 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94755040 # DTB read accesses
-system.cpu.dtb.write_hits 73522102 # DTB write hits
+system.cpu.dtb.write_hits 73522092 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 73522137 # DTB write accesses
-system.cpu.dtb.data_hits 168277121 # DTB hits
+system.cpu.dtb.write_accesses 73522127 # DTB write accesses
+system.cpu.dtb.data_hits 168277111 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 168277177 # DTB accesses
-system.cpu.itb.fetch_hits 49111833 # ITB hits
+system.cpu.dtb.data_accesses 168277167 # DTB accesses
+system.cpu.itb.fetch_hits 49111843 # ITB hits
system.cpu.itb.fetch_misses 88782 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 49200615 # ITB accesses
+system.cpu.itb.fetch_accesses 49200625 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.numCycles 282361880 # number of cpu cycles simulated
+system.cpu.numCycles 282297620 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 53870354 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 30921657 # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups 53870359 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 30921660 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 33426941 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups 33426943 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 15653988 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 46.830450 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 24186508 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 280818440 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct 46.830451 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 29683847 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 24186512 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 280818433 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 440154299 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 440154292 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 100457653 # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards 100457659 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168700458 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 281927927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 281928004 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 8028 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13487383 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 268874497 # Number of cycles cpu stages are processed.
-system.cpu.activity 95.223370 # Percentage of cycles cpu is active
+system.cpu.timesIdled 8014 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 13423125 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 268874495 # Number of cycles cpu stages are processed.
+system.cpu.activity 95.245045 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
-system.cpu.cpi 0.708269 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 0.708108 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 0.708269 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.411892 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 0.708108 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.412214 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 1.411892 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 78547913 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 203813967 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 72.181828 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 108875170 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 173486710 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 61.441265 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 104652466 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 177709414 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 62.936758 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 183580459 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 98781421 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 34.983979 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 92669372 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 189692508 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 67.180636 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 1.412214 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 78483642 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 203813978 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 72.198263 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 108810922 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 173486698 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 61.455246 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 104588213 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 177709407 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 62.951082 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 183516209 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 98781411 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 34.991939 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 92605054 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 189692566 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 67.195949 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1974 # number of replacements
-system.cpu.icache.tagsinuse 1829.872355 # Cycle average of tags in use
-system.cpu.icache.total_refs 49107443 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1830.000422 # Cycle average of tags in use
+system.cpu.icache.total_refs 49107453 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 12588.424250 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 12588.426814 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1829.872355 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.893492 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.893492 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 49107443 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 49107443 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 49107443 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 49107443 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 49107443 # number of overall hits
-system.cpu.icache.overall_hits::total 49107443 # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst 1830.000422 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.893555 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.893555 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 49107453 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 49107453 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 49107453 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 49107453 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 49107453 # number of overall hits
+system.cpu.icache.overall_hits::total 49107453 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses
system.cpu.icache.overall_misses::total 4389 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 215239500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 215239500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 215239500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 215239500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 215239500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 215239500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 49111832 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 49111832 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 49111832 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 49111832 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 49111832 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 49111832 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 191814500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 191814500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 191814500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 191814500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
system.cpu.l2cache.overall_misses::total 7322 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181079500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 46077000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 227156500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172190500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 172190500 # number of ReadExReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data 218267500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 399347000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54005.219207 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55918.689320 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 54382.690927 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54750.556439 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54750.556439 # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 54540.699262 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 36053500 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133849000 # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169902500 # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140250000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169902500 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41828.213540 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43754.247573 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42208.163754 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42559.300477 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42559.300477 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.080354 # Number of seconds simulated
-sim_ticks 80354154000 # Number of ticks simulated
-final_tick 80354154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.080450 # Number of seconds simulated
+sim_ticks 80450416000 # Number of ticks simulated
+final_tick 80450416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 221188 # Simulator instruction rate (inst/s)
-host_op_rate 221188 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47323038 # Simulator tick rate (ticks/s)
-host_mem_usage 219864 # Number of bytes of host memory used
-host_seconds 1697.99 # Real time elapsed on the host
+host_inst_rate 142052 # Simulator instruction rate (inst/s)
+host_op_rate 142052 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 30428395 # Simulator tick rate (ticks/s)
+host_mem_usage 223780 # Number of bytes of host memory used
+host_seconds 2643.93 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 222976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory
-system.physmem.bytes_read::total 478400 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 222976 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 222976 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3484 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7475 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2774916 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3178728 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 5953644 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2774916 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2774916 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2774916 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3178728 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 5953644 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 5939360 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7466 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 7466 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 477824 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
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+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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+system.physmem.perBankRdReqs::4 384 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 401 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 463 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 447 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 456 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 591 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 408 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 548 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 429 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 401 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 80450362000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 7466 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::2 826 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 54925938 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 190713938 # Sum of mem lat for all requests
+system.physmem.totBusLat 29864000 # Total cycles spent in databus access
+system.physmem.totBankLat 105924000 # Total cycles spent in bank access
+system.physmem.avgQLat 7356.81 # Average queueing delay per request
+system.physmem.avgBankLat 14187.52 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 25544.33 # Average memory access latency
+system.physmem.avgRdBW 5.94 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 5.94 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.04 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 6527 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 87.42 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 10775564.16 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 103401614 # DTB read hits
-system.cpu.dtb.read_misses 88552 # DTB read misses
-system.cpu.dtb.read_acv 48603 # DTB read access violations
-system.cpu.dtb.read_accesses 103490166 # DTB read accesses
-system.cpu.dtb.write_hits 79056152 # DTB write hits
-system.cpu.dtb.write_misses 1601 # DTB write misses
+system.cpu.dtb.read_hits 103443494 # DTB read hits
+system.cpu.dtb.read_misses 89204 # DTB read misses
+system.cpu.dtb.read_acv 48604 # DTB read access violations
+system.cpu.dtb.read_accesses 103532698 # DTB read accesses
+system.cpu.dtb.write_hits 79020707 # DTB write hits
+system.cpu.dtb.write_misses 1585 # DTB write misses
system.cpu.dtb.write_acv 2 # DTB write access violations
-system.cpu.dtb.write_accesses 79057753 # DTB write accesses
-system.cpu.dtb.data_hits 182457766 # DTB hits
-system.cpu.dtb.data_misses 90153 # DTB misses
-system.cpu.dtb.data_acv 48605 # DTB access violations
-system.cpu.dtb.data_accesses 182547919 # DTB accesses
-system.cpu.itb.fetch_hits 52578444 # ITB hits
+system.cpu.dtb.write_accesses 79022292 # DTB write accesses
+system.cpu.dtb.data_hits 182464201 # DTB hits
+system.cpu.dtb.data_misses 90789 # DTB misses
+system.cpu.dtb.data_acv 48606 # DTB access violations
+system.cpu.dtb.data_accesses 182554990 # DTB accesses
+system.cpu.itb.fetch_hits 52635617 # ITB hits
system.cpu.itb.fetch_misses 446 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 52578890 # ITB accesses
+system.cpu.itb.fetch_accesses 52636063 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.numCycles 160708310 # number of cpu cycles simulated
+system.cpu.numCycles 160900834 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 52055858 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 30270064 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1609565 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 28583053 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 24291253 # Number of BTB hits
+system.cpu.BPredUnit.lookups 52082511 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 30304197 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1627462 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 28687866 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 24364965 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 9363483 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 1125 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 53630506 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 462761975 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 52055858 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 33654736 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 81569260 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 7805922 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 19227823 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 8640 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 52578444 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 632985 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 160593743 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.881569 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.314206 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 9358559 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 1149 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 53712913 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 462927523 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 52082511 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33723524 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 81628321 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 7863564 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 19256748 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 186 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 8496 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 52635617 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 625198 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 160803654 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.878837 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.313069 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 79024483 49.21% 49.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4373999 2.72% 51.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 7277585 4.53% 56.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 5624285 3.50% 59.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 12451588 7.75% 67.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 8090347 5.04% 72.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 5701462 3.55% 76.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1906860 1.19% 77.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 36143134 22.51% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 79175333 49.24% 49.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4378645 2.72% 51.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 7276914 4.53% 56.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 5654242 3.52% 60.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 12481747 7.76% 67.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 8090070 5.03% 72.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5699527 3.54% 76.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1919584 1.19% 77.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 36127592 22.47% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 160593743 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.323915 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.879515 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 59159628 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 14701180 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 76777373 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3802489 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 6153073 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 9767212 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 4329 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 457201252 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 12277 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 6153073 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 62463630 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4784250 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 400809 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 77384574 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 9407407 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 451419869 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 20713 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 7782416 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 295098377 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 593658097 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 314398187 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 279259910 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 160803654 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.323693 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.877098 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 59260573 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 14714376 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 76844391 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3791608 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 6192706 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 9758398 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 4357 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 457340975 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 12460 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 6192706 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 62581380 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4767420 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 396481 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 77424943 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 9440724 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 451604153 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 23405 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 7795110 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 295281147 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 593898440 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 314599798 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 279298642 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 35566048 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 38393 # count of serializing insts renamed
+system.cpu.rename.UndoneMaps 35748818 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 38358 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 348 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 27305396 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 107006158 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 81864884 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 8914753 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6402170 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 416586090 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 336 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 407940469 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1092011 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 40751586 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 19838559 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 160593743 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.540202 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.007855 # Number of insts issued each cycle
+system.cpu.rename.skidInsts 27322373 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 107078098 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 81809760 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 8914792 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 6385731 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 416755970 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 334 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 407971342 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1213804 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 40920126 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 20099668 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 119 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 160803654 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.537078 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.007577 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 32107491 19.99% 19.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 26532573 16.52% 36.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 26024058 16.20% 52.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 24782303 15.43% 68.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 21577160 13.44% 81.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15465247 9.63% 91.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8675795 5.40% 96.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 4109702 2.56% 99.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1319414 0.82% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 32260500 20.06% 20.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 26539337 16.50% 36.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 26078054 16.22% 52.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 24787830 15.41% 68.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 21571430 13.41% 81.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15523746 9.65% 91.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8624317 5.36% 96.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 4085465 2.54% 99.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1332975 0.83% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 160593743 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 160803654 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 35836 0.30% 0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 36186 0.30% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 73145 0.62% 0.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 5467 0.05% 0.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 3221 0.03% 0.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 1851348 15.57% 16.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 1774625 14.92% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5106562 42.94% 74.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 3040891 25.57% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 74788 0.63% 0.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 4408 0.04% 0.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 3062 0.03% 1.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 1840642 15.50% 16.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 1784659 15.03% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5098486 42.94% 74.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3030945 25.53% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 158120657 38.76% 38.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2126534 0.52% 39.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 33463281 8.20% 47.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 7848056 1.92% 49.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2840409 0.70% 50.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 16567576 4.06% 54.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 1592675 0.39% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 105294166 25.81% 80.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 80053534 19.62% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 158101841 38.75% 38.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2126541 0.52% 39.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 33488456 8.21% 47.49% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 7847707 1.92% 49.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2841085 0.70% 50.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 16565313 4.06% 54.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 1591977 0.39% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 105357579 25.82% 80.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 80017262 19.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 407940469 # Type of FU issued
-system.cpu.iq.rate 2.538391 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 11891095 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.029149 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 648130283 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 270005016 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 237809508 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 341327504 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 187383841 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 162964934 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 245490516 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 174307467 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 14797790 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 407971342 # Type of FU issued
+system.cpu.iq.rate 2.535545 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 11873176 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.029103 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 648496700 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 270371889 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 237775030 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 341336618 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 187355366 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 162947679 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 245502336 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 174308601 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 14799025 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 12251671 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 123751 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 50882 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 8344155 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 12323611 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 124858 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 50857 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 8289031 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 260839 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 260769 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 122 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 6153073 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2493888 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 367103 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 441513906 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 235069 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 107006158 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 81864884 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 336 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 120 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 50882 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1249323 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 568752 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1818075 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 403380721 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 103538845 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4559748 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 6192706 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2493954 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 366810 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 441694516 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 229015 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 107078098 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 81809760 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 334 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 117 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 78 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 50857 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1275804 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 567133 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1842937 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 403387908 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 103581364 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4583434 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 24927480 # number of nop insts executed
-system.cpu.iew.exec_refs 182596628 # number of memory reference insts executed
-system.cpu.iew.exec_branches 47226669 # Number of branches executed
-system.cpu.iew.exec_stores 79057783 # Number of stores executed
-system.cpu.iew.exec_rate 2.510018 # Inst execution rate
-system.cpu.iew.wb_sent 401610425 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 400774442 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 195308199 # num instructions producing a value
-system.cpu.iew.wb_consumers 273451305 # num instructions consuming a value
+system.cpu.iew.exec_nop 24938212 # number of nop insts executed
+system.cpu.iew.exec_refs 182603691 # number of memory reference insts executed
+system.cpu.iew.exec_branches 47210628 # Number of branches executed
+system.cpu.iew.exec_stores 79022327 # Number of stores executed
+system.cpu.iew.exec_rate 2.507059 # Inst execution rate
+system.cpu.iew.wb_sent 401574040 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 400722709 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 195201608 # num instructions producing a value
+system.cpu.iew.wb_consumers 273256469 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.493800 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.714234 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.490495 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.714353 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 42890401 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 43076400 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1605306 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 154440670 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.581345 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.965853 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1623178 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 154610948 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.578502 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.964409 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 58870445 38.12% 38.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 23396206 15.15% 53.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13280012 8.60% 61.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11680215 7.56% 69.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 8466998 5.48% 74.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 5501467 3.56% 78.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 5150112 3.33% 81.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3370011 2.18% 83.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 24725204 16.01% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 58949463 38.13% 38.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 23452675 15.17% 53.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13321237 8.62% 61.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11705960 7.57% 69.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 8475693 5.48% 74.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 5493357 3.55% 78.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 5136307 3.32% 81.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3345893 2.16% 84.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 24730363 16.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 154440670 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 154610948 # Number of insts commited each cycle
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
system.cpu.commit.int_insts 316365839 # Number of committed integer instructions.
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 24725204 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 24730363 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 571267473 # The number of ROB reads
-system.cpu.rob.rob_writes 889277309 # The number of ROB writes
-system.cpu.timesIdled 3039 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 114567 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 571618591 # The number of ROB reads
+system.cpu.rob.rob_writes 889688372 # The number of ROB writes
+system.cpu.timesIdled 2869 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 97180 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated
-system.cpu.cpi 0.427900 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.427900 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.336997 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.336997 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 402957504 # number of integer regfile reads
-system.cpu.int_regfile_writes 172619998 # number of integer regfile writes
-system.cpu.fp_regfile_reads 158343155 # number of floating regfile reads
-system.cpu.fp_regfile_writes 105226626 # number of floating regfile writes
+system.cpu.cpi 0.428412 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.428412 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.334201 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.334201 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 402943078 # number of integer regfile reads
+system.cpu.int_regfile_writes 172629700 # number of integer regfile writes
+system.cpu.fp_regfile_reads 158343488 # number of floating regfile reads
+system.cpu.fp_regfile_writes 105222580 # number of floating regfile writes
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 2218 # number of replacements
-system.cpu.icache.tagsinuse 1836.523631 # Cycle average of tags in use
-system.cpu.icache.total_refs 52573018 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 4149 # Sample count of references to valid blocks.
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-system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 144.500000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3484 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 859 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 4343 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3484 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 3991 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 7475 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3484 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 3991 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 7475 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112975000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31822500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 144797500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115935000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115935000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112975000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147757500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 260732500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112975000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147757500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 260732500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868554 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.845271 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.978444 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.978444 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.952506 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.896390 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.952506 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.896390 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32426.808266 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37045.983702 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33340.432880 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37016.283525 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37016.283525 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32426.808266 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37022.676021 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34880.602007 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32426.808266 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37022.676021 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34880.602007 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3478 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 857 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4335 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3478 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3988 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7466 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3478 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3988 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7466 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 98162814 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31479970 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98128686 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 98162814 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 129608656 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 227771470 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 98162814 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 129608656 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 227771470 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869168 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.847011 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979969 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979969 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953839 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.898111 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953839 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.898111 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28223.925819 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36732.753792 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29906.063206 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31341.004791 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31341.004791 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28223.925819 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32499.662989 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30507.831503 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28223.925819 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32499.662989 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30507.831503 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.070882 # Number of seconds simulated
-sim_ticks 70882487500 # Number of ticks simulated
-final_tick 70882487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.071023 # Number of seconds simulated
+sim_ticks 71023388000 # Number of ticks simulated
+final_tick 71023388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 146290 # Simulator instruction rate (inst/s)
-host_op_rate 187023 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 37976354 # Simulator tick rate (ticks/s)
-host_mem_usage 236976 # Number of bytes of host memory used
-host_seconds 1866.49 # Real time elapsed on the host
+host_inst_rate 129198 # Simulator instruction rate (inst/s)
+host_op_rate 165172 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33606101 # Simulator tick rate (ticks/s)
+host_mem_usage 240544 # Number of bytes of host memory used
+host_seconds 2113.41 # Real time elapsed on the host
sim_insts 273048441 # Number of instructions simulated
sim_ops 349076165 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 272768 # Number of bytes read from this memory
-system.physmem.bytes_read::total 467648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 272832 # Number of bytes read from this memory
+system.physmem.bytes_read::total 467712 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 194880 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 194880 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3045 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4262 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2749339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3848172 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6597511 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2749339 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2749339 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2749339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3848172 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6597511 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 4263 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 7308 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2743885 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3841439 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6585324 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2743885 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2743885 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2743885 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3841439 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6585324 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7308 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 7308 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 467712 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 467712 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 345 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 578 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 461 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 441 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 510 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 480 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 484 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 551 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 363 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 415 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 362 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 71023232000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 7308 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 4207 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2152 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 666 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::4 75 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 41389289 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 172709289 # Sum of mem lat for all requests
+system.physmem.totBusLat 29232000 # Total cycles spent in databus access
+system.physmem.totBankLat 102088000 # Total cycles spent in bank access
+system.physmem.avgQLat 5663.56 # Average queueing delay per request
+system.physmem.avgBankLat 13969.35 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 23632.91 # Average memory access latency
+system.physmem.avgRdBW 6.59 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 6.59 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.04 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 6370 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 87.16 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 9718559.39 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 141764976 # number of cpu cycles simulated
+system.cpu.numCycles 142046777 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 43022632 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 21746290 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2100537 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 27784307 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 17845610 # Number of BTB hits
+system.cpu.BPredUnit.lookups 43162042 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 21862143 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 2121703 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 28877793 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 17918646 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 6965581 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 7462 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 40878725 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 328721134 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 43022632 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 24811191 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 73667201 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 8391169 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 20823021 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 3522 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 39401519 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 692730 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 141652682 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.982295 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.454701 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 6972885 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 7671 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 40968439 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 329355833 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 43162042 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 24891531 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 73809901 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 8464308 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 20842753 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2971 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 39491995 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 707720 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 141956225 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.979912 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.453592 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 68666188 48.48% 48.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 7372946 5.20% 53.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 5824782 4.11% 57.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6228810 4.40% 62.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4953654 3.50% 65.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4319066 3.05% 68.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3319868 2.34% 71.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4326916 3.05% 74.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 36640452 25.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 68825893 48.48% 48.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 7402388 5.21% 53.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 5830184 4.11% 57.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 6288593 4.43% 62.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4967322 3.50% 65.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4323548 3.05% 68.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3311772 2.33% 71.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4321361 3.04% 74.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 36685164 25.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 141652682 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.303479 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.318775 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 47724056 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 16047440 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 69280897 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 2389978 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 6210311 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 7496443 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 70615 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 414536105 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 220570 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 6210311 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 53491207 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1558118 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 338571 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 65828585 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14225890 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 403967880 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1665803 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 10197275 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 723 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 443295910 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2386846444 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1300310044 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1086536400 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 141956225 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.303858 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.318643 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 47854672 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 16043866 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 69433090 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 2362421 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 6262176 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 7513619 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 70716 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 415062954 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 220817 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 6262176 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 53639950 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1545689 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 333184 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 65936980 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 14238246 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 404539854 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 67 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1667551 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 10176735 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 553 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 443995291 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2389355526 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1302857658 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1086497868 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384584946 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 58710964 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 14469 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 14467 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 35655672 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 105463248 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 93220202 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 4594940 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5698907 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 391915159 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 25548 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 378021086 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1395950 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 41892562 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 109796784 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 141652682 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.668648 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.042717 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 59410345 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 14542 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 14541 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 35671511 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 105577606 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 93228051 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 4593885 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5660351 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 392311117 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 25611 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 378254160 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1403521 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 42287591 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 111052876 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1134 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 141956225 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.664583 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.042822 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 28697410 20.26% 20.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 20492119 14.47% 34.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 20907256 14.76% 49.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 18207035 12.85% 62.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 24094157 17.01% 79.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15966233 11.27% 90.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 9051361 6.39% 97.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3319497 2.34% 99.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 917614 0.65% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 28896984 20.36% 20.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 20515288 14.45% 34.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 20937445 14.75% 49.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 18231025 12.84% 62.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 24110473 16.98% 79.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15997056 11.27% 90.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 9050570 6.38% 97.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3298757 2.32% 99.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 918627 0.65% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 141652682 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 141956225 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8869 0.05% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 9062 0.05% 0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 45720 0.25% 0.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 45808 0.25% 0.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 7848 0.04% 0.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 429 0.00% 0.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 7711 0.04% 0.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 383 0.00% 0.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 193652 1.08% 1.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 4980 0.03% 1.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 240582 1.34% 2.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9467921 52.63% 55.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 8015707 44.56% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 193806 1.08% 1.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 5491 0.03% 1.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 241038 1.34% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 9458380 52.63% 55.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 8006771 44.55% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 128195849 33.91% 33.91% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2174611 0.58% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6839706 1.81% 36.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8692181 2.30% 38.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3465000 0.92% 39.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1622054 0.43% 39.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 21343322 5.65% 45.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7172329 1.90% 47.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135364 1.89% 49.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 102447083 27.10% 76.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 88758301 23.48% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 128369790 33.94% 33.94% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2174598 0.57% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 6843583 1.81% 36.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 8689764 2.30% 38.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 3465929 0.92% 39.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1622822 0.43% 39.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 21343412 5.64% 45.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7172666 1.90% 47.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136167 1.89% 49.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 102562726 27.11% 76.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 88697415 23.45% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 378021086 # Type of FU issued
-system.cpu.iq.rate 2.666534 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 17990410 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.047591 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 665853263 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 301144367 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 252283124 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 251227951 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 132702727 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 118872712 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 266490153 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 129521343 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 10844694 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 378254160 # Type of FU issued
+system.cpu.iq.rate 2.662884 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 17973147 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.047516 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 666559792 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 301879538 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 252435570 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 251281421 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 132758695 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 118859507 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 266684443 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 129542864 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 10845590 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 10812156 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 121101 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14360 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 10842267 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 10926514 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 120350 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14368 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 10850116 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 29815 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 119 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 27154 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 6210311 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 59816 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 7651 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 391949728 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1062817 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 105463248 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 93220202 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 14378 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 211 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 349 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14360 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1675475 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 499111 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2174586 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 373364048 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 101084784 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4657038 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 6262176 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 55211 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 11686 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 392346402 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1078418 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 105577606 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 93228051 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 14439 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 194 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14368 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1702737 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 499287 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 2202024 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 373561232 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 101191974 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4692928 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9021 # number of nop insts executed
-system.cpu.iew.exec_refs 188503459 # number of memory reference insts executed
-system.cpu.iew.exec_branches 38700482 # Number of branches executed
-system.cpu.iew.exec_stores 87418675 # Number of stores executed
-system.cpu.iew.exec_rate 2.633683 # Inst execution rate
-system.cpu.iew.wb_sent 371949572 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 371155836 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 184798274 # num instructions producing a value
-system.cpu.iew.wb_consumers 367725403 # num instructions consuming a value
+system.cpu.iew.exec_nop 9674 # number of nop insts executed
+system.cpu.iew.exec_refs 188550520 # number of memory reference insts executed
+system.cpu.iew.exec_branches 38725245 # Number of branches executed
+system.cpu.iew.exec_stores 87358546 # Number of stores executed
+system.cpu.iew.exec_rate 2.629847 # Inst execution rate
+system.cpu.iew.wb_sent 372099364 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 371295077 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 184920977 # num instructions producing a value
+system.cpu.iew.wb_consumers 367888043 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.618107 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.502544 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.613893 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.502656 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 42873018 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 43269770 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 24477 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2030662 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 135442372 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.577309 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.655328 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 2051746 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 135694050 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.572528 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.654395 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 38119190 28.14% 28.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 29150867 21.52% 49.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13483643 9.96% 59.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11130935 8.22% 67.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 13797972 10.19% 78.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7276796 5.37% 83.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3948237 2.92% 86.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3977327 2.94% 89.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 14557405 10.75% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 38297743 28.22% 28.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 29217550 21.53% 49.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13522381 9.97% 59.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11119570 8.19% 67.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 13774007 10.15% 78.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7289874 5.37% 83.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 3949510 2.91% 86.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3974023 2.93% 89.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 14549392 10.72% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 135442372 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 135694050 # Number of insts commited each cycle
system.cpu.commit.committedInsts 273049053 # Number of instructions committed
system.cpu.commit.committedOps 349076777 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.int_insts 279593983 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 14557405 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 14549392 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 512832239 # The number of ROB reads
-system.cpu.rob.rob_writes 790114412 # The number of ROB writes
-system.cpu.timesIdled 3064 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 112294 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 513488682 # The number of ROB reads
+system.cpu.rob.rob_writes 790959694 # The number of ROB writes
+system.cpu.timesIdled 2717 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 90552 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273048441 # Number of Instructions Simulated
system.cpu.committedOps 349076165 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 273048441 # Number of Instructions Simulated
-system.cpu.cpi 0.519194 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.519194 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.926064 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.926064 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1783379175 # number of integer regfile reads
-system.cpu.int_regfile_writes 236079321 # number of integer regfile writes
-system.cpu.fp_regfile_reads 189868959 # number of floating regfile reads
-system.cpu.fp_regfile_writes 133650660 # number of floating regfile writes
-system.cpu.misc_regfile_reads 990849298 # number of misc regfile reads
+system.cpu.cpi 0.520226 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.520226 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.922243 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.922243 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1784209945 # number of integer regfile reads
+system.cpu.int_regfile_writes 236299492 # number of integer regfile writes
+system.cpu.fp_regfile_reads 189823111 # number of floating regfile reads
+system.cpu.fp_regfile_writes 133661428 # number of floating regfile writes
+system.cpu.misc_regfile_reads 991633784 # number of misc regfile reads
system.cpu.misc_regfile_writes 34426469 # number of misc regfile writes
-system.cpu.icache.replacements 13928 # number of replacements
-system.cpu.icache.tagsinuse 1856.985526 # Cycle average of tags in use
-system.cpu.icache.total_refs 39384906 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 15824 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2488.934909 # Average number of references to valid blocks.
+system.cpu.icache.replacements 13962 # number of replacements
+system.cpu.icache.tagsinuse 1856.548325 # Cycle average of tags in use
+system.cpu.icache.total_refs 39475406 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 15856 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 2489.619450 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1856.985526 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.906731 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.906731 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 39384906 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 39384906 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 39384906 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 39384906 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 39384906 # number of overall hits
-system.cpu.icache.overall_hits::total 39384906 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 16613 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 16613 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 16613 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 16613 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 16613 # number of overall misses
-system.cpu.icache.overall_misses::total 16613 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 188398500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 188398500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 188398500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 188398500 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 188398500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 39401519 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 39401519 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 39401519 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 39401519 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 39401519 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 39401519 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000422 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000422 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000422 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000422 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000422 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000422 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11340.426172 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 11340.426172 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 11340.426172 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 11340.426172 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1856.548325 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.906518 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.906518 # Average percentage of cache occupancy
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+system.cpu.icache.ReadReq_hits::total 39475406 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 39475406 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 39475406 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 16589 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 16589 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 16589 # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::total 16589 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 174124000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 174124000 # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total 174124000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 174124000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 174124000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 39491995 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 39491995 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 39491995 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 39491995 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 39491995 # number of overall (read+write) accesses
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97703000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 146251500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 243954500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97703000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 146251500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 243954500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812188 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255900 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993957 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993957 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922910 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.357468 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922910 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.357468 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32086.371100 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34445.429741 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32853.025937 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34246.959943 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34246.959943 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::cpu.data 4263 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7308 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 85814425 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42422648 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 128237073 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72139117 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72139117 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85814425 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 114561765 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 200376190 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85814425 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 114561765 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 200376190 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809813 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255461 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992893 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992893 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921132 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.356766 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921132 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.356766 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28182.077176 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 28878.589517 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 28408.744572 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 25819.297423 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 25819.297423 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28182.077176 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 26873.508093 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 27418.745211 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28182.077176 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 26873.508093 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 27418.745211 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.644314 # Number of seconds simulated
-sim_ticks 644314104000 # Number of ticks simulated
-final_tick 644314104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.652381 # Number of seconds simulated
+sim_ticks 652381344000 # Number of ticks simulated
+final_tick 652381344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 164548 # Simulator instruction rate (inst/s)
-host_op_rate 164548 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 58155841 # Simulator tick rate (ticks/s)
-host_mem_usage 223896 # Number of bytes of host memory used
-host_seconds 11079.10 # Real time elapsed on the host
+host_inst_rate 170851 # Simulator instruction rate (inst/s)
+host_op_rate 170851 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61139648 # Simulator tick rate (ticks/s)
+host_mem_usage 240236 # Number of bytes of host memory used
+host_seconds 10670.35 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 190848 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 94463936 # Number of bytes read from this memory
-system.physmem.bytes_read::total 94654784 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 190848 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 190848 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 191616 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 94459904 # Number of bytes read from this memory
+system.physmem.bytes_read::total 94651520 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 191616 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 191616 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory
system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2982 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1475999 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1478981 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2994 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1475936 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1478930 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 296203 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 146611622 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 146907826 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 296203 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 296203 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6645007 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6645007 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6645007 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 296203 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 146611622 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 153552833 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 293718 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 144792467 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 145086184 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 293718 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 293718 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6562836 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6562836 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6562836 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 293718 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 144792467 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 151649021 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1478931 # Total number of read requests seen
+system.physmem.writeReqs 66898 # Total number of write requests seen
+system.physmem.cpureqs 1545829 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 94651520 # Total number of bytes read from memory
+system.physmem.bytesWritten 4281472 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 94651520 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 4281472 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 3904 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 91678 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 92672 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 91873 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 92907 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 92232 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 92052 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 92519 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 92192 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 92430 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 91951 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 91930 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 92149 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 91869 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 92596 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 91765 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 92212 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 4187 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 4171 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 4158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 4346 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 4296 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 4159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 4199 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 4202 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 4131 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 4109 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 4102 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 4160 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 4198 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 4170 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 4213 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 652381327000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 1478931 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 66898 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 1404621 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 67056 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2986 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 181 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2901 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 2909 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 2908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 2908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 2908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 2908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 2908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 2908 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 5885504293 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 50112950293 # Sum of mem lat for all requests
+system.physmem.totBusLat 5900108000 # Total cycles spent in databus access
+system.physmem.totBankLat 38327338000 # Total cycles spent in bank access
+system.physmem.avgQLat 3990.10 # Average queueing delay per request
+system.physmem.avgBankLat 25984.16 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 33974.26 # Average memory access latency
+system.physmem.avgRdBW 145.09 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 6.56 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 145.09 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 6.56 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.95 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.08 # Average read queue length over time
+system.physmem.avgWrQLen 10.99 # Average write queue length over time
+system.physmem.readRowHits 824972 # Number of row buffer hits during reads
+system.physmem.writeRowHits 37277 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 55.93 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 55.72 # Row buffer hit rate for writes
+system.physmem.avgGap 422026.84 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 526091283 # DTB read hits
-system.cpu.dtb.read_misses 609189 # DTB read misses
+system.cpu.dtb.read_hits 526096858 # DTB read hits
+system.cpu.dtb.read_misses 613073 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 526700472 # DTB read accesses
-system.cpu.dtb.write_hits 292251681 # DTB write hits
-system.cpu.dtb.write_misses 54656 # DTB write misses
+system.cpu.dtb.read_accesses 526709931 # DTB read accesses
+system.cpu.dtb.write_hits 292394059 # DTB write hits
+system.cpu.dtb.write_misses 53899 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 292306337 # DTB write accesses
-system.cpu.dtb.data_hits 818342964 # DTB hits
-system.cpu.dtb.data_misses 663845 # DTB misses
+system.cpu.dtb.write_accesses 292447958 # DTB write accesses
+system.cpu.dtb.data_hits 818490917 # DTB hits
+system.cpu.dtb.data_misses 666972 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 819006809 # DTB accesses
-system.cpu.itb.fetch_hits 402493704 # ITB hits
-system.cpu.itb.fetch_misses 819 # ITB misses
+system.cpu.dtb.data_accesses 819157889 # DTB accesses
+system.cpu.itb.fetch_hits 401734157 # ITB hits
+system.cpu.itb.fetch_misses 1039 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 402494523 # ITB accesses
+system.cpu.itb.fetch_accesses 401735196 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
-system.cpu.numCycles 1288628209 # number of cpu cycles simulated
+system.cpu.numCycles 1304762689 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 393523603 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 256622136 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 27591372 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 324682531 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 262034039 # Number of BTB hits
+system.cpu.BPredUnit.lookups 395100113 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 257879210 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 27591675 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 325941438 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 262133239 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 57682078 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 6792 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 421081938 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3322079900 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 393523603 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 319716117 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 638226273 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 162822813 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 94445154 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 8938 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 402493704 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 9540813 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1288505558 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.578243 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.138227 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 57700479 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 6698 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 421496575 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3322405570 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 395100113 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 319833718 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 638480554 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 162110923 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 102053744 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 9801 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 401734157 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 8363180 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1296072068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.563442 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.138795 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 650279285 50.47% 50.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 59669001 4.63% 55.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 43760756 3.40% 58.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 72624833 5.64% 64.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 127388332 9.89% 74.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46848563 3.64% 77.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 41619525 3.23% 80.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 7020509 0.54% 81.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 239294754 18.57% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 657591514 50.74% 50.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 60871982 4.70% 55.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 44636510 3.44% 58.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 71794407 5.54% 64.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 126302912 9.75% 74.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 45673565 3.52% 77.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 41643401 3.21% 80.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7024748 0.54% 81.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 240533029 18.56% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1288505558 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.305382 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.577997 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 453351036 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 77522549 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 613342023 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9559025 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 134730925 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 33522574 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12306 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3228150524 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 46600 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 134730925 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 483601779 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 32079469 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 25997 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 591314469 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 46752919 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3136805366 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 365 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 7001 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 40828800 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2086363185 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3649389993 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3531980340 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 117409653 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1296072068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.302814 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.546368 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 453815792 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 84580008 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 615145766 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 8511561 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 134018941 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 34684248 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12433 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3231024090 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 46816 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 134018941 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 483692761 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37815213 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 26926 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 592981976 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 47536251 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3144588480 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1177 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 7026 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 41373292 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2089769744 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3655475569 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3535468644 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 120006925 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 701394115 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4228 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 134 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 140886298 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 736269341 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 360318998 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 68834783 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 9382400 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2642228655 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2193185137 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 17944949 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 819070745 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 708820503 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 83 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1288505558 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.702115 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.805670 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 704800674 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4226 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 127 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 142344309 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 735042012 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 359395829 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 68166545 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 9320020 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2645223582 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 121 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2193823681 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 17946245 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 822107127 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 708225593 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 82 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1296072068 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.692671 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.804037 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 470226956 36.49% 36.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 215277039 16.71% 53.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 253569254 19.68% 72.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 121312750 9.41% 82.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 106354397 8.25% 90.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 77759673 6.03% 96.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 21099202 1.64% 98.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 17230121 1.34% 99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5676166 0.44% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 475835975 36.71% 36.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 218666129 16.87% 53.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 251350949 19.39% 72.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 122837911 9.48% 82.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 105713044 8.16% 90.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 77520434 5.98% 96.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 21238629 1.64% 98.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 17216175 1.33% 99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 5692822 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1288505558 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1296072068 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1175249 3.24% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 24027488 66.23% 69.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 11077412 30.53% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1168166 3.19% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 25201102 68.89% 72.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 10214807 27.92% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1255595425 57.25% 57.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 16675 0.00% 57.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 29225002 1.33% 58.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 7204653 0.33% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 589172005 26.86% 86.15% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 303713925 13.85% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1258217376 57.35% 57.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 16681 0.00% 57.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 29224824 1.33% 58.69% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 8254695 0.38% 59.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 7204652 0.33% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 587046185 26.76% 86.15% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 303856512 13.85% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2193185137 # Type of FU issued
-system.cpu.iq.rate 1.701953 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 36280149 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.016542 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5574611120 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3377500690 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2021426713 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 154489810 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 83871907 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 75374894 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2150389693 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 79072841 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 67211668 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2193823681 # Type of FU issued
+system.cpu.iq.rate 1.681397 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 36584075 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.016676 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5583657415 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3378809764 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2023568909 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 154592335 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 88593840 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 75404787 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2151259351 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 79145653 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 62323542 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 225199315 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 24267 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 76315 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 149524102 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 223971986 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 12645 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 76017 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 148600933 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4398 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 4436 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 69 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 134730925 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 4001327 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 199767 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 3000725705 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 2706866 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 736269341 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 360318998 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 195059 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 4865 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 76315 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 27584399 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 31784 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 27616183 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2101081456 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 526700571 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 92103681 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 134018941 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 11876310 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 832949 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 3002252422 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 2341492 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 735042012 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 359395829 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 121 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 187560 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 4854 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 76017 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 27589712 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 31349 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 27621061 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2103239947 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 526710042 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 90583734 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 358496928 # number of nop insts executed
-system.cpu.iew.exec_refs 819007361 # number of memory reference insts executed
-system.cpu.iew.exec_branches 281208089 # Number of branches executed
-system.cpu.iew.exec_stores 292306790 # Number of stores executed
-system.cpu.iew.exec_rate 1.630479 # Inst execution rate
-system.cpu.iew.wb_sent 2099578580 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2096801607 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1184710151 # num instructions producing a value
-system.cpu.iew.wb_consumers 1754117094 # num instructions consuming a value
+system.cpu.iew.exec_nop 357028719 # number of nop insts executed
+system.cpu.iew.exec_refs 819158443 # number of memory reference insts executed
+system.cpu.iew.exec_branches 282386049 # Number of branches executed
+system.cpu.iew.exec_stores 292448401 # Number of stores executed
+system.cpu.iew.exec_rate 1.611971 # Inst execution rate
+system.cpu.iew.wb_sent 2101749466 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2098973696 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1185216175 # num instructions producing a value
+system.cpu.iew.wb_consumers 1752698092 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.627158 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.675388 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.608702 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.676224 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 975019383 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 976452699 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 27579200 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1153774633 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.741231 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.495587 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 27579406 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1162053127 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.728826 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.486115 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 537356152 46.57% 46.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 227667410 19.73% 66.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 119239977 10.33% 76.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 56780365 4.92% 81.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 50766064 4.40% 85.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 24581833 2.13% 88.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 18432159 1.60% 89.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 15672614 1.36% 91.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 103278059 8.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 542846661 46.71% 46.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 230306455 19.82% 66.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 119679848 10.30% 76.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 57176464 4.92% 81.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 50189917 4.32% 86.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 25112757 2.16% 88.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 18284566 1.57% 89.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 15890460 1.37% 91.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 102565999 8.83% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1153774633 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1162053127 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 103278059 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 102565999 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 4028867151 # The number of ROB reads
-system.cpu.rob.rob_writes 6102747283 # The number of ROB writes
-system.cpu.timesIdled 3543 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 122651 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 4039291021 # The number of ROB reads
+system.cpu.rob.rob_writes 6104902002 # The number of ROB writes
+system.cpu.timesIdled 33492 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 8690621 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
-system.cpu.cpi 0.706855 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.706855 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.414716 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.414716 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2678227479 # number of integer regfile reads
-system.cpu.int_regfile_writes 1517398403 # number of integer regfile writes
-system.cpu.fp_regfile_reads 81948895 # number of floating regfile reads
-system.cpu.fp_regfile_writes 54035615 # number of floating regfile writes
+system.cpu.cpi 0.715706 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.715706 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.397222 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.397222 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2679345799 # number of integer regfile reads
+system.cpu.int_regfile_writes 1518234716 # number of integer regfile writes
+system.cpu.fp_regfile_reads 81979255 # number of floating regfile reads
+system.cpu.fp_regfile_writes 54034777 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 8420 # number of replacements
-system.cpu.icache.tagsinuse 1668.242053 # Cycle average of tags in use
-system.cpu.icache.total_refs 402482315 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 10141 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 39688.621931 # Average number of references to valid blocks.
+system.cpu.icache.replacements 8417 # number of replacements
+system.cpu.icache.tagsinuse 1668.126238 # Cycle average of tags in use
+system.cpu.icache.total_refs 401722811 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 10139 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 39621.541671 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1668.242053 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.814571 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.814571 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 402482315 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 402482315 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 402482315 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 402482315 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 402482315 # number of overall hits
-system.cpu.icache.overall_hits::total 402482315 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 11389 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 11389 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 11389 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 11389 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 11389 # number of overall misses
-system.cpu.icache.overall_misses::total 11389 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 178670000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 178670000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 178670000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 178670000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 178670000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 178670000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 402493704 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 402493704 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 402493704 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 402493704 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 402493704 # number of overall (read+write) accesses
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-system.cpu.l2cache.demand_mshr_misses::total 1478981 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2982 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1475999 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 1478981 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96989500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44003988500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44100978000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913645500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913645500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96989500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46917634000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 47014623500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96989500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46917634000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 47014623500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964838 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960212 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933614 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933614 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963379 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.958977 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963379 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.958977 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32524.983233 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31227.504751 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31230.244653 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43580.260855 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43580.260855 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32524.983233 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31787.036441 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31788.524329 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32524.983233 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31787.036441 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31788.524329 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2995 # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_misses::total 66855 # number of ReadExReq MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49028505930 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3470186582 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106523142 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 52498692512 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 52605215654 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106523142 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 52498692512 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 52605215654 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965039 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960421 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933612 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933612 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963570 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.959176 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963570 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.959176 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.992321 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34794.668248 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34796.306340 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51906.163817 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51906.163817 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35566.992321 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35569.762179 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35569.756570 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35566.992321 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35569.762179 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35569.756570 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.659244 # Number of seconds simulated
-sim_ticks 659244465000 # Number of ticks simulated
-final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.659992 # Number of seconds simulated
+sim_ticks 659991928000 # Number of ticks simulated
+final_tick 659991928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153116 # Simulator instruction rate (inst/s)
-host_op_rate 208523 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 72914339 # Simulator tick rate (ticks/s)
-host_mem_usage 237584 # Number of bytes of host memory used
-host_seconds 9041.36 # Real time elapsed on the host
-sim_insts 1384375635 # Number of instructions simulated
-sim_ops 1885330387 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 94515200 # Number of bytes read from this memory
-system.physmem.bytes_read::total 94714816 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 199616 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 199616 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory
-system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3119 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1476800 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1479919 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 302795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 143368970 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 143671765 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 302795 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 302795 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6416946 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6416946 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6416946 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 302795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 143368970 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 150088711 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 102750 # Simulator instruction rate (inst/s)
+host_op_rate 139931 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48985343 # Simulator tick rate (ticks/s)
+host_mem_usage 254632 # Number of bytes of host memory used
+host_seconds 13473.25 # Real time elapsed on the host
+sim_insts 1384374560 # Number of instructions simulated
+sim_ops 1885329312 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 198528 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 94517696 # Number of bytes read from this memory
+system.physmem.bytes_read::total 94716224 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 198528 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 198528 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
+system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3102 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1476839 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1479941 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 300804 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 143210382 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 143511185 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 300804 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 300804 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6409581 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6409581 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6409581 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 300804 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 143210382 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 149920767 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1479941 # Total number of read requests seen
+system.physmem.writeReqs 66098 # Total number of write requests seen
+system.physmem.cpureqs 1550203 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 94716224 # Total number of bytes read from memory
+system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 94716224 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 4222 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4164 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 92954 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 91941 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 92050 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 91689 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 92209 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 92061 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 92149 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 92666 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 91875 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 92213 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 92439 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 92957 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 92247 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 91863 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 92572 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 91834 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 4102 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 4129 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 4105 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 4104 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 4141 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 4162 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 4162 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 659991863500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 1479941 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 66098 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4164 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 1408404 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66850 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 338 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2842 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 5597502027 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 50332290027 # Sum of mem lat for all requests
+system.physmem.totBusLat 5902876000 # Total cycles spent in databus access
+system.physmem.totBankLat 38831912000 # Total cycles spent in bank access
+system.physmem.avgQLat 3793.07 # Average queueing delay per request
+system.physmem.avgBankLat 26313.89 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 34106.96 # Average memory access latency
+system.physmem.avgRdBW 143.51 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 6.41 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 143.51 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 6.41 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.94 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.08 # Average read queue length over time
+system.physmem.avgWrQLen 14.18 # Average write queue length over time
+system.physmem.readRowHits 809039 # Number of row buffer hits during reads
+system.physmem.writeRowHits 36662 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 54.82 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 55.47 # Row buffer hit rate for writes
+system.physmem.avgGap 426892.12 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
-system.cpu.numCycles 1318488931 # number of cpu cycles simulated
+system.cpu.numCycles 1319983857 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 461326092 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 364071075 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 34100101 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 298580925 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 245422956 # Number of BTB hits
+system.cpu.BPredUnit.lookups 454350981 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 358310478 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 33373061 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 312072233 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 240275028 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 54976315 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 2806988 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 381926912 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2354617227 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 461326092 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 300399271 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 631966560 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 174781634 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 133381872 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1547 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 26290 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 359560180 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 11891763 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1287933807 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.529860 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.156146 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 53876645 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 2808673 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 374001286 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2331861224 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 454350981 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 294151673 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 622796021 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 170528608 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 135818762 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 24217 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 352463772 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11980006 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1269746213 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.542801 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.164977 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 656012764 50.94% 50.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 47127862 3.66% 54.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 105351348 8.18% 62.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 60429666 4.69% 67.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 75027065 5.83% 73.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 45419751 3.53% 76.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 32157937 2.50% 79.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 32241388 2.50% 81.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 234166026 18.18% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 646995456 50.95% 50.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 44687712 3.52% 54.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 102379693 8.06% 62.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 59922071 4.72% 67.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 74129472 5.84% 73.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 45582835 3.59% 76.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 31361893 2.47% 79.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 30601811 2.41% 81.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 234085270 18.44% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1287933807 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.349890 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.785845 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 433461682 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 105761116 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 591844441 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16248270 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 140618298 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 52072887 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12605 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3150187282 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 23939 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 140618298 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 469309271 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 39277977 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 483250 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 570159229 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 68085782 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3069262221 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 155 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4380621 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 54394099 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1922 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 3038163295 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14611934802 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13977694721 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 634240081 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1993148162 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 1045015133 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 27322 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 23140 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 179514029 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 982659180 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 514844433 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 35819898 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 36120464 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2890303698 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 33130 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2506565055 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 17234382 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 992532581 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2476785189 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 10737 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1287933807 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.946191 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.883330 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 1269746213 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.344209 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.766583 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 425403268 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 107718588 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 581478902 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 18055452 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 137090003 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 51078179 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 15137 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3127640414 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 28961 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 137090003 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 461511464 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 39177126 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 530700 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 561763722 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 69673198 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3042064401 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 391 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4490697 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 56029467 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 2572 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2999547883 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14489457877 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13880825981 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 608631896 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1993146442 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 1006401441 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 29463 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 25504 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 180658895 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 975543094 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 514319343 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 34765547 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 38827815 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2864053634 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 32821 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2484775177 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 12535683 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 966091505 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2435627475 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 10643 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1269746213 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.956907 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.886378 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 425460645 33.03% 33.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 193710960 15.04% 48.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 207680071 16.13% 64.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 174651445 13.56% 77.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 137124890 10.65% 88.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 94993427 7.38% 95.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 35869114 2.79% 98.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12687801 0.99% 99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5755454 0.45% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 414113290 32.61% 32.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 194811826 15.34% 47.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 206120235 16.23% 64.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 171548762 13.51% 77.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 130841431 10.30% 88.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 97116191 7.65% 95.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 37554058 2.96% 98.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 12317792 0.97% 99.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 5322628 0.42% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1287933807 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1269746213 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 692420 0.75% 0.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 24115 0.03% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 56113360 61.04% 61.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 35101326 38.18% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 947301 1.02% 1.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 24145 0.03% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 56191268 60.42% 61.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 35841535 38.54% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1147061112 45.76% 45.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11228333 0.45% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 6876483 0.27% 46.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 5512765 0.22% 46.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 16 0.00% 46.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 23755231 0.95% 47.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 846734490 33.78% 81.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 464021335 18.51% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1133457764 45.62% 45.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11237396 0.45% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 6876496 0.28% 46.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 5506177 0.22% 46.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 23536328 0.95% 47.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 838863420 33.76% 81.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 463922306 18.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2506565055 # Type of FU issued
-system.cpu.iq.rate 1.901089 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 91931221 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.036676 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6281789129 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3788847878 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2312502456 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 128440391 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 94088071 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 58648289 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2531838073 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 66658203 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 81288215 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2484775177 # Type of FU issued
+system.cpu.iq.rate 1.882428 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 93004249 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.037430 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6215984950 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3740236476 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2293829225 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 128851549 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 90009348 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 59026271 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2510712861 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 67066565 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 78532237 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 351270990 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 24451 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1405210 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 237848127 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 344155119 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5694 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 1300004 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 237323252 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 140618298 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 16819525 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1547443 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2890351322 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 8718298 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 982659180 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 514844433 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 22537 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1538114 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1067 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1405210 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 36121914 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 2298987 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 38420901 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2424696979 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 800223206 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 81868076 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 137090003 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 17084434 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1439762 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2864100864 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 11154453 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 975543094 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 514319343 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 22441 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1430096 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1153 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 1300004 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 35278606 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1697024 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 36975630 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2406030122 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 793312488 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 78745055 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 14494 # number of nop insts executed
-system.cpu.iew.exec_refs 1240121255 # number of memory reference insts executed
-system.cpu.iew.exec_branches 334180264 # Number of branches executed
-system.cpu.iew.exec_stores 439898049 # Number of stores executed
-system.cpu.iew.exec_rate 1.838997 # Inst execution rate
-system.cpu.iew.wb_sent 2396725321 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2371150745 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1368219909 # num instructions producing a value
-system.cpu.iew.wb_consumers 2564381587 # num instructions consuming a value
+system.cpu.iew.exec_nop 14409 # number of nop insts executed
+system.cpu.iew.exec_refs 1235149676 # number of memory reference insts executed
+system.cpu.iew.exec_branches 329779468 # Number of branches executed
+system.cpu.iew.exec_stores 441837188 # Number of stores executed
+system.cpu.iew.exec_rate 1.822772 # Inst execution rate
+system.cpu.iew.wb_sent 2378266547 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2352855496 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1358943525 # num instructions producing a value
+system.cpu.iew.wb_consumers 2560958188 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.798385 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.533548 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.782488 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.530639 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 1005010225 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 22393 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 34087773 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1147315511 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.643263 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.351044 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 978761117 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 22178 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 33359188 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1132656212 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.664530 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.366367 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 497187613 43.33% 43.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 300050723 26.15% 69.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 93458742 8.15% 77.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 72384885 6.31% 83.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 45393865 3.96% 87.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 22818775 1.99% 89.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15801520 1.38% 91.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 11015018 0.96% 92.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 89204370 7.78% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 484847147 42.81% 42.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 300235204 26.51% 69.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 89818902 7.93% 77.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 73190759 6.46% 83.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 44951546 3.97% 87.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 23093029 2.04% 89.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 15848859 1.40% 91.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 9835568 0.87% 91.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 90835198 8.02% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1147315511 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 1384386651 # Number of instructions committed
-system.cpu.commit.committedOps 1885341403 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 1132656212 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 1384385576 # Number of instructions committed
+system.cpu.commit.committedOps 1885340328 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 908384496 # Number of memory references committed
-system.cpu.commit.loads 631388190 # Number of loads committed
+system.cpu.commit.refs 908384066 # Number of memory references committed
+system.cpu.commit.loads 631387975 # Number of loads committed
system.cpu.commit.membars 9986 # Number of memory barriers committed
-system.cpu.commit.branches 299635404 # Number of branches committed
+system.cpu.commit.branches 299635189 # Number of branches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1653702903 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1653702043 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 89204370 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 90835198 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3948444424 # The number of ROB reads
-system.cpu.rob.rob_writes 5921335810 # The number of ROB writes
-system.cpu.timesIdled 1335770 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 30555124 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1384375635 # Number of Instructions Simulated
-system.cpu.committedOps 1885330387 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 1384375635 # Number of Instructions Simulated
-system.cpu.cpi 0.952407 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.952407 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.049971 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.049971 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12040516185 # number of integer regfile reads
-system.cpu.int_regfile_writes 2278755627 # number of integer regfile writes
-system.cpu.fp_regfile_reads 70304928 # number of floating regfile reads
-system.cpu.fp_regfile_writes 50983418 # number of floating regfile writes
-system.cpu.misc_regfile_reads 3755360027 # number of misc regfile reads
-system.cpu.misc_regfile_writes 13774920 # number of misc regfile writes
-system.cpu.icache.replacements 22971 # number of replacements
-system.cpu.icache.tagsinuse 1659.651348 # Cycle average of tags in use
-system.cpu.icache.total_refs 359526375 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 24666 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 14575.787521 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 3905904114 # The number of ROB reads
+system.cpu.rob.rob_writes 5865307964 # The number of ROB writes
+system.cpu.timesIdled 1232544 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 50237644 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 1384374560 # Number of Instructions Simulated
+system.cpu.committedOps 1885329312 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1384374560 # Number of Instructions Simulated
+system.cpu.cpi 0.953488 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.953488 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.048781 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.048781 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 11951457171 # number of integer regfile reads
+system.cpu.int_regfile_writes 2254061534 # number of integer regfile writes
+system.cpu.fp_regfile_reads 71109797 # number of floating regfile reads
+system.cpu.fp_regfile_writes 50119198 # number of floating regfile writes
+system.cpu.misc_regfile_reads 3727888158 # number of misc regfile reads
+system.cpu.misc_regfile_writes 13774490 # number of misc regfile writes
+system.cpu.icache.replacements 23076 # number of replacements
+system.cpu.icache.tagsinuse 1653.132974 # Cycle average of tags in use
+system.cpu.icache.total_refs 352429997 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 24765 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 14230.971007 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1659.651348 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.810377 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.810377 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 359530551 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 359530551 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 359530551 # number of demand (read+write) hits
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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-system.cpu.l2cache.writebacks::total 66099 # number of writebacks
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system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963201 # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31312.826651 # average ReadReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31299.362134 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31299.362134 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.046793 # Number of seconds simulated
-sim_ticks 46793182500 # Number of ticks simulated
-final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.046394 # Number of seconds simulated
+sim_ticks 46393648500 # Number of ticks simulated
+final_tick 46393648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 131801 # Simulator instruction rate (inst/s)
-host_op_rate 131801 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 69813482 # Simulator tick rate (ticks/s)
-host_mem_usage 220956 # Number of bytes of host memory used
-host_seconds 670.26 # Real time elapsed on the host
+host_inst_rate 96549 # Simulator instruction rate (inst/s)
+host_op_rate 96549 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50704548 # Simulator tick rate (ticks/s)
+host_mem_usage 252684 # Number of bytes of host memory used
+host_seconds 914.98 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10272832 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10787712 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 514880 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 514880 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 514944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10272704 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10787648 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 514944 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 514944 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory
system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 8045 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 160513 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 168558 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 8046 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 160511 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 168557 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 11003312 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 219536938 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 230540250 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 11003312 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 11003312 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 158621397 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 158621397 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 158621397 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 11003312 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 219536938 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 389161648 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 11099450 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 221424793 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 232524243 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 11099450 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 11099450 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 159987417 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 159987417 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 159987417 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 11099450 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 221424793 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 392511660 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 168557 # Total number of read requests seen
+system.physmem.writeReqs 115975 # Total number of write requests seen
+system.physmem.cpureqs 284532 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 10787648 # Total number of bytes read from memory
+system.physmem.bytesWritten 7422400 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 10787648 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7422400 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 10983 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 10544 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 10882 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 10471 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 10736 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 10499 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 10300 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 10074 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 10523 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 10483 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 10797 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 10531 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 10543 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 10030 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 10827 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 10322 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7019 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7391 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7077 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7441 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7201 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6969 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7287 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6971 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7555 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7177 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7254 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7052 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7484 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7300 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 46393600000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 168557 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 115975 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 162958 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 3658 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1045 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 825 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4989 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 5035 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::3 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5043 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5043 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5043 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5043 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5043 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 5042 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::12 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5042 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 54 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 1271098054 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4666794054 # Sum of mem lat for all requests
+system.physmem.totBusLat 674180000 # Total cycles spent in databus access
+system.physmem.totBankLat 2721516000 # Total cycles spent in bank access
+system.physmem.avgQLat 7541.59 # Average queueing delay per request
+system.physmem.avgBankLat 16147.12 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 27688.71 # Average memory access latency
+system.physmem.avgRdBW 232.52 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 159.99 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 232.52 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 159.99 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 2.45 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.10 # Average read queue length over time
+system.physmem.avgWrQLen 10.39 # Average write queue length over time
+system.physmem.readRowHits 152922 # Number of row buffer hits during reads
+system.physmem.writeRowHits 84722 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 90.73 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.05 # Row buffer hit rate for writes
+system.physmem.avgGap 163052.31 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 20277225 # DTB read hits
+system.cpu.dtb.read_hits 20277224 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 20367373 # DTB read accesses
-system.cpu.dtb.write_hits 14736820 # DTB write hits
+system.cpu.dtb.read_accesses 20367372 # DTB read accesses
+system.cpu.dtb.write_hits 14736801 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 14744072 # DTB write accesses
-system.cpu.dtb.data_hits 35014045 # DTB hits
+system.cpu.dtb.write_accesses 14744053 # DTB write accesses
+system.cpu.dtb.data_hits 35014025 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 35111445 # DTB accesses
-system.cpu.itb.fetch_hits 12477645 # ITB hits
-system.cpu.itb.fetch_misses 12958 # ITB misses
+system.cpu.dtb.data_accesses 35111425 # DTB accesses
+system.cpu.itb.fetch_hits 12475425 # ITB hits
+system.cpu.itb.fetch_misses 12954 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 12490603 # ITB accesses
+system.cpu.itb.fetch_accesses 12488379 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 93586366 # number of cpu cycles simulated
+system.cpu.numCycles 92787298 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 18829185 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 12442057 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 5026145 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 16204746 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 5047870 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 1660949 # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.lookups 18828887 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 12440846 # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 5023695 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 16217673 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 5047073 # Number of BTB hits
+system.cpu.branch_predictor.usedRAS 1660946 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 1031 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 31.150565 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 8475762 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 10353423 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 74332851 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct 31.120821 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 8474385 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 10354502 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 74331965 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 126652101 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 65265 # Number of Reads from FP Register File
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+system.cpu.regfile_manager.floatRegFileReads 65206 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 292895 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 14120054 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 35064610 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 4681911 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 233734 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 4915645 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 8856618 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 35.692355 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 44775927 # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses 292836 # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards 14119774 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 35064022 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 4679410 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 233785 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 4913195 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 8859107 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 35.674465 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 44776036 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 78075293 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 78069956 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 311800 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 23300937 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 70285429 # Number of cycles cpu stages are processed.
-system.cpu.activity 75.102210 # Percentage of cycles cpu is active
+system.cpu.timesIdled 311324 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 22508104 # Number of cycles cpu's stages were not processed
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+system.cpu.activity 75.742257 # Percentage of cycles cpu is active
system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
-system.cpu.cpi 1.059380 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 1.050335 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 1.059380 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.943948 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 1.050335 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.952077 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.943948 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 40161098 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 53425268 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 57.086593 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 50931554 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 42654812 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 45.578019 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 50461046 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 43125320 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 46.080772 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 71466223 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 22120143 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 23.636074 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 47482076 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 46104290 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 49.263896 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.replacements 85221 # number of replacements
-system.cpu.icache.tagsinuse 1887.407088 # Cycle average of tags in use
-system.cpu.icache.total_refs 12359392 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 87267 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 141.627328 # Average number of references to valid blocks.
+system.cpu.ipc_total 0.952077 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 39364116 # Number of cycles 0 instructions are processed.
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+system.cpu.stage0.utilization 57.575965 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 50132225 # Number of cycles 0 instructions are processed.
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+system.cpu.stage1.utilization 45.970811 # Percentage of cycles stage was utilized (processing insts).
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+system.cpu.stage2.utilization 46.477015 # Percentage of cycles stage was utilized (processing insts).
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+system.cpu.stage3.runCycles 22120691 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 23.840215 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 46683402 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 46103896 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 49.687723 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements 85246 # number of replacements
+system.cpu.icache.tagsinuse 1892.367381 # Cycle average of tags in use
+system.cpu.icache.total_refs 12357191 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 87292 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 141.561552 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1887.407088 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.921585 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.921585 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 12359392 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 12359392 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 12359392 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 12359392 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 12359392 # number of overall hits
-system.cpu.icache.overall_hits::total 12359392 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 118206 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 118206 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 118206 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 118206 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 118206 # number of overall misses
-system.cpu.icache.overall_misses::total 118206 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1871587000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1871587000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1871587000 # number of demand (read+write) miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4985919806 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339209803 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6079968538 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6419178341 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339209803 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6079968538 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6419178341 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486381 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253669 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911511 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911511 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.578018 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.578018 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40934.369173 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40104.136971 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40282.197222 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40232.698955 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40232.698955 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785483 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.577965 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785483 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.577965 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42158.812205 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37131.710969 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38210.038256 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38046.806154 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38046.806154 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42158.812205 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37878.827856 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38083.131172 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42158.812205 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37878.827856 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38083.131172 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.021083 # Number of seconds simulated
-sim_ticks 21083079000 # Number of ticks simulated
-final_tick 21083079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.021820 # Number of seconds simulated
+sim_ticks 21820020000 # Number of ticks simulated
+final_tick 21820020000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 198104 # Simulator instruction rate (inst/s)
-host_op_rate 198104 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52475767 # Simulator tick rate (ticks/s)
-host_mem_usage 221996 # Number of bytes of host memory used
-host_seconds 401.77 # Real time elapsed on the host
+host_inst_rate 158943 # Simulator instruction rate (inst/s)
+host_op_rate 158943 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 43574235 # Simulator tick rate (ticks/s)
+host_mem_usage 253708 # Number of bytes of host memory used
+host_seconds 500.76 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 559552 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10295232 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10854784 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 559552 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 559552 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7426304 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7426304 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 8743 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 160863 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 169606 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 116036 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 116036 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 26540336 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 488317290 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 514857626 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 26540336 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 26540336 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 352240012 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 352240012 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 352240012 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 26540336 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 488317290 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 867097638 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 559680 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10296000 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10855680 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 559680 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 559680 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7426944 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7426944 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 8745 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 160875 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 169620 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 116046 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 116046 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 25649839 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 471860246 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 497510085 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 25649839 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 25649839 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 340372924 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 340372924 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 340372924 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 25649839 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 471860246 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 837883008 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 169621 # Total number of read requests seen
+system.physmem.writeReqs 116046 # Total number of write requests seen
+system.physmem.cpureqs 285667 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 10855680 # Total number of bytes read from memory
+system.physmem.bytesWritten 7426944 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 10855680 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7426944 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 11095 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 10656 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 10958 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 10512 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 10822 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 10578 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 10358 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 10136 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 10631 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 10535 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 10838 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 10589 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 10582 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 10059 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 10909 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 10352 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7516 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7034 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7412 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7083 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7440 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7204 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7289 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6977 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7287 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7555 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7178 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7257 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7051 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7488 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7299 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 21820003000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 169621 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 116046 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 66903 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 55166 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 38777 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 7012 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 919 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 475 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 187 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 90 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 47 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 34 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2256 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4654 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 5024 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 5039 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5046 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5046 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5046 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5046 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 5046 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 5046 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 2790 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 392 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 5060410122 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7401532122 # Sum of mem lat for all requests
+system.physmem.totBusLat 678440000 # Total cycles spent in databus access
+system.physmem.totBankLat 1662682000 # Total cycles spent in bank access
+system.physmem.avgQLat 29835.56 # Average queueing delay per request
+system.physmem.avgBankLat 9802.97 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 43638.54 # Average memory access latency
+system.physmem.avgRdBW 497.51 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 340.37 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 497.51 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 340.37 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 5.24 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.34 # Average read queue length over time
+system.physmem.avgWrQLen 10.53 # Average write queue length over time
+system.physmem.readRowHits 153635 # Number of row buffer hits during reads
+system.physmem.writeRowHits 84286 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 90.58 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 72.63 # Row buffer hit rate for writes
+system.physmem.avgGap 76382.65 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 22489278 # DTB read hits
-system.cpu.dtb.read_misses 215924 # DTB read misses
-system.cpu.dtb.read_acv 41 # DTB read access violations
-system.cpu.dtb.read_accesses 22705202 # DTB read accesses
-system.cpu.dtb.write_hits 15793400 # DTB write hits
-system.cpu.dtb.write_misses 42287 # DTB write misses
+system.cpu.dtb.read_hits 22500738 # DTB read hits
+system.cpu.dtb.read_misses 216644 # DTB read misses
+system.cpu.dtb.read_acv 44 # DTB read access violations
+system.cpu.dtb.read_accesses 22717382 # DTB read accesses
+system.cpu.dtb.write_hits 15795905 # DTB write hits
+system.cpu.dtb.write_misses 41245 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 15835687 # DTB write accesses
-system.cpu.dtb.data_hits 38282678 # DTB hits
-system.cpu.dtb.data_misses 258211 # DTB misses
-system.cpu.dtb.data_acv 41 # DTB access violations
-system.cpu.dtb.data_accesses 38540889 # DTB accesses
-system.cpu.itb.fetch_hits 14126698 # ITB hits
-system.cpu.itb.fetch_misses 39196 # ITB misses
+system.cpu.dtb.write_accesses 15837150 # DTB write accesses
+system.cpu.dtb.data_hits 38296643 # DTB hits
+system.cpu.dtb.data_misses 257889 # DTB misses
+system.cpu.dtb.data_acv 44 # DTB access violations
+system.cpu.dtb.data_accesses 38554532 # DTB accesses
+system.cpu.itb.fetch_hits 14148494 # ITB hits
+system.cpu.itb.fetch_misses 39336 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 14165894 # ITB accesses
+system.cpu.itb.fetch_accesses 14187830 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 42166161 # number of cpu cycles simulated
+system.cpu.numCycles 43640043 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 16730416 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 10797894 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 473008 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 12422807 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7474415 # Number of BTB hits
+system.cpu.BPredUnit.lookups 16741832 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 10806668 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 477582 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 12162476 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7482577 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1997304 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 44664 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 15021331 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 106728114 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16730416 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9471719 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 19806820 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2130939 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 5131628 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 8233 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 318680 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 14126698 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 218104 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 41829396 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.551510 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.168900 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1995510 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 45710 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 15036393 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 106856108 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16741832 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9478087 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 19828359 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2147542 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 4492220 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 8232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 323266 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 14148494 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 220972 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 41243035 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.590889 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.177319 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 22022576 52.65% 52.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1548600 3.70% 56.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1408416 3.37% 59.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1521519 3.64% 63.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4198220 10.04% 73.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1858565 4.44% 77.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 685862 1.64% 79.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1087856 2.60% 82.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 7497782 17.92% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 21414676 51.92% 51.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1548321 3.75% 55.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1410779 3.42% 59.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1521748 3.69% 62.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4201075 10.19% 72.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1864766 4.52% 77.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 686260 1.66% 79.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1087985 2.64% 81.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 7507425 18.20% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 41829396 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.396774 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.531132 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16130863 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 4679035 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18837705 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 745587 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1436206 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3804156 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 108982 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 104831583 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 305633 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1436206 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 16616599 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2463979 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 82005 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19040737 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2189870 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 103389139 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 244 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 14351 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2051944 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 62312738 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 124671441 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 124212160 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 459281 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 41243035 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.383635 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.448579 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16096491 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 4096982 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18769266 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 833511 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1446785 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3807119 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 110554 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 104936406 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 308694 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1446785 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 16548633 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1976361 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 82879 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19114757 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2073620 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 103469028 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 341 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 14640 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1956889 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 62372396 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 124769861 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 124309039 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 460822 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 9765857 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 5555 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 5551 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 4525057 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 23373120 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16387776 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1111175 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 372431 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 91431067 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 5402 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 89032304 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 124930 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11266116 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 4904200 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 819 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 41829396 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.128463 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.117137 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 9825515 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 5546 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 5543 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 4207574 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 23385563 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16393614 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1121004 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 386917 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 91482649 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 5403 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 89074963 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 123031 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 11309425 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 4934372 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 820 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 41243035 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.159758 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.116316 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 13456265 32.17% 32.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 6919123 16.54% 48.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5589725 13.36% 62.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 4803253 11.48% 73.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4671765 11.17% 84.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2679732 6.41% 91.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1951840 4.67% 95.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1334332 3.19% 98.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 423361 1.01% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 12823282 31.09% 31.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 6988742 16.95% 48.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5560534 13.48% 61.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 4799338 11.64% 73.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4679683 11.35% 84.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2682377 6.50% 91.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1950315 4.73% 95.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1335480 3.24% 98.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 423284 1.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 41829396 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 41243035 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 128041 6.73% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 804964 42.29% 49.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 970251 50.98% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 129257 6.79% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 803786 42.23% 49.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 970116 50.97% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49721701 55.85% 55.85% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 43788 0.05% 55.90% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49746538 55.85% 55.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 43785 0.05% 55.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 121439 0.14% 56.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 86 0.00% 56.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 122461 0.14% 56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 38932 0.04% 56.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 121262 0.14% 56.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 122235 0.14% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 38920 0.04% 56.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 22979273 25.81% 82.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 16004570 17.98% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 22991531 25.81% 82.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 16010548 17.97% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 89032304 # Type of FU issued
-system.cpu.iq.rate 2.111463 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1903256 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.021377 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 221310686 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 102298169 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86978851 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 611504 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 420531 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 298097 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 90629664 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 305896 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1444097 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 89074963 # Type of FU issued
+system.cpu.iq.rate 2.041129 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1903159 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.021366 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 220805862 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 102391842 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87007224 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 613289 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 421743 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 298831 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 90671357 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 306765 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1448727 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3096482 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 5652 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 17147 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1774399 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3108925 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5719 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 17139 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1780237 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2494 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 46 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2546 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 373 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1436206 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1444549 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 56493 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100968085 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 243573 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 23373120 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16387776 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 5402 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 48618 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 436 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 17147 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 252218 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 171298 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 423516 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 88057641 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 22708636 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 974663 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1446785 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1296877 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 55540 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 101030605 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 244499 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 23385563 # Number of dispatched load instructions
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+system.cpu.iew.iewIQFullEvents 48652 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 428 # Number of times the LSQ has become full, causing a stall
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+system.cpu.iew.predictedTakenIncorrect 253350 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 173638 # Number of branches that were predicted not taken incorrectly
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+system.cpu.iew.iewExecutedInsts 88093519 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9531616 # number of nop insts executed
-system.cpu.iew.exec_refs 38544729 # number of memory reference insts executed
-system.cpu.iew.exec_branches 15136263 # Number of branches executed
-system.cpu.iew.exec_stores 15836093 # Number of stores executed
-system.cpu.iew.exec_rate 2.088349 # Inst execution rate
-system.cpu.iew.wb_sent 87691296 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 87276948 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 33460873 # num instructions producing a value
-system.cpu.iew.wb_consumers 43882648 # num instructions consuming a value
+system.cpu.iew.exec_nop 9542553 # number of nop insts executed
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+system.cpu.iew.exec_branches 15140678 # Number of branches executed
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+system.cpu.iew.exec_rate 2.018640 # Inst execution rate
+system.cpu.iew.wb_sent 87722588 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 87306055 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 33473930 # num instructions producing a value
+system.cpu.iew.wb_consumers 43902488 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.069834 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.762508 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.000595 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.762461 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 9477917 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9547814 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 366510 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 40393190 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.187019 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.818394 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 369802 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 2.219824 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.827061 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 17375613 43.02% 43.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 7063647 17.49% 60.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3493568 8.65% 69.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2102678 5.21% 74.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2090838 5.18% 79.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1172557 2.90% 82.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1137405 2.82% 85.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 723784 1.79% 87.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5233100 12.96% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 16770955 42.14% 42.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 7067067 17.76% 59.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3514313 8.83% 68.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2098075 5.27% 74.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2085843 5.24% 79.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1169184 2.94% 82.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1108409 2.79% 84.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 748224 1.88% 86.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5234180 13.15% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::total 39796250 # Number of insts commited each cycle
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5233100 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5234180 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 131661337 # The number of ROB reads
-system.cpu.rob.rob_writes 197076783 # The number of ROB writes
-system.cpu.timesIdled 11011 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 336765 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 131133214 # The number of ROB reads
+system.cpu.rob.rob_writes 197227324 # The number of ROB writes
+system.cpu.timesIdled 14215 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 2397008 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 0.529781 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.529781 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.887574 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.887574 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 116593496 # number of integer regfile reads
-system.cpu.int_regfile_writes 57858579 # number of integer regfile writes
-system.cpu.fp_regfile_reads 252858 # number of floating regfile reads
-system.cpu.fp_regfile_writes 241901 # number of floating regfile writes
-system.cpu.misc_regfile_reads 38310 # number of misc regfile reads
+system.cpu.cpi 0.548299 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.548299 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.823824 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.823824 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 116640350 # number of integer regfile reads
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system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 94995 # number of replacements
-system.cpu.icache.tagsinuse 1931.010955 # Cycle average of tags in use
-system.cpu.icache.total_refs 14025954 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 97043 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 144.533392 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 17649756000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1931.010955 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.942876 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.942876 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 14025954 # number of ReadReq hits
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-system.cpu.icache.ReadReq_misses::total 100744 # number of ReadReq misses
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-system.cpu.icache.overall_misses::total 100744 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 779635000 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_accesses::total 14126698 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 14126698 # number of demand (read+write) accesses
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-system.cpu.icache.ReadReq_miss_rate::total 0.007131 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.007131 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.007131 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7738.773525 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 7738.773525 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 7738.773525 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 7738.773525 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 7738.773525 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 7738.773525 # average overall miss latency
+system.cpu.icache.replacements 93950 # number of replacements
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+system.cpu.icache.overall_miss_latency::total 808544500 # number of overall miss cycles
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+system.cpu.icache.overall_miss_rate::total 0.007035 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8123.789285 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 8123.789285 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 8123.789285 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 8123.789285 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 8123.789285 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 8123.789285 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3700 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 3700 # number of ReadReq MSHR hits
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-system.cpu.icache.demand_mshr_hits::total 3700 # number of demand (read+write) MSHR hits
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+system.cpu.l2cache.ReadExReq_mshr_misses::total 130960 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 8746 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 160875 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 169621 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 8746 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 160875 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 169621 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 306935647 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 916786687 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1223722334 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7694631450 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7694631450 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 306935647 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8611418137 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 8918353784 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 306935647 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8611418137 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 8918353784 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091105 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480462 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.244285 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913122 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913122 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091105 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782150 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.562251 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091105 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782150 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.562251 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35094.402813 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30646.387665 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31652.630144 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58755.585293 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58755.585293 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35094.402813 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53528.628668 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52578.122898 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35094.402813 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53528.628668 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52578.122898 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.023747 # Number of seconds simulated
-sim_ticks 23747395500 # Number of ticks simulated
-final_tick 23747395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.024118 # Number of seconds simulated
+sim_ticks 24118236000 # Number of ticks simulated
+final_tick 24118236000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 142184 # Simulator instruction rate (inst/s)
-host_op_rate 201762 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47606944 # Simulator tick rate (ticks/s)
-host_mem_usage 237384 # Number of bytes of host memory used
-host_seconds 498.82 # Real time elapsed on the host
-sim_insts 70924309 # Number of instructions simulated
-sim_ops 100643556 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 325888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 8028992 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8354880 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 325888 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 325888 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5417728 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5417728 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 5092 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 125453 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 130545 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 84652 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 84652 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 13723105 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 338099898 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 351823003 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 13723105 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 13723105 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 228139882 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 228139882 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 228139882 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 13723105 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 338099898 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 579962885 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 96109 # Simulator instruction rate (inst/s)
+host_op_rate 136382 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32682486 # Simulator tick rate (ticks/s)
+host_mem_usage 260548 # Number of bytes of host memory used
+host_seconds 737.96 # Real time elapsed on the host
+sim_insts 70924474 # Number of instructions simulated
+sim_ops 100643721 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 326720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory
+system.physmem.bytes_read::total 8354752 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 326720 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 326720 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5417408 # Number of bytes written to this memory
+system.physmem.bytes_written::total 5417408 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 5105 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 130543 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 84647 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 84647 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 13546596 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 332861491 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 346408087 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 13546596 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 13546596 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 224618749 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 224618749 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 224618749 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 13546596 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 332861491 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 571026836 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 130544 # Total number of read requests seen
+system.physmem.writeReqs 84647 # Total number of write requests seen
+system.physmem.cpureqs 215212 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 8354752 # Total number of bytes read from memory
+system.physmem.bytesWritten 5417408 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 8354752 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 5417408 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 21 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 8259 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 8120 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 8253 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 7969 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 7982 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 8186 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 8215 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 8129 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 8104 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 8304 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 8313 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 8256 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 8235 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 8061 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 8114 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 8038 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 5294 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 5079 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 5310 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 5269 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 5220 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 5401 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 5230 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 5186 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 5230 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 5326 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 5458 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 5400 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 5367 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 5357 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 5265 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 5255 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 24118216500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 130544 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 84647 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 21 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 69205 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 57726 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 3491 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3556 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3679 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 3680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 125 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 2308860118 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4224446118 # Sum of mem lat for all requests
+system.physmem.totBusLat 522152000 # Total cycles spent in databus access
+system.physmem.totBankLat 1393434000 # Total cycles spent in bank access
+system.physmem.avgQLat 17687.26 # Average queueing delay per request
+system.physmem.avgBankLat 10674.55 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 32361.81 # Average memory access latency
+system.physmem.avgRdBW 346.41 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 224.62 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 346.41 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 224.62 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 3.57 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.18 # Average read queue length over time
+system.physmem.avgWrQLen 10.22 # Average write queue length over time
+system.physmem.readRowHits 119025 # Number of row buffer hits during reads
+system.physmem.writeRowHits 63519 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes
+system.physmem.avgGap 112078.18 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 47494792 # number of cpu cycles simulated
+system.cpu.numCycles 48236473 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 16945853 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12976600 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 671047 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11791616 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7980415 # Number of BTB hits
+system.cpu.BPredUnit.lookups 16941730 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12971297 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 673506 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 11955063 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7993850 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1850372 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 114214 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 12555295 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 86800259 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16945853 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9830787 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21603869 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2612787 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 10088905 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 11920379 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 192164 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 46165707 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.632126 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.343505 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1846956 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 114386 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 12578866 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 86846522 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16941730 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9840806 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21621241 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2621679 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 9822158 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 11935876 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 192083 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 45946369 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.646136 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.346825 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24583523 53.25% 53.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2172032 4.70% 57.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2013449 4.36% 62.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2091121 4.53% 66.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1494392 3.24% 70.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1411801 3.06% 73.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 982905 2.13% 75.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1224192 2.65% 77.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10192292 22.08% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24346810 52.99% 52.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2176798 4.74% 57.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2018114 4.39% 62.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2096656 4.56% 66.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1493050 3.25% 69.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1410144 3.07% 73.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 982338 2.14% 75.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1219252 2.65% 77.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10203207 22.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46165707 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.356794 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.827574 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 14647959 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8470510 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19858799 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1377235 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1811204 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3409264 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 108749 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 118806925 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 370081 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1811204 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 16375618 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2381141 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 742521 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19461585 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5393638 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 116666793 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 61 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 9401 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4563999 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 255 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 117035573 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 537232740 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 537225721 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 7019 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 99159360 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 17876213 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 25291 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 25289 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12820996 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29922759 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 22636012 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3511140 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4209388 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 112770529 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 41465 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 108119060 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 319934 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 12017924 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 28288746 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 4343 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 46165707 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.341978 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.993843 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 45946369 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.351222 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.800433 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 14667970 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8208523 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19889635 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1362773 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1817468 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3410064 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 108805 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 118869438 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 371525 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1817468 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 16391147 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2180805 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 744758 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19482609 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5329582 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 116713190 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 108 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 9859 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4505903 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 207 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 117071318 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 537479367 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 537472531 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 6836 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 99159624 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 17911694 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 25668 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 25645 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12679365 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29945230 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 22644975 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 3554453 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 4308488 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 112817859 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 41708 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 108131794 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 320520 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 12061302 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 28451439 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 4553 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 45946369 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.353435 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.992555 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10763393 23.31% 23.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 8065577 17.47% 40.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7395154 16.02% 56.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7189034 15.57% 72.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5495666 11.90% 84.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3896907 8.44% 92.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1882413 4.08% 96.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 886108 1.92% 98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 591455 1.28% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10567306 23.00% 23.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 8020118 17.46% 40.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7429171 16.17% 56.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7172224 15.61% 72.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5474021 11.91% 84.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3920572 8.53% 92.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1887629 4.11% 96.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 890680 1.94% 98.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 584648 1.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 46165707 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 45946369 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 111137 4.37% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1401194 55.04% 59.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1033519 40.60% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 112571 4.42% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1415190 55.57% 59.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 1018757 40.01% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 57171551 52.88% 52.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 91476 0.08% 52.96% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57176824 52.88% 52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 91588 0.08% 52.96% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.96% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 254 0.00% 52.96% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 236 0.00% 52.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 29115621 26.93% 79.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21740151 20.11% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 29115499 26.93% 79.89% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21747640 20.11% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 108119060 # Type of FU issued
-system.cpu.iq.rate 2.276440 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2545850 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.023547 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 265268953 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 124855497 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 106214423 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 658 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1042 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 198 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 110664579 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 331 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2183386 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 108131794 # Type of FU issued
+system.cpu.iq.rate 2.241702 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2546520 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.023550 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 265076321 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 124946354 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 106228285 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1064 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 184 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 110677977 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2176777 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2612315 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 8134 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 27815 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2076938 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2634753 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7333 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 27466 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2085868 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1811204 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 969930 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 37593 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 112821828 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 344750 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29922759 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 22636012 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 24938 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1077 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 4742 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 27815 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 448633 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 200270 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 648903 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 106941825 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 28766464 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1177235 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1817468 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 825568 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 31883 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 112869381 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewExecutedInsts 106955311 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9834 # number of nop insts executed
-system.cpu.iew.exec_refs 50197967 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14707935 # Number of branches executed
-system.cpu.iew.exec_stores 21431503 # Number of stores executed
-system.cpu.iew.exec_rate 2.251654 # Inst execution rate
-system.cpu.iew.wb_sent 106459563 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 106214621 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 53551409 # num instructions producing a value
-system.cpu.iew.wb_consumers 103987749 # num instructions consuming a value
+system.cpu.iew.exec_nop 9814 # number of nop insts executed
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+system.cpu.iew.wb_producers 53599142 # num instructions producing a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.236342 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.514978 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.202244 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.514015 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 12173182 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 37122 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 565028 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::stdev 2.754788 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 12220612 # The number of squashed insts skipped by commit
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 15099779 34.04% 34.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11755524 26.50% 60.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3528202 7.95% 68.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2907503 6.56% 75.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1884478 4.25% 79.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1967896 4.44% 83.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 685684 1.55% 85.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 580329 1.31% 86.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5945109 13.40% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 14889585 33.74% 33.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11723135 26.57% 60.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3525477 7.99% 68.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2911105 6.60% 74.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1898953 4.30% 79.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1983472 4.49% 83.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 685141 1.55% 85.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 578421 1.31% 86.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5933613 13.45% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 44354504 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 70929861 # Number of instructions committed
-system.cpu.commit.committedOps 100649108 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 44128902 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 70930026 # Number of instructions committed
+system.cpu.commit.committedOps 100649273 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 47869518 # Number of memory references committed
-system.cpu.commit.loads 27310444 # Number of loads committed
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system.cpu.commit.membars 15920 # Number of memory barriers committed
-system.cpu.commit.branches 13744841 # Number of branches committed
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system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 91486123 # Number of committed integer instructions.
+system.cpu.commit.int_insts 91486255 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5945109 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5933613 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 151206386 # The number of ROB reads
-system.cpu.rob.rob_writes 227466743 # The number of ROB writes
-system.cpu.timesIdled 61795 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 1329085 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 70924309 # Number of Instructions Simulated
-system.cpu.committedOps 100643556 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 70924309 # Number of Instructions Simulated
-system.cpu.cpi 0.669655 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.669655 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.493307 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.493307 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 514746035 # number of integer regfile reads
-system.cpu.int_regfile_writes 104090442 # number of integer regfile writes
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-system.cpu.misc_regfile_reads 145207051 # number of misc regfile reads
-system.cpu.misc_regfile_writes 38512 # number of misc regfile writes
-system.cpu.icache.replacements 28686 # number of replacements
-system.cpu.icache.tagsinuse 1815.800680 # Cycle average of tags in use
-system.cpu.icache.total_refs 11888473 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 30726 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 386.918994 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 151039875 # The number of ROB reads
+system.cpu.rob.rob_writes 227567987 # The number of ROB writes
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+system.cpu.idleCycles 2290104 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 70924474 # Number of Instructions Simulated
+system.cpu.committedOps 100643721 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 70924474 # Number of Instructions Simulated
+system.cpu.cpi 0.680110 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.680110 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.470350 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.470350 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 514798749 # number of integer regfile reads
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+system.cpu.misc_regfile_writes 38578 # number of misc regfile writes
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+system.cpu.icache.total_refs 11903209 # Total number of references to valid blocks.
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+system.cpu.icache.avg_refs 376.743440 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1815.800680 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.886621 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.886621 # Average percentage of cache occupancy
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-system.cpu.icache.overall_hits::total 11888474 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 31905 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 31905 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 31905 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 328897000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 328897000 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 328897000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11920379 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11920379 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 11920379 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11920379 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11920379 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002677 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.002677 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.002677 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.002677 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10308.635010 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10308.635010 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 10308.635010 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10308.635010 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10308.635010 # average overall miss latency
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11071.419825 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 11071.419825 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1159 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1159 # number of ReadReq MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 1159 # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 30746 # number of ReadReq MSHR misses
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-system.cpu.icache.demand_mshr_misses::total 30746 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 30746 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 30746 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 238224500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 238224500 # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total 238224500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 238224500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 238224500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002579 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002579 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.002579 # mshr miss rate for demand accesses
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-system.cpu.icache.overall_mshr_miss_rate::total 0.002579 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7748.146100 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7748.146100 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7748.146100 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 7748.146100 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7748.146100 # average overall mshr miss latency
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771624 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.675325 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32302.042419 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33631.752960 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33391.905774 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31500 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31500 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33186.111518 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33186.111518 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32302.042419 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33268.303668 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33230.613965 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32302.042419 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33268.303668 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33230.613965 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 84647 # number of writebacks
+system.cpu.l2cache.writebacks::total 84647 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 83 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5106 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23122 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 28228 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 21 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 21 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102316 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 102316 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 5106 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 125438 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 130544 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 5106 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 125438 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 130544 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187620086 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 964824313 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1152444399 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 21021 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 21021 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3752861945 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3752861945 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187620086 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4717686258 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 4905306344 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187620086 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4717686258 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 4905306344 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.161618 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416470 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.324043 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.954545 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.954545 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956046 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956046 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.161618 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771741 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.672450 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.161618 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771741 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.672450 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36745.022718 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41727.545757 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40826.285922 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36679.130781 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36679.130781 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36745.022718 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37609.705655 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37575.885096 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36745.022718 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37609.705655 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37575.885096 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.983203 # Number of seconds simulated
-sim_ticks 983202553500 # Number of ticks simulated
-final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.998096 # Number of seconds simulated
+sim_ticks 998095972500 # Number of ticks simulated
+final_tick 998095972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 119503 # Simulator instruction rate (inst/s)
-host_op_rate 119503 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64565869 # Simulator tick rate (ticks/s)
-host_mem_usage 212872 # Number of bytes of host memory used
-host_seconds 15227.90 # Real time elapsed on the host
+host_inst_rate 135518 # Simulator instruction rate (inst/s)
+host_op_rate 135518 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 74327611 # Simulator tick rate (ticks/s)
+host_mem_usage 465236 # Number of bytes of host memory used
+host_seconds 13428.33 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 137579776 # Number of bytes read from this memory
-system.physmem.bytes_read::total 137634752 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 137579264 # Number of bytes read from this memory
+system.physmem.bytes_read::total 137634240 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory
-system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 67104640 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67104640 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2149684 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2150543 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 55915 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 139930247 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 139986162 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 55915 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 55915 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 68251540 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 68251540 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 68251540 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 55915 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 139930247 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 208237702 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 2149676 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2150535 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1048510 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1048510 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 55081 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 137841718 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 137896799 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 55081 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 55081 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 67232653 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 67232653 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 67232653 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 55081 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 137841718 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 205129452 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2150535 # Total number of read requests seen
+system.physmem.writeReqs 1048510 # Total number of write requests seen
+system.physmem.cpureqs 3199045 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 137634240 # Total number of bytes read from memory
+system.physmem.bytesWritten 67104640 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 137634240 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 67104640 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 1104 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 134750 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 134519 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 135461 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 133443 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 134821 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 134519 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 135107 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 134152 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 133438 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 134313 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 134956 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 130690 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 131784 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 134689 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 137104 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 135685 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 65615 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 65313 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 65943 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 64961 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 65149 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 64711 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 65179 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 65010 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 64600 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 65119 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 65708 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 64486 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 65220 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 66941 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 67682 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 66873 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 998095934500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 2150535 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 1048510 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 1835130 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 153641 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 61976 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 38042 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 24246 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 14808 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 8848 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 5750 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 4166 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 2824 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 43501 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 44806 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 45260 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 45477 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 45551 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 45580 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 45588 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 45587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 2087 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 328 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 19730119710 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 92821713710 # Sum of mem lat for all requests
+system.physmem.totBusLat 8597724000 # Total cycles spent in databus access
+system.physmem.totBankLat 64493870000 # Total cycles spent in bank access
+system.physmem.avgQLat 9179.23 # Average queueing delay per request
+system.physmem.avgBankLat 30005.09 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 43184.32 # Average memory access latency
+system.physmem.avgRdBW 137.90 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 67.23 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 137.90 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 67.23 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 1.28 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.09 # Average read queue length over time
+system.physmem.avgWrQLen 11.29 # Average write queue length over time
+system.physmem.readRowHits 884898 # Number of row buffer hits during reads
+system.physmem.writeRowHits 338451 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 41.17 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 32.28 # Row buffer hit rate for writes
+system.physmem.avgGap 311998.09 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 444615529 # DTB read hits
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system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 449512607 # DTB read accesses
-system.cpu.dtb.write_hits 160920414 # DTB write hits
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system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 162621718 # DTB write accesses
-system.cpu.dtb.data_hits 605535943 # DTB hits
+system.cpu.dtb.write_accesses 162619212 # DTB write accesses
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system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 612134325 # DTB accesses
-system.cpu.itb.fetch_hits 232170189 # ITB hits
+system.cpu.dtb.data_accesses 612144306 # DTB accesses
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system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 232170211 # ITB accesses
+system.cpu.itb.fetch_accesses 232077790 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1966405108 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 328916467 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 253806684 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 140065896 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 232656738 # Number of BTB lookups
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+system.cpu.branch_predictor.lookups 328934492 # Number of BP lookups
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system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 59.367510 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 175157469 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 153758998 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
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-system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 650997764 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 617989099 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 121287494 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 12179944 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 133467438 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 81732764 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 62.020127 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 1139628962 # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File
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+system.cpu.execution_unit.mispredicted 133474136 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 81726090 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 62.023232 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 1139616626 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.icache.replacements 1 # number of replacements
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system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
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+system.cpu.icache.avg_refs 270170.772992 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.occ_percent::total 0.325468 # Average percentage of cache occupancy
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-system.cpu.icache.ReadReq_hits::total 232169108 # number of ReadReq hits
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-system.cpu.icache.demand_hits::total 232169108 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 232169108 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 1077 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 1077 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 1077 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 58736500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54855.646100 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54855.646100 # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency
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-system.cpu.l2cache.Writeback_accesses::total 3389692 # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53849.243306 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52491.863915 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52492.720183 # average ReadReq miss latency
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40277.243431 # average ReadReq mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.601742 # Number of seconds simulated
-sim_ticks 601741522500 # Number of ticks simulated
-final_tick 601741522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.622687 # Number of seconds simulated
+sim_ticks 622686686500 # Number of ticks simulated
+final_tick 622686686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 165987 # Simulator instruction rate (inst/s)
-host_op_rate 165987 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 57533745 # Simulator tick rate (ticks/s)
-host_mem_usage 213900 # Number of bytes of host memory used
-host_seconds 10458.93 # Real time elapsed on the host
+host_inst_rate 130099 # Simulator instruction rate (inst/s)
+host_op_rate 130099 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 46664017 # Simulator tick rate (ticks/s)
+host_mem_usage 466244 # Number of bytes of host memory used
+host_seconds 13344.04 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 138172352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 138234112 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 67207424 # Number of bytes written to this memory
-system.physmem.bytes_written::total 67207424 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2158943 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2159908 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1050116 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1050116 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 102635 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 229620770 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 229723406 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 102635 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 102635 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 111688194 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 111688194 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 111688194 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 102635 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 229620770 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 341411600 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 67206720 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67206720 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2158955 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2159916 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1050105 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1050105 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 98772 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 221898305 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 221997077 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 98772 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 98772 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 107930234 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 107930234 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 107930234 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 98772 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 221898305 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 329927311 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2159916 # Total number of read requests seen
+system.physmem.writeReqs 1050105 # Total number of write requests seen
+system.physmem.cpureqs 3210021 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 138234624 # Total number of bytes read from memory
+system.physmem.bytesWritten 67206720 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 138234624 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 67206720 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 1101 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 135516 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 134944 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 135958 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 133984 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 135382 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 135012 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 135645 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 134678 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 134063 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 135260 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 135483 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 131205 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 132348 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 135290 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 137712 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 136335 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 65727 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 65366 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 66027 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 65044 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 65255 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 64804 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 65281 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 65090 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 64712 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 65264 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 65787 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 64601 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 65333 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 67038 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 67805 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 66971 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 622686634000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 2159916 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 1050105 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 1715217 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 265103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 85338 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 37466 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 21744 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 13852 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 9060 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 6661 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2751 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1623 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 42630 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 44902 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 45367 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 45530 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 45641 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 45652 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 45656 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 45657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 45657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 45657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 45657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 45657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 45657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 45657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 45657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 45657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 45657 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 45656 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 45656 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 45656 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 45656 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 45656 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 45656 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 3027 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 755 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 290 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 22793561782 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 94682781782 # Sum of mem lat for all requests
+system.physmem.totBusLat 8635260000 # Total cycles spent in databus access
+system.physmem.totBankLat 63253960000 # Total cycles spent in bank access
+system.physmem.avgQLat 10558.37 # Average queueing delay per request
+system.physmem.avgBankLat 29300.32 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 43858.68 # Average memory access latency
+system.physmem.avgRdBW 222.00 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 107.93 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 222.00 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 107.93 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 2.06 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.15 # Average read queue length over time
+system.physmem.avgWrQLen 10.91 # Average write queue length over time
+system.physmem.readRowHits 893342 # Number of row buffer hits during reads
+system.physmem.writeRowHits 340237 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 41.38 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 32.40 # Row buffer hit rate for writes
+system.physmem.avgGap 193982.11 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 610863506 # DTB read hits
-system.cpu.dtb.read_misses 10801691 # DTB read misses
+system.cpu.dtb.read_hits 610476386 # DTB read hits
+system.cpu.dtb.read_misses 10761875 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 621665197 # DTB read accesses
-system.cpu.dtb.write_hits 207455295 # DTB write hits
-system.cpu.dtb.write_misses 6623437 # DTB write misses
+system.cpu.dtb.read_accesses 621238261 # DTB read accesses
+system.cpu.dtb.write_hits 207269464 # DTB write hits
+system.cpu.dtb.write_misses 6561537 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 214078732 # DTB write accesses
-system.cpu.dtb.data_hits 818318801 # DTB hits
-system.cpu.dtb.data_misses 17425128 # DTB misses
+system.cpu.dtb.write_accesses 213831001 # DTB write accesses
+system.cpu.dtb.data_hits 817745850 # DTB hits
+system.cpu.dtb.data_misses 17323412 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 835743929 # DTB accesses
-system.cpu.itb.fetch_hits 399244233 # ITB hits
-system.cpu.itb.fetch_misses 57 # ITB misses
+system.cpu.dtb.data_accesses 835069262 # DTB accesses
+system.cpu.itb.fetch_hits 398378101 # ITB hits
+system.cpu.itb.fetch_misses 55 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 399244290 # ITB accesses
+system.cpu.itb.fetch_accesses 398378156 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1203483046 # number of cpu cycles simulated
+system.cpu.numCycles 1245373374 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 378630674 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 290853975 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 18842896 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 264245889 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 260518236 # Number of BTB hits
+system.cpu.BPredUnit.lookups 378146140 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 290510585 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 18737073 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 264395160 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 259999350 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 25134989 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 6201 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 410689836 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3138690905 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 378630674 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 285653225 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 572677806 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 132533954 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 108403122 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 399244233 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10255002 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1198760050 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.618281 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.169328 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 25131917 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 6182 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 409812987 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3135210650 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 378146140 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 285131267 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 571966611 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 132239561 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 126137605 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1394 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 398378101 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 10155921 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1214707352 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.581042 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.162326 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 626082244 52.23% 52.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42560367 3.55% 55.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22212227 1.85% 57.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 40796625 3.40% 61.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 126320083 10.54% 71.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 63645436 5.31% 76.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 40565089 3.38% 80.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 30205669 2.52% 82.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 206372310 17.22% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 642740741 52.91% 52.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42508733 3.50% 56.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22198972 1.83% 58.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 40683898 3.35% 61.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 126205169 10.39% 71.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 63532228 5.23% 77.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 40428272 3.33% 80.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 30073881 2.48% 83.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 206335458 16.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1198760050 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.314612 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.608006 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 438814843 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95153182 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 542714056 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 15090918 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 106987051 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 60150241 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 1010 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3059802509 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2177 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 106987051 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 459387866 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 50448288 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 5147 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 536142849 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 45788849 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2978016816 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 421943 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1715322 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 41464029 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2227365150 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3845813324 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3844419965 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1393359 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1214707352 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.303641 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.517486 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 437634335 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 113109865 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 542282236 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 14893078 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 106787838 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 60009942 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 1008 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3056719356 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2151 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 106787838 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 458205445 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 68879857 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 5925 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 535635557 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 45192730 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2974950452 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 455085 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1725044 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 40939895 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2225174239 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3842201349 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3840803931 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1397418 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 851162187 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 215 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 214 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 95471202 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 674494217 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 250159031 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 59771171 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 34263403 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2674166611 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 189 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2477607357 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3173205 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 927397839 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 394299937 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 160 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1198760050 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.066808 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.969624 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 848971276 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 208 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 208 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 94220163 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 674209051 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 250003668 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 60248313 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 34574137 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2672716058 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2475684354 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3185220 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 926051369 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 394490469 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1214707352 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.038091 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.971432 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 374466356 31.24% 31.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 190640446 15.90% 47.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 181417957 15.13% 62.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 153622544 12.82% 75.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 136730069 11.41% 86.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 80254846 6.69% 93.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 61695164 5.15% 98.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 14563469 1.21% 99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5369199 0.45% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 391612222 32.24% 32.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 190116739 15.65% 47.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 180710183 14.88% 62.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 153608021 12.65% 75.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 136709031 11.25% 86.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 80377873 6.62% 93.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 61799975 5.09% 98.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 14388617 1.18% 99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 5384691 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1198760050 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1214707352 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2251857 11.87% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 12201284 64.32% 76.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4515049 23.80% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2236018 11.81% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12183595 64.36% 76.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4510642 23.83% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1617068630 65.27% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1615926808 65.27% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 102 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 297 0.00% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 41 0.00% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 639258763 25.80% 91.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 221279320 8.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 638812583 25.80% 91.08% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 220944337 8.92% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2477607357 # Type of FU issued
-system.cpu.iq.rate 2.058697 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 18968190 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6174132781 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3600319262 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2375945234 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1983378 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1347629 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 869060 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2495600765 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 974782 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 56278777 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2475684354 # Type of FU issued
+system.cpu.iq.rate 1.987905 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 18930255 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.007646 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6186206687 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3597520072 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2374361589 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1984848 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1351695 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 870010 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2493639169 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 975440 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 56324993 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 229898554 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 250139 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 103830 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 89430529 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 229613388 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 251555 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 105716 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 89275166 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 234 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 81236 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 232 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 90239 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 106987051 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 18488263 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 963433 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2816062244 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 17529415 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 674494217 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 250159031 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 189 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 221508 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 12923 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 103830 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 13260228 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8848776 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 22109004 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2426798028 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 621666775 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 50809329 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 106787838 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 30509174 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1004696 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2814392916 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 16951249 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 674209051 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 250003668 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 211284 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 14280 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 105716 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 13148912 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8849149 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 21998061 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2424970447 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 621239857 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 50713907 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 141895444 # number of nop insts executed
-system.cpu.iew.exec_refs 835745555 # number of memory reference insts executed
-system.cpu.iew.exec_branches 297016780 # Number of branches executed
-system.cpu.iew.exec_stores 214078780 # Number of stores executed
-system.cpu.iew.exec_rate 2.016479 # Inst execution rate
-system.cpu.iew.wb_sent 2405369179 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2376814294 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1361493757 # num instructions producing a value
-system.cpu.iew.wb_consumers 1724612513 # num instructions consuming a value
+system.cpu.iew.exec_nop 141676677 # number of nop insts executed
+system.cpu.iew.exec_refs 835070896 # number of memory reference insts executed
+system.cpu.iew.exec_branches 296780799 # Number of branches executed
+system.cpu.iew.exec_stores 213831039 # Number of stores executed
+system.cpu.iew.exec_rate 1.947183 # Inst execution rate
+system.cpu.iew.wb_sent 2403689836 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2375231599 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1360982490 # num instructions producing a value
+system.cpu.iew.wb_consumers 1724379175 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.974946 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.789449 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.907245 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.789259 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 756436478 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 754743358 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 18841975 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1091772999 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.666812 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.514787 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 18736187 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1107919514 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.642520 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.504559 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 565636558 51.81% 51.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 181878211 16.66% 68.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 91372107 8.37% 76.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 53285897 4.88% 81.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 36714852 3.36% 85.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 28908245 2.65% 87.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 22459323 2.06% 89.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 22999009 2.11% 91.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 88518797 8.11% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 582245438 52.55% 52.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 181606604 16.39% 68.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 90875132 8.20% 77.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 53034266 4.79% 81.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 36917610 3.33% 85.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 29689254 2.68% 87.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 22142026 2.00% 89.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 22921878 2.07% 92.01% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu.dcache.writebacks::total 3416489 # number of writebacks
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+system.cpu.l2cache.Writeback_accesses::writebacks 3416510 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 3416510 # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36539.378238 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35933.316720 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 35933.741325 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37033.583553 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37033.583553 # average ReadExReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::total 36332.202112 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 47300 # number of cycles access was blocked
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+system.cpu.l2cache.blocked_cycles::no_mshrs 138175 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 3906 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12.109575 # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1050116 # number of writebacks
-system.cpu.l2cache.writebacks::total 1050116 # number of writebacks
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45055642500 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188640 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188747 # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415398 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235170 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235170 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.235250 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33372.020725 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32733.649392 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32734.096633 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33823.259993 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33823.259993 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33372.020725 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33128.579819 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33128.688583 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33372.020725 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33128.579819 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33128.688583 # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47010.516786 # average ReadReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46652.725224 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46652.725224 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46647.508209 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.454149 # Number of seconds simulated
-sim_ticks 454149445000 # Number of ticks simulated
-final_tick 454149445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.473434 # Number of seconds simulated
+sim_ticks 473433799500 # Number of ticks simulated
+final_tick 473433799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 251011 # Simulator instruction rate (inst/s)
-host_op_rate 280022 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 73805166 # Simulator tick rate (ticks/s)
-host_mem_usage 228580 # Number of bytes of host memory used
-host_seconds 6153.36 # Real time elapsed on the host
-sim_insts 1544563043 # Number of instructions simulated
-sim_ops 1723073855 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 48256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 156265984 # Number of bytes read from this memory
-system.physmem.bytes_read::total 156314240 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 48256 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 48256 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 71930048 # Number of bytes written to this memory
-system.physmem.bytes_written::total 71930048 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 754 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2441656 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2442410 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1123907 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1123907 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 106256 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 344084939 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 344191195 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 106256 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 106256 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 158384093 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 158384093 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 158384093 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 106256 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 344084939 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 502575288 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 169995 # Simulator instruction rate (inst/s)
+host_op_rate 189642 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52106394 # Simulator tick rate (ticks/s)
+host_mem_usage 499160 # Number of bytes of host memory used
+host_seconds 9085.91 # Real time elapsed on the host
+sim_insts 1544563083 # Number of instructions simulated
+sim_ops 1723073895 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 48384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 156296704 # Number of bytes read from this memory
+system.physmem.bytes_read::total 156345088 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 48384 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 48384 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 71931712 # Number of bytes written to this memory
+system.physmem.bytes_written::total 71931712 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 756 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2442136 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2442892 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1123933 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1123933 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 102198 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 330134232 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 330236430 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 102198 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 102198 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 151936157 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 151936157 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 151936157 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 102198 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 330134232 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 482172587 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2442892 # Total number of read requests seen
+system.physmem.writeReqs 1123933 # Total number of write requests seen
+system.physmem.cpureqs 3566825 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 156345088 # Total number of bytes read from memory
+system.physmem.bytesWritten 71931712 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 156345088 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 71931712 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 1286 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 151934 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 156031 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 154856 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 153024 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 150249 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 152372 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 153472 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 154746 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 153379 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 151879 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 152199 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 152305 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 150118 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 153271 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 150713 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 151058 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 70393 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 72288 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 71658 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 69978 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 69490 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 69799 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 70024 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 70449 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 69754 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 69615 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 69971 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 69698 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 68976 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 71736 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 70217 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 69887 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 473433771000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 2442892 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 1123933 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 1613567 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 411043 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 122672 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 76227 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 63723 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 50754 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 36534 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 28949 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 23035 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 15102 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 43358 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 46512 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 47775 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 48422 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 48759 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 48833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 48858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 48865 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 48866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 48867 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 48867 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 48867 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 48867 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 48867 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 48867 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 48866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 48866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 48866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 48866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 48866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 48866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 48866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 48866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5509 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 2355 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 1092 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 445 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 108 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 39045821973 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 121584903973 # Sum of mem lat for all requests
+system.physmem.totBusLat 9766424000 # Total cycles spent in databus access
+system.physmem.totBankLat 72772658000 # Total cycles spent in bank access
+system.physmem.avgQLat 15991.86 # Average queueing delay per request
+system.physmem.avgBankLat 29805.24 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 49797.10 # Average memory access latency
+system.physmem.avgRdBW 330.24 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 151.94 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 330.24 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 151.94 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 3.01 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.26 # Average read queue length over time
+system.physmem.avgWrQLen 10.90 # Average write queue length over time
+system.physmem.readRowHits 966664 # Number of row buffer hits during reads
+system.physmem.writeRowHits 336338 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 39.59 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 29.93 # Row buffer hit rate for writes
+system.physmem.avgGap 132732.55 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 908298891 # number of cpu cycles simulated
+system.cpu.numCycles 946867600 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 299221505 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 245089393 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 16036207 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 167476566 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 155260747 # Number of BTB hits
+system.cpu.BPredUnit.lookups 299593765 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 245452602 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 16045022 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 170764551 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 155662191 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 18353715 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 235 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 291143927 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2147541842 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 299221505 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 173614462 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 427042376 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 81995589 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 117912816 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 18346296 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 201 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 291830558 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2150759454 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 299593765 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 174008487 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 427702866 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 82463506 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 122599229 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 94 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 282188311 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5315637 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 901821520 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.649341 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.246532 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 88 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 282801731 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5377782 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 908156186 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.634401 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.243337 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 474779291 52.65% 52.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 22710427 2.52% 55.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 38716038 4.29% 59.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 47664478 5.29% 64.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 40313573 4.47% 69.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46765093 5.19% 74.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38987797 4.32% 78.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 17988591 1.99% 80.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 173896232 19.28% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 480453401 52.90% 52.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 22859151 2.52% 55.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 38736937 4.27% 59.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 47688218 5.25% 64.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 40498646 4.46% 69.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46746329 5.15% 74.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38999717 4.29% 78.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 18064778 1.99% 80.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 174109009 19.17% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 901821520 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.329431 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.364356 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 319221723 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 98997420 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 402809489 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 15071254 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 65721634 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46024947 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 700 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2336308946 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2514 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 65721634 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 340227863 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 45083280 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 12690 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 395699548 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 55076505 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2280327240 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 18280 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4628387 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 42035635 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2254967875 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10525732443 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 10525728121 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4322 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 548647913 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1655 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1650 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 127333779 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 622133622 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 217936550 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 85018666 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 64907509 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2181155194 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1636 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2010118619 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 4778350 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 453891413 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1054915735 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1462 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 901821520 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.228954 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.928169 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 908156186 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.316405 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.271447 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 320351849 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 103310609 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 403372314 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 15098642 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 66022772 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46034722 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2339352792 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2529 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 66022772 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 341796573 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 48717971 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 14906 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 395855837 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 55748127 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2282794185 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 39847 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4611517 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 42695661 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2257537981 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10537280026 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10537275559 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4467 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1706320026 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 551217955 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 838 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 835 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 129599333 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 622569059 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 218142237 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 84983278 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 64739003 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2182778805 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 865 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2010794421 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 4810108 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 455220170 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1060725588 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 908156186 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.214150 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.929063 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 241649201 26.80% 26.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 133398569 14.79% 41.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 156277076 17.33% 58.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 115862389 12.85% 71.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 125673548 13.94% 85.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 75895678 8.42% 94.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 39700475 4.40% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 10713373 1.19% 99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2651211 0.29% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 247277493 27.23% 27.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 133932127 14.75% 41.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 156228000 17.20% 59.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 116195915 12.79% 71.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 125706835 13.84% 85.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 75923793 8.36% 94.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 39533015 4.35% 98.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 10697910 1.18% 99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2661098 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 901821520 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 908156186 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 707951 2.82% 2.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4768 0.02% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 19054904 75.97% 78.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 5315511 21.19% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 703286 2.81% 2.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4771 0.02% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 19012865 76.06% 78.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 5274676 21.10% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1230445204 61.21% 61.21% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 929764 0.05% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1230823853 61.21% 61.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 930532 0.05% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 30 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 585105545 29.11% 90.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193637984 9.63% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 585374477 29.11% 90.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193665439 9.63% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2010118619 # Type of FU issued
-system.cpu.iq.rate 2.213059 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 25083134 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012478 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4951919807 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2635232712 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1952804452 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 778 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 167 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2035201532 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 63665905 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2010794421 # Type of FU issued
+system.cpu.iq.rate 2.123628 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 24995598 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4959550302 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2638184259 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1953078988 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2035789802 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 217 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 63764603 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 136206849 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 286531 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 188011 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 43089501 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 136642278 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 284566 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 187935 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 43295180 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 117367 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 386993 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 65721634 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 20156212 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1080802 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2181156911 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 5548348 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 622133622 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 217936550 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1571 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 177848 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 42316 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 188011 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8591764 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 10177079 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18768843 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1980852010 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 570685009 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 29266609 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 66022772 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 23145640 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1044628 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2182779773 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 5713944 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 622569059 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 218142237 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 173655 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 44651 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 187935 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 8601247 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 10177350 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 18778597 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1981378382 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 570935022 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 29416039 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 81 # number of nop insts executed
-system.cpu.iew.exec_refs 761345389 # number of memory reference insts executed
-system.cpu.iew.exec_branches 237537296 # Number of branches executed
-system.cpu.iew.exec_stores 190660380 # Number of stores executed
-system.cpu.iew.exec_rate 2.180837 # Inst execution rate
-system.cpu.iew.wb_sent 1961817327 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1952804619 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1293399468 # num instructions producing a value
-system.cpu.iew.wb_consumers 2065182627 # num instructions consuming a value
+system.cpu.iew.exec_nop 103 # number of nop insts executed
+system.cpu.iew.exec_refs 761630934 # number of memory reference insts executed
+system.cpu.iew.exec_branches 237544754 # Number of branches executed
+system.cpu.iew.exec_stores 190695912 # Number of stores executed
+system.cpu.iew.exec_rate 2.092561 # Inst execution rate
+system.cpu.iew.wb_sent 1962075581 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1953079152 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1293757962 # num instructions producing a value
+system.cpu.iew.wb_consumers 2065123050 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.149958 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.626288 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.062674 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.626480 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 458146610 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16035536 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 836099887 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.060847 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.764107 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 459769347 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 182 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 16044351 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 842133415 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.046082 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.757625 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 346421369 41.43% 41.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 193942009 23.20% 64.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 73849330 8.83% 73.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35339477 4.23% 77.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18485791 2.21% 79.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30991807 3.71% 83.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 19654660 2.35% 85.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10738938 1.28% 87.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106676506 12.76% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 351966566 41.79% 41.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 194208080 23.06% 64.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 73932281 8.78% 73.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 35396184 4.20% 77.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 18675547 2.22% 80.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 31087553 3.69% 83.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 19760319 2.35% 86.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10744228 1.28% 87.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106362657 12.63% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 836099887 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 1544563061 # Number of instructions committed
-system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 842133415 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 1544563101 # Number of instructions committed
+system.cpu.commit.committedOps 1723073913 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 660773822 # Number of memory references committed
-system.cpu.commit.loads 485926773 # Number of loads committed
+system.cpu.commit.refs 660773838 # Number of memory references committed
+system.cpu.commit.loads 485926781 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
-system.cpu.commit.branches 213462430 # Number of branches committed
+system.cpu.commit.branches 213462438 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1536941889 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106676506 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106362657 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2910643265 # The number of ROB reads
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37166.666667 # average LoadLockedReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency
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-system.cpu.dcache.blocked_cycles::no_targets 306 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 59951 # number of cycles access was blocked
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-system.cpu.dcache.writebacks::total 3473179 # number of writebacks
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-system.cpu.dcache.WriteReq_mshr_hits::total 3281264 # number of WriteReq MSHR hits
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10.991234 # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1123907 # number of writebacks
-system.cpu.l2cache.writebacks::total 1123907 # number of writebacks
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208494 # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33643.777598 # average ReadReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131407022048 # number of overall MSHR miss cycles
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.042001 # Number of seconds simulated
-sim_ticks 42001440000 # Number of ticks simulated
-final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.041975 # Number of seconds simulated
+sim_ticks 41974805000 # Number of ticks simulated
+final_tick 41974805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 134131 # Simulator instruction rate (inst/s)
-host_op_rate 134131 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 61300636 # Simulator tick rate (ticks/s)
-host_mem_usage 216520 # Number of bytes of host memory used
-host_seconds 685.17 # Real time elapsed on the host
+host_inst_rate 82989 # Simulator instruction rate (inst/s)
+host_op_rate 82989 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37903288 # Simulator tick rate (ticks/s)
+host_mem_usage 220440 # Number of bytes of host memory used
+host_seconds 1107.42 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 4257378 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3266936 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 7524313 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 4257378 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 4257378 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 4257378 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3266936 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7524313 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 4260079 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3269009 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 7529088 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 4260079 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 4260079 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 4260079 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3269009 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7529088 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 4938 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 316032 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 349 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 313 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 229 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 290 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 250 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 283 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 352 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 383 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 306 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 254 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 283 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 313 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 363 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 356 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 332 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 41974753000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 4938 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 3879 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 789 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 235 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 15273921 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 109715921 # Sum of mem lat for all requests
+system.physmem.totBusLat 19752000 # Total cycles spent in databus access
+system.physmem.totBankLat 74690000 # Total cycles spent in bank access
+system.physmem.avgQLat 3093.14 # Average queueing delay per request
+system.physmem.avgBankLat 15125.56 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 22218.70 # Average memory access latency
+system.physmem.avgRdBW 7.53 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 7.53 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 4458 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 8500355.00 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26498155 # DTB accesses
-system.cpu.itb.fetch_hits 10035828 # ITB hits
+system.cpu.itb.fetch_hits 10035744 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 10035877 # ITB accesses
+system.cpu.itb.fetch_accesses 10035793 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.numCycles 84002881 # number of cpu cycles simulated
+system.cpu.numCycles 83949611 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 13564877 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 9782208 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 4497797 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 7992443 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 3850454 # Number of BTB hits
+system.cpu.branch_predictor.lookups 13564912 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 9782242 # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 4497823 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 7992579 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 3850502 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 48.176183 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 5999677 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 7565200 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 73745294 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct 48.175964 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 5999728 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 7565184 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 73745301 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 136320766 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 136320773 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 38528678 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 26769096 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 3520460 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 976479 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 4496939 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 5743763 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 43.912410 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 57470351 # Number of Instructions Executed.
+system.cpu.regfile_manager.regForwards 38528717 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 26769089 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 3520477 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 976488 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 4496965 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 5743737 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 43.912663 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 57470360 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 83639631 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 83639616 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 11378 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7720370 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 76282511 # Number of cycles cpu stages are processed.
-system.cpu.activity 90.809399 # Percentage of cycles cpu is active
+system.cpu.timesIdled 11375 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7667023 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 76282588 # Number of cycles cpu stages are processed.
+system.cpu.activity 90.867113 # Percentage of cycles cpu is active
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
-system.cpu.cpi 0.914038 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 0.913458 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 0.914038 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.094046 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 0.913458 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.094741 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 1.094046 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 27781439 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 56221442 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 66.927993 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 34555420 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 49447461 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 58.864006 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 34024816 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 1.094741 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 27728071 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 56221540 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 66.970578 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 34502106 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 49447505 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 58.901411 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 33971546 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 59.495656 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 65973303 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 18029578 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 21.463047 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 30058791 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 53944090 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 64.216952 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.utilization 59.533409 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 65920043 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 18029568 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 21.476655 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 30005535 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 53944076 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 64.257684 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 8127 # number of replacements
-system.cpu.icache.tagsinuse 1492.293343 # Cycle average of tags in use
-system.cpu.icache.total_refs 10024070 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1492.468291 # Cycle average of tags in use
+system.cpu.icache.total_refs 10023999 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 1001.205553 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1001.198462 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1492.293343 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.728659 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.728659 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 10024070 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 10024070 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 10024070 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 10024070 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 10024070 # number of overall hits
-system.cpu.icache.overall_hits::total 10024070 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 11754 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 11754 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 11754 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 11754 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 11754 # number of overall misses
-system.cpu.icache.overall_misses::total 11754 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 284626500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 284626500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 284626500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 284626500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 284626500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 284626500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 10035824 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 10035824 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 10035824 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 10035824 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 10035824 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 10035824 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24215.288412 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 24215.288412 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 24215.288412 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1492.468291 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.728744 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.728744 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 10023999 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 10023999 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 10023999 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 10023999 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 10023999 # number of overall hits
+system.cpu.icache.overall_hits::total 10023999 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 11743 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 11743 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 11743 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 11743 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 11743 # number of overall misses
+system.cpu.icache.overall_misses::total 11743 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 259067500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 259067500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 259067500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 259067500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 259067500 # number of overall miss cycles
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-system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23132500 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53471.546170 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54816.350711 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 53648.009950 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54944.831591 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54944.831591 # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17984000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42616.113744 # average ReadReq mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.023660 # Number of seconds simulated
-sim_ticks 23659827000 # Number of ticks simulated
-final_tick 23659827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.023631 # Number of seconds simulated
+sim_ticks 23630830000 # Number of ticks simulated
+final_tick 23630830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 188397 # Simulator instruction rate (inst/s)
-host_op_rate 188397 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52951506 # Simulator tick rate (ticks/s)
-host_mem_usage 217548 # Number of bytes of host memory used
-host_seconds 446.82 # Real time elapsed on the host
+host_inst_rate 120910 # Simulator instruction rate (inst/s)
+host_op_rate 120910 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33941778 # Simulator tick rate (ticks/s)
+host_mem_usage 221472 # Number of bytes of host memory used
+host_seconds 696.22 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
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+system.physmem.bytesWritten 0 # Total number of bytes written to memory
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+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
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+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 23669737 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 116101737 # Sum of mem lat for all requests
+system.physmem.totBusLat 20976000 # Total cycles spent in databus access
+system.physmem.totBankLat 71456000 # Total cycles spent in bank access
+system.physmem.avgQLat 4513.68 # Average queueing delay per request
+system.physmem.avgBankLat 13626.24 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 22139.92 # Average memory access latency
+system.physmem.avgRdBW 14.20 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 14.20 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.09 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 4702 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 4506243.71 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 23229098 # DTB read hits
-system.cpu.dtb.read_misses 198676 # DTB read misses
+system.cpu.dtb.read_hits 23223355 # DTB read hits
+system.cpu.dtb.read_misses 199967 # DTB read misses
system.cpu.dtb.read_acv 4 # DTB read access violations
-system.cpu.dtb.read_accesses 23427774 # DTB read accesses
-system.cpu.dtb.write_hits 7078776 # DTB write hits
-system.cpu.dtb.write_misses 1365 # DTB write misses
-system.cpu.dtb.write_acv 4 # DTB write access violations
-system.cpu.dtb.write_accesses 7080141 # DTB write accesses
-system.cpu.dtb.data_hits 30307874 # DTB hits
-system.cpu.dtb.data_misses 200041 # DTB misses
-system.cpu.dtb.data_acv 8 # DTB access violations
-system.cpu.dtb.data_accesses 30507915 # DTB accesses
-system.cpu.itb.fetch_hits 14959914 # ITB hits
-system.cpu.itb.fetch_misses 83 # ITB misses
+system.cpu.dtb.read_accesses 23423322 # DTB read accesses
+system.cpu.dtb.write_hits 7080030 # DTB write hits
+system.cpu.dtb.write_misses 1356 # DTB write misses
+system.cpu.dtb.write_acv 2 # DTB write access violations
+system.cpu.dtb.write_accesses 7081386 # DTB write accesses
+system.cpu.dtb.data_hits 30303385 # DTB hits
+system.cpu.dtb.data_misses 201323 # DTB misses
+system.cpu.dtb.data_acv 6 # DTB access violations
+system.cpu.dtb.data_accesses 30504708 # DTB accesses
+system.cpu.itb.fetch_hits 14954333 # ITB hits
+system.cpu.itb.fetch_misses 120 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 14959997 # ITB accesses
+system.cpu.itb.fetch_accesses 14954453 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.numCycles 47319655 # number of cpu cycles simulated
+system.cpu.numCycles 47261661 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15036576 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 10900203 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 965407 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 8822625 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7081383 # Number of BTB hits
+system.cpu.BPredUnit.lookups 15031497 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 10899201 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 964727 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 8732701 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 7076597 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1488044 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 3227 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 15623244 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 128299344 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15036576 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 8569427 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22397875 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4641617 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 5564099 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 1487345 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 3368 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 15614500 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 128263242 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 15031497 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 8563942 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22389896 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4636452 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 5551739 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1980 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 14959914 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 337946 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 47229880 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.716487 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.372485 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 2133 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 14954333 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 338853 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 47196510 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.717643 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.372831 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24832005 52.58% 52.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2392801 5.07% 57.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1209799 2.56% 60.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1776867 3.76% 63.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2804961 5.94% 69.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1173464 2.48% 72.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1230763 2.61% 75.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 789158 1.67% 76.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 11020062 23.33% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24806614 52.56% 52.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2389980 5.06% 57.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1210958 2.57% 60.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1776777 3.76% 63.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2802179 5.94% 69.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1172690 2.48% 72.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1230204 2.61% 74.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 789239 1.67% 76.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 11017869 23.34% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 47229880 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.317766 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.711333 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 17466031 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 4264969 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20777128 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1090965 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3630787 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2547167 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12222 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 125218187 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 32252 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3630787 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18637244 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 968362 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 8091 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 20675127 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 3310269 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 122217574 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 404537 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2431302 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 89737060 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 158727741 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 148984302 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 9743439 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 47196510 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.318048 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.713896 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 17460604 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 4250656 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20766421 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1092488 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3626341 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2544445 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12397 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 125174951 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 32088 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3626341 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 18627234 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 962190 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 8129 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 20670858 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 3301758 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 122185352 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 402329 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 2427096 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 89707747 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 158670699 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 148931458 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 9739241 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 21309699 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1072 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1080 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 8762996 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 25566964 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 8306109 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2633900 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 924738 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 106206807 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2480 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 97009064 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 188398 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21564802 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 16193043 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2091 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 47229880 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.053977 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.874944 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 21280386 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1002 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1014 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 8742077 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 25560713 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 8304198 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2649829 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 949216 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 106168633 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2274 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 96984807 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 186233 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21527282 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 16158700 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1885 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 47196510 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.054915 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.875207 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 12465875 26.39% 26.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 9434862 19.98% 46.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8477387 17.95% 64.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6321383 13.38% 77.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4949351 10.48% 88.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2846830 6.03% 94.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1724266 3.65% 97.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 801279 1.70% 99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 208647 0.44% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 12446961 26.37% 26.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 9431395 19.98% 46.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8468096 17.94% 64.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6320682 13.39% 77.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4944837 10.48% 88.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2848295 6.03% 94.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1728522 3.66% 97.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 798557 1.69% 99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 209165 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 47229880 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 47196510 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 189791 12.08% 12.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 12.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 12.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 221 0.01% 12.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 7127 0.45% 12.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 5711 0.36% 12.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 843066 53.68% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 445505 28.36% 94.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 79246 5.05% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 189157 12.05% 12.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 12.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 12.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 237 0.02% 12.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 7151 0.46% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 5547 0.35% 12.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 843237 53.72% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 445222 28.36% 94.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 79100 5.04% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59007350 60.83% 60.83% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 480907 0.50% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58989351 60.82% 60.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 480619 0.50% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2801835 2.89% 64.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 115568 0.12% 64.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2386144 2.46% 66.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 311424 0.32% 67.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 759643 0.78% 67.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2802202 2.89% 64.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 115471 0.12% 64.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2386536 2.46% 66.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 311369 0.32% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 759928 0.78% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 23975074 24.71% 92.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 7170793 7.39% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 23967188 24.71% 92.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 7171817 7.39% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 97009064 # Type of FU issued
-system.cpu.iq.rate 2.050080 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1570667 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.016191 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 227877046 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 118983933 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87385352 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 15130027 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 8824854 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 7067767 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 90585387 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 7994337 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1520935 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 96984807 # Type of FU issued
+system.cpu.iq.rate 2.052082 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1569651 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.016185 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 227791870 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 118912637 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87370988 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 15130138 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 8820177 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 7068200 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 90559677 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 7994774 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1518774 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5570766 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 20063 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 34811 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1805006 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 5564515 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 19809 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 34734 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1803095 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 10523 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 10505 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3630787 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 133855 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 17474 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 116506957 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 391259 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 25566964 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 8306109 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2480 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3139 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 34811 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 570809 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 508196 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1079005 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 95710462 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 23428475 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1298602 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3626341 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 131070 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 17619 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 116470742 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 396615 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 25560713 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 8304198 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2274 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 3005 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 34734 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 570082 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 507540 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1077622 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 95693120 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 23424012 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1291687 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 10297670 # number of nop insts executed
-system.cpu.iew.exec_refs 30508815 # number of memory reference insts executed
-system.cpu.iew.exec_branches 12080088 # Number of branches executed
-system.cpu.iew.exec_stores 7080340 # Number of stores executed
-system.cpu.iew.exec_rate 2.022637 # Inst execution rate
-system.cpu.iew.wb_sent 94996847 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 94453119 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 64630172 # num instructions producing a value
-system.cpu.iew.wb_consumers 90018458 # num instructions consuming a value
+system.cpu.iew.exec_nop 10299835 # number of nop insts executed
+system.cpu.iew.exec_refs 30505591 # number of memory reference insts executed
+system.cpu.iew.exec_branches 12076727 # Number of branches executed
+system.cpu.iew.exec_stores 7081579 # Number of stores executed
+system.cpu.iew.exec_rate 2.024752 # Inst execution rate
+system.cpu.iew.wb_sent 94981894 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 94439188 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 64622529 # num instructions producing a value
+system.cpu.iew.wb_consumers 90009959 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.996065 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.998220 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.717949 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24605076 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 24568706 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 953560 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 43599093 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.107912 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.734433 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 952874 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 43570169 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.109311 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.735421 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 17053308 39.11% 39.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 9978024 22.89% 62.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4508053 10.34% 72.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2287531 5.25% 77.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1622514 3.72% 81.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1125878 2.58% 83.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 721380 1.65% 85.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 820634 1.88% 87.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5481771 12.57% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 17034200 39.10% 39.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 9970297 22.88% 61.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4508116 10.35% 72.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2285317 5.25% 77.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1618875 3.72% 81.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1127711 2.59% 83.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 720325 1.65% 85.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 818054 1.88% 87.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5487274 12.59% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 43599093 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 43570169 # Number of insts commited each cycle
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5481771 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5487274 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 154624413 # The number of ROB reads
-system.cpu.rob.rob_writes 236671244 # The number of ROB writes
-system.cpu.timesIdled 1995 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 89775 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 154553616 # The number of ROB reads
+system.cpu.rob.rob_writes 236594431 # The number of ROB writes
+system.cpu.timesIdled 1889 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 65151 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
-system.cpu.cpi 0.562127 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.562127 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.778959 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.778959 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 129495815 # number of integer regfile reads
-system.cpu.int_regfile_writes 70794338 # number of integer regfile writes
-system.cpu.fp_regfile_reads 6191717 # number of floating regfile reads
-system.cpu.fp_regfile_writes 6049387 # number of floating regfile writes
-system.cpu.misc_regfile_reads 714327 # number of misc regfile reads
+system.cpu.cpi 0.561438 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.561438 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.781142 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.781142 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 129470706 # number of integer regfile reads
+system.cpu.int_regfile_writes 70779763 # number of integer regfile writes
+system.cpu.fp_regfile_reads 6192026 # number of floating regfile reads
+system.cpu.fp_regfile_writes 6049557 # number of floating regfile writes
+system.cpu.misc_regfile_reads 714457 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 10388 # number of replacements
-system.cpu.icache.tagsinuse 1605.369069 # Cycle average of tags in use
-system.cpu.icache.total_refs 14946221 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 12326 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 1212.576748 # Average number of references to valid blocks.
+system.cpu.icache.replacements 10301 # number of replacements
+system.cpu.icache.tagsinuse 1602.585562 # Cycle average of tags in use
+system.cpu.icache.total_refs 14940827 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 12238 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 1220.855287 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1605.369069 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.783872 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.783872 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 14946221 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 14946221 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 14946221 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 14946221 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 14946221 # number of overall hits
-system.cpu.icache.overall_hits::total 14946221 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 13693 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 13693 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 13693 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 13693 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 13693 # number of overall misses
-system.cpu.icache.overall_misses::total 13693 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 189030000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 189030000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 189030000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 189030000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 189030000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 189030000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 14959914 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 14959914 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 14959914 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 14959914 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 14959914 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 14959914 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000915 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.000915 # miss rate for demand accesses
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+system.cpu.l2cache.demand_avg_miss_latency::total 29843.154081 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 27645.197923 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 32976.410731 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 29843.154081 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 43 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 21.500000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3088 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 3546 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1705 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1705 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3088 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 5251 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3088 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 5251 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 99150000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16063500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 115213500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61053000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61053000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 99150000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77116500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 176266500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 99150000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77116500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 176266500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.276211 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.360423 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.360423 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32108.160622 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35073.144105 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32491.116751 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35808.211144 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35808.211144 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32108.160622 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35652.565881 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33568.177490 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32108.160622 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35652.565881 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33568.177490 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3082 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 455 # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_misses::total 1707 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3082 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2162 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 5244 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3082 # number of overall MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15695119 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64284384 # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74145562 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64284384 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 138429946 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251839 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893910 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.277477 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985566 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985566 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251839 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964748 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.362180 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251839 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964748 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.362180 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 24057.612589 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34494.767033 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 25400.249081 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28464.712947 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28464.712947 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 24057.612589 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29733.757632 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 26397.777651 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 24057.612589 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29733.757632 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 26397.777651 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.075929 # Number of seconds simulated
-sim_ticks 75929256000 # Number of ticks simulated
-final_tick 75929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.075917 # Number of seconds simulated
+sim_ticks 75916922000 # Number of ticks simulated
+final_tick 75916922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 126863 # Simulator instruction rate (inst/s)
-host_op_rate 138901 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 55895176 # Simulator tick rate (ticks/s)
-host_mem_usage 231880 # Number of bytes of host memory used
-host_seconds 1358.42 # Real time elapsed on the host
-sim_insts 172333091 # Number of instructions simulated
-sim_ops 188686573 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 132864 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 112384 # Number of bytes read from this memory
-system.physmem.bytes_read::total 245248 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 132864 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 132864 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2076 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1756 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3832 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1749839 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1480115 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3229954 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1749839 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1749839 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1749839 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1480115 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3229954 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 139176 # Simulator instruction rate (inst/s)
+host_op_rate 152383 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61310301 # Simulator tick rate (ticks/s)
+host_mem_usage 236468 # Number of bytes of host memory used
+host_seconds 1238.24 # Real time elapsed on the host
+sim_insts 172333316 # Number of instructions simulated
+sim_ops 188686798 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 112320 # Number of bytes read from this memory
+system.physmem.bytes_read::total 245056 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1755 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3829 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1748438 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1479512 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3227950 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1748438 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1748438 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1748438 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1479512 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3227950 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 3829 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 245056 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 245056 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 239 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 195 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 283 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 245 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 265 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 250 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 240 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 75916775000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 3829 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 2774 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 838 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 153 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 12309321 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 87055321 # Sum of mem lat for all requests
+system.physmem.totBusLat 15316000 # Total cycles spent in databus access
+system.physmem.totBankLat 59430000 # Total cycles spent in bank access
+system.physmem.avgQLat 3214.76 # Average queueing delay per request
+system.physmem.avgBankLat 15521.02 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 22735.79 # Average memory access latency
+system.physmem.avgRdBW 3.23 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 3.23 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 3315 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.58 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 19826788.98 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 151858513 # number of cpu cycles simulated
+system.cpu.numCycles 151833845 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 96795637 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 76023233 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 6554345 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 46458722 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 44211681 # Number of BTB hits
+system.cpu.BPredUnit.lookups 96840599 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 76060531 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 6557597 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 46497854 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 44230275 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 4476295 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 89485 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 40599440 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 388212036 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 96795637 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 48687976 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 82231847 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 28434690 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7095448 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 8914 # Number of stall cycles due to pending traps
+system.cpu.BPredUnit.usedRAS 4471070 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 89483 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 40605581 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 388281645 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 96840599 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 48701345 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 82243787 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 28438511 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 7066827 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 8646 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines 37656314 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1885789 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 151799953 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.799634 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.153355 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 37664937 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1885880 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 151789722 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.799994 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.153176 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 69738143 45.94% 45.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5498940 3.62% 49.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 10708649 7.05% 56.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10436622 6.88% 63.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8785452 5.79% 69.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 6828707 4.50% 73.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 6299043 4.15% 77.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8356617 5.51% 83.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 25147780 16.57% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 69716020 45.93% 45.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 5494868 3.62% 49.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 10713361 7.06% 56.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10448438 6.88% 63.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8787039 5.79% 69.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 6829673 4.50% 73.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 6296859 4.15% 77.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 8361926 5.51% 83.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 25141538 16.56% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151799953 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.637407 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.556406 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 46621790 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5807519 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 76550031 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1109408 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 21711205 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 14812709 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 162826 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 401248063 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 743977 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 21711205 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 52126095 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 710072 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 694282 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 72094443 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4463856 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 378978195 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 318341 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3575220 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 642418416 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1614444989 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1596851669 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 17593320 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 298092251 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 344326165 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 33370 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 33366 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12643089 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 43991113 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16880527 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 5791698 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3695359 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 334838724 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 55508 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 252834206 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 902162 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 144982237 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 373879643 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 4278 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151799953 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.665575 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.759908 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151789722 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.637806 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.557280 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 46630303 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5777884 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 76557243 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1112705 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 21711587 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 14823931 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 162890 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 401294311 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 730539 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 21711587 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 52135013 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 698137 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 692737 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 72105161 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4447087 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 379004822 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 318070 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3558685 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 642471315 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1614529203 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1596934770 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 17594433 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 298092611 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 344378704 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 33379 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 33376 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12572106 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 43979277 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16887724 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 5767479 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 3738298 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 334855562 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 55454 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 252836764 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 889769 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 145001031 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 373941866 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 4179 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151789722 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.665704 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.759623 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 58349265 38.44% 38.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 22992328 15.15% 53.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25145387 16.56% 70.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 20486668 13.50% 83.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12884605 8.49% 92.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 6585084 4.34% 96.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 4053755 2.67% 99.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1118158 0.74% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 184703 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 58337035 38.43% 38.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 22987248 15.14% 53.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25139726 16.56% 70.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 20501728 13.51% 83.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12883464 8.49% 92.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 6586273 4.34% 96.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4061259 2.68% 99.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1111807 0.73% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 181182 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151799953 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151789722 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 967156 37.45% 37.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5599 0.22% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 95 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1198375 46.40% 84.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 411308 15.93% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 964155 37.62% 37.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5594 0.22% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 1 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 24 0.00% 37.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1191140 46.48% 84.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 401719 15.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 197345283 78.05% 78.05% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 996010 0.39% 78.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 197361954 78.06% 78.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 995375 0.39% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 33191 0.01% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 164019 0.06% 78.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 254959 0.10% 78.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 76456 0.03% 78.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 467688 0.18% 78.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 206418 0.08% 78.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 71860 0.03% 78.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 78.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 39024792 15.43% 94.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 14193209 5.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 33153 0.01% 78.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 164117 0.06% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 255226 0.10% 78.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 76451 0.03% 78.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 467799 0.19% 78.85% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 206454 0.08% 78.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 71861 0.03% 78.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 78.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 39017631 15.43% 94.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 14186422 5.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 252834206 # Type of FU issued
-system.cpu.iq.rate 1.664933 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2582566 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010214 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 657177755 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 477646556 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 240591983 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3775338 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2248788 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1851684 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 253520354 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1896418 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2029780 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 252836764 # Type of FU issued
+system.cpu.iq.rate 1.665220 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2562727 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010136 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 657141484 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 477682512 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 240592268 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3774262 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2248392 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1852132 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 253504217 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1895274 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2034571 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 14135615 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 17349 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 19653 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 4229879 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 14123734 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 16793 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 19636 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 4237031 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 21711205 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 12896 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 616 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 334912035 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 838129 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 43991113 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16880527 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 32938 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles 21711587 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 4884 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 553 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 334928786 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 838607 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 43979277 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16887724 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 32914 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 266 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 19653 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4103971 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3924992 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8028963 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 245839126 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 37402304 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6995080 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewLSQFullEvents 218 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 19636 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4106046 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3927041 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8033087 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 245835770 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 37393574 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 7000994 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 17803 # number of nop insts executed
-system.cpu.iew.exec_refs 51215601 # number of memory reference insts executed
-system.cpu.iew.exec_branches 54034095 # Number of branches executed
-system.cpu.iew.exec_stores 13813297 # Number of stores executed
-system.cpu.iew.exec_rate 1.618870 # Inst execution rate
-system.cpu.iew.wb_sent 243576806 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 242443667 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 150073604 # num instructions producing a value
-system.cpu.iew.wb_consumers 269189037 # num instructions consuming a value
+system.cpu.iew.exec_nop 17770 # number of nop insts executed
+system.cpu.iew.exec_refs 51200144 # number of memory reference insts executed
+system.cpu.iew.exec_branches 54041718 # Number of branches executed
+system.cpu.iew.exec_stores 13806570 # Number of stores executed
+system.cpu.iew.exec_rate 1.619110 # Inst execution rate
+system.cpu.iew.wb_sent 243578722 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 242444400 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 150079170 # num instructions producing a value
+system.cpu.iew.wb_consumers 269183647 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.596510 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.557503 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.596774 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.557534 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 146211047 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 51230 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 6401258 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 130088749 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.450556 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.162504 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 146227575 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 51275 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 6404316 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 130078136 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.450676 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.162324 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 59880842 46.03% 46.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 32046581 24.63% 70.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13987597 10.75% 81.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 7657894 5.89% 87.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4414755 3.39% 90.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1334314 1.03% 91.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1737378 1.34% 93.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1284458 0.99% 94.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 7744930 5.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 59851320 46.01% 46.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 32072665 24.66% 70.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13982527 10.75% 81.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 7658050 5.89% 87.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4412794 3.39% 90.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1335206 1.03% 91.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1737015 1.34% 93.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1288451 0.99% 94.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 7740108 5.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 130088749 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 172347479 # Number of instructions committed
-system.cpu.commit.committedOps 188700961 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 130078136 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 172347704 # Number of instructions committed
+system.cpu.commit.committedOps 188701186 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 42506146 # Number of memory references committed
-system.cpu.commit.loads 29855498 # Number of loads committed
+system.cpu.commit.refs 42506236 # Number of memory references committed
+system.cpu.commit.loads 29855543 # Number of loads committed
system.cpu.commit.membars 22408 # Number of memory barriers committed
-system.cpu.commit.branches 40306325 # Number of branches committed
+system.cpu.commit.branches 40306370 # Number of branches committed
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 150130273 # Number of committed integer instructions.
+system.cpu.commit.int_insts 150130453 # Number of committed integer instructions.
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 7744930 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 7740108 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 457250626 # The number of ROB reads
-system.cpu.rob.rob_writes 691654263 # The number of ROB writes
-system.cpu.timesIdled 1589 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 58560 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 172333091 # Number of Instructions Simulated
-system.cpu.committedOps 188686573 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 172333091 # Number of Instructions Simulated
-system.cpu.cpi 0.881192 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.881192 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.134827 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.134827 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1091994433 # number of integer regfile reads
-system.cpu.int_regfile_writes 388620965 # number of integer regfile writes
-system.cpu.fp_regfile_reads 2912840 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2511233 # number of floating regfile writes
-system.cpu.misc_regfile_reads 474441039 # number of misc regfile reads
-system.cpu.misc_regfile_writes 832064 # number of misc regfile writes
-system.cpu.icache.replacements 2657 # number of replacements
-system.cpu.icache.tagsinuse 1370.154308 # Cycle average of tags in use
-system.cpu.icache.total_refs 37651093 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 4401 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 8555.122245 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 457261588 # The number of ROB reads
+system.cpu.rob.rob_writes 691688263 # The number of ROB writes
+system.cpu.timesIdled 1182 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 44123 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 172333316 # Number of Instructions Simulated
+system.cpu.committedOps 188686798 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 172333316 # Number of Instructions Simulated
+system.cpu.cpi 0.881048 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.881048 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.135013 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.135013 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1091959933 # number of integer regfile reads
+system.cpu.int_regfile_writes 388658885 # number of integer regfile writes
+system.cpu.fp_regfile_reads 2913610 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2511674 # number of floating regfile writes
+system.cpu.misc_regfile_reads 474503072 # number of misc regfile reads
+system.cpu.misc_regfile_writes 832154 # number of misc regfile writes
+system.cpu.icache.replacements 2619 # number of replacements
+system.cpu.icache.tagsinuse 1372.300046 # Cycle average of tags in use
+system.cpu.icache.total_refs 37659845 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 4361 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 8635.598487 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1370.154308 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.669021 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.669021 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 37651093 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 37651093 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 37651093 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 37651093 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 37651093 # number of overall hits
-system.cpu.icache.overall_hits::total 37651093 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 5221 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 5221 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 5221 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 5221 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 5221 # number of overall misses
-system.cpu.icache.overall_misses::total 5221 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 109554000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 109554000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 109554000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 109554000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 109554000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 109554000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 37656314 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 37656314 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 37656314 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 37656314 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 37656314 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 37656314 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000139 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000139 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000139 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000139 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000139 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000139 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20983.336526 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20983.336526 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20983.336526 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20983.336526 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20983.336526 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20983.336526 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1372.300046 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.670068 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.670068 # Average percentage of cache occupancy
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+system.cpu.icache.ReadReq_hits::total 37659851 # number of ReadReq hits
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system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
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+system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2074 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 680 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 2754 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2076 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1756 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 3832 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2076 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1756 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 3832 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66628500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22957500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89586000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33945000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33945000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66628500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56902500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 123531000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66628500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56902500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 123531000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.471604 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870844 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.531829 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991697 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991697 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.471604 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941050 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.611359 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.471604 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941050 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.611359 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32094.653179 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33711.453744 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32494.015234 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31576.744186 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31576.744186 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32094.653179 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32404.612756 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32236.691023 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32094.653179 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32404.612756 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32236.691023 # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2074 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 3829 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2074 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 3829 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53338835 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19774493 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73113328 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 23276655 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 23276655 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53338835 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43051148 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 96389983 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53338835 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43051148 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 96389983 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866242 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.534965 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.614508 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.614508 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 25717.856798 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.136765 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 26548.049383 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 21652.702326 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 21652.702326 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.084599 # Number of seconds simulated
-sim_ticks 84599483500 # Number of ticks simulated
-final_tick 84599483500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.084594 # Number of seconds simulated
+sim_ticks 84594088000 # Number of ticks simulated
+final_tick 84594088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 50330 # Simulator instruction rate (inst/s)
-host_op_rate 84358 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32239425 # Simulator tick rate (ticks/s)
-host_mem_usage 239332 # Number of bytes of host memory used
-host_seconds 2624.10 # Real time elapsed on the host
+host_inst_rate 94248 # Simulator instruction rate (inst/s)
+host_op_rate 157968 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 60367706 # Simulator tick rate (ticks/s)
+host_mem_usage 238096 # Number of bytes of host memory used
+host_seconds 1401.31 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221362960 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 220032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 124672 # Number of bytes read from this memory
-system.physmem.bytes_read::total 344704 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 220032 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 220032 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3438 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1948 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5386 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2600867 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1473673 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4074540 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2600867 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2600867 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2600867 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1473673 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4074540 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 220544 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 124864 # Number of bytes read from this memory
+system.physmem.bytes_read::total 345408 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 220544 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 220544 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3446 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1951 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5397 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2607085 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1476037 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4083122 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2607085 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2607085 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2607085 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1476037 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4083122 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5399 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 5664 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 345408 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 345408 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 265 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 319 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 313 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 372 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 333 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 312 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 261 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 363 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 438 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 441 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 367 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 298 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 84594067000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 5399 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 265 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 4217 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 41 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 16379877 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 123109877 # Sum of mem lat for all requests
+system.physmem.totBusLat 21596000 # Total cycles spent in databus access
+system.physmem.totBankLat 85134000 # Total cycles spent in bank access
+system.physmem.avgQLat 3033.87 # Average queueing delay per request
+system.physmem.avgBankLat 15768.48 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 22802.35 # Average memory access latency
+system.physmem.avgRdBW 4.08 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 4.08 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 4777 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 88.48 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 15668469.53 # Average gap between requests
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 169198968 # number of cpu cycles simulated
+system.cpu.numCycles 169188177 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 20690463 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 20690463 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2250102 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 15079710 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 13739283 # Number of BTB hits
+system.cpu.BPredUnit.lookups 20680258 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 20680258 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 2246160 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 15085015 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 13721428 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 27218141 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 227440359 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 20690463 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 13739283 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 59726319 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 19306281 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 65395131 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 224 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1651 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 25701311 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 473765 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 169122323 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.213301 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.334482 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27164568 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 227213982 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 20680258 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 13721428 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 59660749 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 19257155 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 65568957 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 236 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1768 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 25653013 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 474244 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 169131808 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.211225 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.333765 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 111062519 65.67% 65.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3230504 1.91% 67.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2469579 1.46% 69.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 3091757 1.83% 70.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 3527779 2.09% 72.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 3730060 2.21% 75.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4582508 2.71% 77.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2803800 1.66% 79.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 34623817 20.47% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 111136116 65.71% 65.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3216747 1.90% 67.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2468197 1.46% 69.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3082745 1.82% 70.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 3525528 2.08% 72.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 3731818 2.21% 75.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4565922 2.70% 77.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2807540 1.66% 79.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 34597195 20.46% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 169122323 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.122285 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.344218 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 40123368 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 55633776 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 46741593 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9842729 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 16780857 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 365282924 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 16780857 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 47679812 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 14629061 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 22937 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 48366453 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 41643203 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 356095908 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 17377193 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 22149388 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 410376112 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 987879370 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 977929387 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 9949983 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 169131808 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.122232 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.342966 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 40083092 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 55790408 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 46646195 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9876583 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 16735530 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 364948187 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 16735530 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 47642140 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 14699446 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 23267 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 48304644 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 41726781 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 355757826 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 35 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 17417112 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 22198638 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 410011414 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 986948203 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 977030227 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 9917976 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 150947509 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1877 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1873 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 89979833 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 89683170 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 32866708 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 59054771 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 19177166 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 343137266 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 5038 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 271920674 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 307949 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 121254430 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 247003349 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3792 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 169122323 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.607834 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.514763 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 150582811 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1844 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1841 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 90083407 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 89641616 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 32814586 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 59002795 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 19228439 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 342836678 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4827 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 271794183 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 309279 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 120959244 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 246380396 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3581 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 169131808 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.606996 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.512238 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 47444811 28.05% 28.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 46907027 27.74% 55.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 33033517 19.53% 75.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 20154930 11.92% 87.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 13461767 7.96% 95.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4965301 2.94% 98.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2426983 1.44% 99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 577544 0.34% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 150443 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 47364329 28.00% 28.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 46969212 27.77% 55.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 33133132 19.59% 75.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 20170100 11.93% 87.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 13409099 7.93% 95.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4965437 2.94% 98.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2407480 1.42% 99.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 564206 0.33% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 148813 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 169122323 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 169131808 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 134207 5.09% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2238473 84.87% 89.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 264949 10.04% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 133221 5.02% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2254463 85.01% 90.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 264273 9.97% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 1212573 0.45% 0.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 177106081 65.13% 65.58% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1583088 0.58% 66.16% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 1212759 0.45% 0.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 177009113 65.13% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 1584136 0.58% 66.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 68507215 25.19% 91.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 23511717 8.65% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 68507132 25.21% 91.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 23481043 8.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 271920674 # Type of FU issued
-system.cpu.iq.rate 1.607106 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2637629 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.009700 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 710614385 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 460072874 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 264170911 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 5294864 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 4624558 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2540762 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 270691856 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 2653874 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 19027871 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 271794183 # Type of FU issued
+system.cpu.iq.rate 1.606461 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2651957 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.009757 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 710390564 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 459507075 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 264054683 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 5290846 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 4594594 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 2539782 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 270581714 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 2651667 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 19012084 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 33033584 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 33172 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 306303 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 12350992 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 32992030 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 32876 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 306652 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 12298870 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 49574 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 49471 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 16780857 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 570141 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 256886 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 343142304 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 262882 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 89683170 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 32866708 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1845 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 170649 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 30071 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 306303 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1331965 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1023841 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2355806 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 268743201 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 67386869 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3177473 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 16735530 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 583808 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 272322 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 342841505 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 257255 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 89641616 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 32814586 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1824 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 184475 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 30365 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 306652 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1330858 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1021453 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 2352311 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 268621044 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 67379328 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3173139 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 90490770 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14773340 # Number of branches executed
-system.cpu.iew.exec_stores 23103901 # Number of stores executed
-system.cpu.iew.exec_rate 1.588326 # Inst execution rate
-system.cpu.iew.wb_sent 267665043 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 266711673 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 215305025 # num instructions producing a value
-system.cpu.iew.wb_consumers 378544002 # num instructions consuming a value
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+system.cpu.iew.exec_rate 1.587706 # Inst execution rate
+system.cpu.iew.wb_sent 267534302 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 266594465 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 215217179 # num instructions producing a value
+system.cpu.iew.wb_consumers 378376353 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.576320 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.568771 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.575728 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.568791 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 121862932 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 121559121 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2250269 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 152341466 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.453071 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.928588 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 2246323 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 1.452548 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.926116 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 52729760 34.61% 34.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 57497101 37.74% 72.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 14043120 9.22% 81.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11929275 7.83% 89.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4291590 2.82% 92.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2949185 1.94% 94.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1071112 0.70% 94.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 989747 0.65% 95.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6840576 4.49% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 52678390 34.57% 34.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 57577424 37.78% 72.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 14059718 9.23% 81.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11956991 7.85% 89.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4305123 2.82% 92.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2949818 1.94% 94.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1066386 0.70% 94.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 992195 0.65% 95.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6810233 4.47% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 152341466 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 152396278 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 220339549 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 6840576 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6810233 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 488726782 # The number of ROB reads
-system.cpu.rob.rob_writes 703273689 # The number of ROB writes
-system.cpu.timesIdled 1665 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 76645 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 488508126 # The number of ROB reads
+system.cpu.rob.rob_writes 702620216 # The number of ROB writes
+system.cpu.timesIdled 1506 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 56369 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
-system.cpu.cpi 1.281119 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.281119 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.780567 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.780567 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 567776084 # number of integer regfile reads
-system.cpu.int_regfile_writes 302793169 # number of integer regfile writes
-system.cpu.fp_regfile_reads 3492670 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2212557 # number of floating regfile writes
-system.cpu.misc_regfile_reads 139469476 # number of misc regfile reads
+system.cpu.cpi 1.281038 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.281038 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.780617 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.780617 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 567639196 # number of integer regfile reads
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+system.cpu.fp_regfile_writes 2211250 # number of floating regfile writes
+system.cpu.misc_regfile_reads 139399302 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
-system.cpu.icache.replacements 5445 # number of replacements
-system.cpu.icache.tagsinuse 1641.882453 # Cycle average of tags in use
-system.cpu.icache.total_refs 25692314 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 7414 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 3465.378203 # Average number of references to valid blocks.
+system.cpu.icache.replacements 5641 # number of replacements
+system.cpu.icache.tagsinuse 1641.401127 # Cycle average of tags in use
+system.cpu.icache.total_refs 25643925 # Total number of references to valid blocks.
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+system.cpu.icache.avg_refs 3368.881372 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1641.882453 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.801700 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.801700 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 25692314 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 25692314 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 25692314 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 25692314 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 25692314 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 8997 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 8997 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 8997 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 8997 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 180939500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 180939500 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 180939500 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 180939500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 25701311 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 25701311 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses::total 25701311 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000350 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000350 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000350 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000350 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000350 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000350 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20111.092586 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20111.092586 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20111.092586 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20111.092586 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1641.401127 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.801465 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.801465 # Average percentage of cache occupancy
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+system.cpu.icache.overall_hits::total 25643925 # number of overall hits
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+system.cpu.icache.ReadReq_misses::total 9088 # number of ReadReq misses
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+system.cpu.icache.overall_misses::total 9088 # number of overall misses
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+system.cpu.icache.overall_miss_latency::total 147639500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 25653013 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 25653013 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 25653013 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 25653013 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 25653013 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000354 # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16245.543574 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16245.543574 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16245.543574 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16245.543574 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1358 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1358 # number of ReadReq MSHR hits
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-system.cpu.icache.demand_mshr_hits::total 1358 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 1358 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7639 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 7639 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 7639 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 7639 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 7639 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 7639 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 132852000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 132852000 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.452706 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.928241 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.478245 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994872 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.452706 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980422 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.562162 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.452706 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980422 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.562162 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 24764.514510 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38259.628429 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 26171.205615 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 21214.230670 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 21214.230670 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 24764.514510 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 24714.079365 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 24764.514510 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24714.079365 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 1870325497500 # Number of ticks simulated
final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2529303 # Simulator instruction rate (inst/s)
-host_op_rate 2529302 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 74909435310 # Simulator tick rate (ticks/s)
-host_mem_usage 298360 # Number of bytes of host memory used
-host_seconds 24.97 # Real time elapsed on the host
+host_inst_rate 1528286 # Simulator instruction rate (inst/s)
+host_op_rate 1528286 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 45262701867 # Simulator tick rate (ticks/s)
+host_mem_usage 296828 # Number of bytes of host memory used
+host_seconds 41.32 # Real time elapsed on the host
sim_insts 63151114 # Number of instructions simulated
sim_ops 63151114 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory
system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 0 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 0 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 0 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 0 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 0 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
+system.physmem.totBusLat 0 # Total cycles spent in databus access
+system.physmem.totBankLat 0 # Total cycles spent in bank access
+system.physmem.avgQLat nan # Average queueing delay per request
+system.physmem.avgBankLat nan # Average bank access latency per request
+system.physmem.avgBusLat nan # Average bus latency per request
+system.physmem.avgMemAccLat nan # Average memory access latency
+system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.00 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 0 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate nan # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap nan # Average gap between requests
system.l2c.replacements 1000406 # number of replacements
-system.l2c.tagsinuse 65381.817479 # Cycle average of tags in use
-system.l2c.total_refs 2465974 # Total number of references to valid blocks.
+system.l2c.tagsinuse 65381.817483 # Cycle average of tags in use
+system.l2c.total_refs 2465980 # Total number of references to valid blocks.
system.l2c.sampled_refs 1065550 # Sample count of references to valid blocks.
-system.l2c.avg_refs 2.314273 # Average number of references to valid blocks.
+system.l2c.avg_refs 2.314279 # Average number of references to valid blocks.
system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 56158.126687 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4894.240577 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 4135.004263 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 174.436812 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 56158.126694 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4894.240575 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 4135.004261 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 174.436811 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 20.009142 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.856905 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.997647 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 872724 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 763058 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 763064 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 102911 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 36889 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1775582 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1775588 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 816811 # number of Writeback hits
system.l2c.Writeback_hits::total 816811 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 138 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu1.data 14300 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 180734 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 872724 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 929492 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 929498 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 102911 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 51189 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1956316 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1956322 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 872724 # number of overall hits
-system.l2c.overall_hits::cpu0.data 929492 # number of overall hits
+system.l2c.overall_hits::cpu0.data 929498 # number of overall hits
system.l2c.overall_hits::cpu1.inst 102911 # number of overall hits
system.l2c.overall_hits::cpu1.data 51189 # number of overall hits
-system.l2c.overall_hits::total 1956316 # number of overall hits
+system.l2c.overall_hits::total 1956322 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 11889 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 926770 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 1737 # number of ReadReq misses
system.l2c.overall_misses::cpu1.data 10780 # number of overall misses
system.l2c.overall_misses::total 1066458 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.inst 884613 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 1689828 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 1689834 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 104648 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 37807 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2716896 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2716902 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 816811 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 816811 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2579 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 24162 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 305878 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 884613 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 1971544 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 1971550 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 104648 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 61969 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3022774 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 3022780 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 884613 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 1971544 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 1971550 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 104648 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 61969 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3022774 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 3022780 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.548440 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.548438 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.346467 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.346466 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.528546 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.528545 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.352808 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.352807 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.528546 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.528545 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.352808 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.352807 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.num_mem_refs 15124548 # number of memory refs
system.cpu0.num_load_insts 9178366 # Number of load instructions
system.cpu0.num_store_insts 5946182 # Number of store instructions
-system.cpu0.num_idle_cycles 3683454679.572560 # Number of idle cycles
-system.cpu0.num_busy_cycles 57196203.427440 # Number of busy cycles
+system.cpu0.num_idle_cycles 3683454681.836560 # Number of idle cycles
+system.cpu0.num_busy_cycles 57196201.163440 # Number of busy cycles
system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 1978242 # number of replacements
+system.cpu0.dcache.replacements 1978248 # number of replacements
system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13113201 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 1978754 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 6.626999 # Average number of references to valid blocks.
+system.cpu0.dcache.total_refs 13113195 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 1978760 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 6.626976 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 7292600 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7292600 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu0.data 7292594 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 7292594 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 12750387 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12750387 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 12750387 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12750387 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 1683130 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1683130 # number of ReadReq misses
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+system.cpu0.dcache.overall_hits::total 12750381 # number of overall hits
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system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1968928 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1968928 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1968928 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1968928 # number of overall misses
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187520 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.187520 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187521 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.187521 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses
sim_ticks 1829330593000 # Number of ticks simulated
final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2569577 # Simulator instruction rate (inst/s)
-host_op_rate 2569575 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 78294086451 # Simulator tick rate (ticks/s)
-host_mem_usage 295292 # Number of bytes of host memory used
-host_seconds 23.37 # Real time elapsed on the host
+host_inst_rate 1577718 # Simulator instruction rate (inst/s)
+host_op_rate 1577717 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 48072530632 # Simulator tick rate (ticks/s)
+host_mem_usage 294780 # Number of bytes of host memory used
+host_seconds 38.05 # Real time elapsed on the host
sim_insts 60037737 # Number of instructions simulated
sim_ops 60037737 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 0 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 0 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 0 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 0 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 0 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
+system.physmem.totBusLat 0 # Total cycles spent in databus access
+system.physmem.totBankLat 0 # Total cycles spent in bank access
+system.physmem.avgQLat nan # Average queueing delay per request
+system.physmem.avgBankLat nan # Average bank access latency per request
+system.physmem.avgBusLat nan # Average bus latency per request
+system.physmem.avgMemAccLat nan # Average memory access latency
+system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.00 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 0 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate nan # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap nan # Average gap between requests
system.iocache.replacements 41686 # number of replacements
system.iocache.tagsinuse 1.225558 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.cpu.num_mem_refs 16115688 # number of memory refs
system.cpu.num_load_insts 9747503 # Number of load instructions
system.cpu.num_store_insts 6368185 # Number of store instructions
-system.cpu.num_idle_cycles 3598606247.544791 # Number of idle cycles
-system.cpu.num_busy_cycles 60054830.455209 # Number of busy cycles
+system.cpu.num_idle_cycles 3598606250.520791 # Number of idle cycles
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system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983586 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2042708 # number of replacements
+system.cpu.dcache.replacements 2042707 # number of replacements
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14038404 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2043220 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 6.870726 # Average number of references to valid blocks.
+system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7807768 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7807768 # number of ReadReq hits
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+system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
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-system.cpu.dcache.demand_hits::total 13655967 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 13655967 # number of overall hits
-system.cpu.dcache.overall_hits::total 13655967 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
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+system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses
-system.cpu.dcache.overall_misses::total 2026075 # number of overall misses
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system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 992297 # number of replacements
system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.301012 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 56309.097197 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 4867.351143 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 4247.927159 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
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system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits
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system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses
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system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses
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system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
---------- Begin Simulation Statistics ----------
-sim_seconds 1.955746 # Number of seconds simulated
-sim_ticks 1955746240500 # Number of ticks simulated
-final_tick 1955746240500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.950813 # Number of seconds simulated
+sim_ticks 1950813247500 # Number of ticks simulated
+final_tick 1950813247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1240365 # Simulator instruction rate (inst/s)
-host_op_rate 1240364 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39831169965 # Simulator tick rate (ticks/s)
-host_mem_usage 291792 # Number of bytes of host memory used
-host_seconds 49.10 # Real time elapsed on the host
-sim_insts 60902973 # Number of instructions simulated
-sim_ops 60902973 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 830080 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24726528 # Number of bytes read from this memory
+host_inst_rate 1287440 # Simulator instruction rate (inst/s)
+host_op_rate 1287440 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41184614921 # Simulator tick rate (ticks/s)
+host_mem_usage 325660 # Number of bytes of host memory used
+host_seconds 47.37 # Real time elapsed on the host
+sim_insts 60982794 # Number of instructions simulated
+sim_ops 60982794 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24727680 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 438464 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28681152 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 830080 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 865280 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7699072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7699072 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 12970 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 386352 # Number of read requests responded to by this memory
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+system.physmem.bytes_read::cpu1.data 439808 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28684096 # Number of bytes read from this memory
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+system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7706368 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7706368 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 386370 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 6851 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 448143 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 120298 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 120298 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 424431 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12643014 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1355431 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 17998 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 224193 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14665068 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 424431 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 17998 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 442430 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3936642 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3936642 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3936642 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 424431 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12643014 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1355431 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 17998 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 224193 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18601710 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 341281 # number of replacements
-system.l2c.tagsinuse 65229.882617 # Cycle average of tags in use
-system.l2c.total_refs 2441318 # Total number of references to valid blocks.
-system.l2c.sampled_refs 406256 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.009309 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 7648586000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 55341.365970 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4865.877793 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 4868.452553 # Average occupied blocks per requestor
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-system.l2c.occ_blocks::cpu1.data 38.024844 # Average occupied blocks per requestor
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-system.l2c.Writeback_accesses::writebacks 793334 # number of Writeback accesses(hits+misses)
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-system.l2c.ReadReq_miss_rate::cpu1.data 0.002235 # miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941552 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760262 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.864970 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.962244 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976009 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.969089 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.477072 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.122847 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.412517 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.018561 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.328608 # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.data 0.042121 # miss rate for demand accesses
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-system.l2c.overall_miss_rate::cpu0.inst 0.018561 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.328608 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.001771 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.042121 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.172916 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52378.141866 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52026.330807 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52375.222816 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52481.557377 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52043.394091 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 922.659430 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12670.590465 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 5284.601834 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2294.843049 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 582.681564 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 1437.325126 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52080.762903 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52447.412102 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52100.661715 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52060.554155 # average overall miss latency
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+system.physmem.num_reads::cpu1.data 6872 # Number of read requests responded to by this memory
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+system.physmem.num_writes::total 120412 # Number of write requests responded to by this memory
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+system.physmem.bw_read::cpu0.data 12675575 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu1.data 225449 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14703661 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::total 3950336 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::cpu1.data 225449 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 18653997 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 448189 # Total number of read requests seen
+system.physmem.writeReqs 120412 # Total number of write requests seen
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+system.physmem.bytesRead 28684096 # Total number of bytes read from memory
+system.physmem.bytesWritten 7706368 # Total number of bytes written to memory
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+system.physmem.neitherReadNorWrite 7172 # Reqs where no action is needed
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+system.physmem.totMemAccLat 10947900804 # Sum of mem lat for all requests
+system.physmem.totBusLat 1792528000 # Total cycles spent in databus access
+system.physmem.totBankLat 6289598000 # Total cycles spent in bank access
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+system.physmem.avgBankLat 14035.15 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 24430.08 # Average memory access latency
+system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s
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+system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.12 # Data bus utilization in percentage
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+system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes
+system.physmem.avgGap 3430805.67 # Average gap between requests
+system.l2c.replacements 341333 # number of replacements
+system.l2c.tagsinuse 65247.038846 # Cycle average of tags in use
+system.l2c.total_refs 2438074 # Total number of references to valid blocks.
+system.l2c.sampled_refs 406309 # Sample count of references to valid blocks.
+system.l2c.avg_refs 6.000541 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit.
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+system.l2c.occ_blocks::cpu1.data 43.456784 # Average occupied blocks per requestor
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-system.cpu0.num_busy_cycles 208986078.503285 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.053447 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.946553 # Percentage of idle cycles
+system.cpu0.committedInsts 47350752 # Number of instructions committed
+system.cpu0.committedOps 47350752 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 43919757 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses
+system.cpu0.num_func_calls 1188579 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 5567605 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 43919757 # number of integer instructions
+system.cpu0.num_fp_insts 206365 # number of float instructions
+system.cpu0.num_int_register_reads 60378447 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 32741783 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written
+system.cpu0.num_mem_refs 12475681 # number of memory refs
+system.cpu0.num_load_insts 7451619 # Number of load instructions
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+system.cpu0.num_busy_cycles 201491320.780943 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.051659 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.948341 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6789 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 164868 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 56806 40.18% 40.18% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1972 1.39% 41.67% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 420 0.30% 41.97% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 82040 58.03% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 141369 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 56268 49.08% 49.08% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1972 1.72% 50.92% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 420 0.37% 51.28% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 55848 48.72% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 114639 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1899887304000 97.18% 97.18% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 92906000 0.00% 97.18% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 760170500 0.04% 97.22% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 309335500 0.02% 97.24% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 54033794000 2.76% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1955083510000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.990529 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed
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+system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl
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+system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl
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+system.cpu0.kern.ipl_ticks::0 1898626830000 97.36% 97.36% # number of cycles we spent at this ipl
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+system.cpu0.kern.ipl_ticks::30 326793000 0.02% 97.42% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 50392837500 2.58% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1950199481000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.680741 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.810920 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 222 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
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-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3070 2.05% 2.39% # number of callpals executed
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-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed
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-system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
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+system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed
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system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 149688 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6889 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1285 # number of protection mode switches
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system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1285
-system.cpu0.kern.mode_good::user 1285
+system.cpu0.kern.mode_good::kernel 1283
+system.cpu0.kern.mode_good::user 1283
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.186529 # fraction of useful protection mode switches
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system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
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-system.cpu0.kern.mode_ticks::kernel 1951516113500 99.83% 99.83% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 3347061000 0.17% 100.00% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3071 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3025 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 698187 # number of replacements
-system.cpu0.icache.tagsinuse 508.830635 # Cycle average of tags in use
-system.cpu0.icache.total_refs 47028847 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 698699 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 67.309166 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 35739052000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 508.830635 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.993810 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.993810 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 47028847 # number of ReadReq hits
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 13872.743964 # average ReadReq miss latency
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-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13872.743964 # average overall miss latency
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+system.cpu0.icache.avg_refs 67.929207 # Average number of references to valid blocks.
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+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13938.126124 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses
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-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014641 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11872.743964 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30591.119165 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8845.138583 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8845.138583 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 10421.491389 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 10421.491389 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 672349 # number of writebacks
+system.cpu0.dcache.writebacks::total 672349 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933040 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 933040 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249280 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 249280 # number of WriteReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13436 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182320 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1182320 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182320 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1182320 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18954803000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18954803000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7263044000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7263044000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117630500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117630500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31985000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31985000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26217847000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 26217847000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26217847000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 26217847000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465453500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465453500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285524000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285524000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750977500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750977500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051328 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051328 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088494 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088494 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.097377 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.097377 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20315.102246 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20315.102246 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29136.087933 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29136.087933 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8754.874963 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8754.874963 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5581.050427 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5581.050427 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 2425080 # DTB read hits
+system.cpu1.dtb.read_hits 2500235 # DTB read hits
system.cpu1.dtb.read_misses 2992 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 239363 # DTB read accesses
-system.cpu1.dtb.write_hits 1761000 # DTB write hits
+system.cpu1.dtb.write_hits 1820988 # DTB write hits
system.cpu1.dtb.write_misses 341 # DTB write misses
system.cpu1.dtb.write_acv 29 # DTB write access violations
system.cpu1.dtb.write_accesses 105247 # DTB write accesses
-system.cpu1.dtb.data_hits 4186080 # DTB hits
+system.cpu1.dtb.data_hits 4321223 # DTB hits
system.cpu1.dtb.data_misses 3333 # DTB misses
system.cpu1.dtb.data_acv 29 # DTB access violations
system.cpu1.dtb.data_accesses 344610 # DTB accesses
-system.cpu1.itb.fetch_hits 1964871 # ITB hits
+system.cpu1.itb.fetch_hits 1990033 # ITB hits
system.cpu1.itb.fetch_misses 1216 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 1966087 # ITB accesses
+system.cpu1.itb.fetch_accesses 1991249 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3911492481 # number of cpu cycles simulated
+system.cpu1.numCycles 3901626495 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 13183934 # Number of instructions committed
-system.cpu1.committedOps 13183934 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 12160396 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 172922 # Number of float alu accesses
-system.cpu1.num_func_calls 412685 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1307407 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 12160396 # number of integer instructions
-system.cpu1.num_fp_insts 172922 # number of float instructions
-system.cpu1.num_int_register_reads 16740645 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 8924669 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 90471 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 92344 # number of times the floating registers were written
-system.cpu1.num_mem_refs 4209624 # number of memory refs
-system.cpu1.num_load_insts 2439377 # Number of load instructions
-system.cpu1.num_store_insts 1770247 # Number of store instructions
-system.cpu1.num_idle_cycles 3861803254.998025 # Number of idle cycles
-system.cpu1.num_busy_cycles 49689226.001975 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.012703 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.987297 # Percentage of idle cycles
+system.cpu1.committedInsts 13632042 # Number of instructions committed
+system.cpu1.committedOps 13632042 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 12571491 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses
+system.cpu1.num_func_calls 426717 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1355011 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 12571491 # number of integer instructions
+system.cpu1.num_fp_insts 180459 # number of float instructions
+system.cpu1.num_int_register_reads 17311598 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 9221787 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written
+system.cpu1.num_mem_refs 4345531 # number of memory refs
+system.cpu1.num_load_insts 2514982 # Number of load instructions
+system.cpu1.num_store_insts 1830549 # Number of store instructions
+system.cpu1.num_idle_cycles 3850258507.998026 # Number of idle cycles
+system.cpu1.num_busy_cycles 51367987.001974 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 78634 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 26575 38.36% 38.36% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1967 2.84% 41.20% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 503 0.73% 41.93% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 40225 58.07% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 69270 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 25736 48.16% 48.16% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 503 0.94% 52.78% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 25233 47.22% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 53439 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1909053778500 97.61% 97.61% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 705460500 0.04% 97.65% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 351339000 0.02% 97.67% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 45634904500 2.33% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1955745482500 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.968429 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1907138262500 97.76% 97.76% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 705201000 0.04% 97.80% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 364168000 0.02% 97.82% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 42604858000 2.18% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1950812489500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.627296 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.771460 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 104 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 420 0.59% 0.59% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1995 2.79% 3.38% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 63027 88.05% 91.44% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2168 3.03% 94.47% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 94.47% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.00% 94.48% # number of callpals executed
-system.cpu1.kern.callpal::rti 3772 5.27% 99.75% # number of callpals executed
-system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed
+system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed
+system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed
+system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed
+system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed
system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 71584 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 2065 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 891
-system.cpu1.kern.mode_good::user 464
-system.cpu1.kern.mode_good::idle 427
-system.cpu1.kern.mode_switch_good::kernel 0.431477 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 73828 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 2126 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 465 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2924 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 915
+system.cpu1.kern.mode_good::user 465
+system.cpu1.kern.mode_good::idle 450
+system.cpu1.kern.mode_switch_good::kernel 0.430386 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.148573 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.329817 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 17893399500 0.91% 0.91% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1709951500 0.09% 1.00% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1936142128000 99.00% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1996 # number of times the context was actually changed
-system.cpu1.icache.replacements 316204 # number of replacements
-system.cpu1.icache.tagsinuse 447.456269 # Cycle average of tags in use
-system.cpu1.icache.total_refs 12870545 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 316716 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 40.637495 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1953875803000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 447.456269 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.873938 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.873938 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 12870545 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 12870545 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 12870545 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 12870545 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 12870545 # number of overall hits
-system.cpu1.icache.overall_hits::total 12870545 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 316752 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 316752 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 316752 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 316752 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 316752 # number of overall misses
-system.cpu1.icache.overall_misses::total 316752 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4179857000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 4179857000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 4179857000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 4179857000 # number of demand (read+write) miss cycles
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-system.cpu1.icache.overall_miss_latency::total 4179857000 # number of overall miss cycles
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 13195.992448 # average ReadReq miss latency
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-system.cpu1.icache.demand_avg_miss_latency::total 13195.992448 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13195.992448 # average overall miss latency
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+system.cpu1.dcache.overall_miss_latency::cpu1.data 2659991500 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 2659991500 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452330 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 2452330 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763997 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 1763997 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59567 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 59567 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59070 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 59070 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 4216327 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 4216327 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 4216327 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 4216327 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050253 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.050253 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036709 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.036709 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156916 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156916 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103995 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103995 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044586 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.044586 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044586 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.044586 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12120.581648 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12120.581648 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.234827 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.234827 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.551514 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.551514 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7246.540778 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7246.540778 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14149.643598 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14149.643598 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 114265 # number of writebacks
-system.cpu1.dcache.writebacks::total 114265 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118301 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 118301 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62725 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 62725 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8915 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8915 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5846 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 5846 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 181026 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 181026 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 181026 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 181026 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203948500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203948500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 988115500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 988115500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63615500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63615500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57370000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57370000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2192064000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 2192064000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2192064000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 2192064000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713392500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713392500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732780000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732780000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049724 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049724 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036763 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036763 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155971 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155971 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103131 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103131 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.044311 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.044311 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10176.993432 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10176.993432 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15753.136708 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15753.136708 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.782389 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.782389 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9813.547725 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9813.547725 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 119115 # number of writebacks
+system.cpu1.dcache.writebacks::total 119115 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123236 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 123236 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64754 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 64754 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9347 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9347 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6143 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 6143 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 187990 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 187990 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 187990 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 187990 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247220000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247220000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1036791500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1036791500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66696000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66696000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32229500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32229500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284011500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2284011500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284011500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2284011500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723171500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723171500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742552500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742552500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050253 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050253 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036709 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036709 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156916 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156916 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103995 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103995 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.044586 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.044586 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10120.581648 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10120.581648 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.234827 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.234827 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.551514 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.551514 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5246.540778 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5246.540778 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 1.914421 # Number of seconds simulated
-sim_ticks 1914420945000 # Number of ticks simulated
-final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.910582 # Number of seconds simulated
+sim_ticks 1910582068000 # Number of ticks simulated
+final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1299276 # Simulator instruction rate (inst/s)
-host_op_rate 1299275 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44286723014 # Simulator tick rate (ticks/s)
-host_mem_usage 288696 # Number of bytes of host memory used
-host_seconds 43.23 # Real time elapsed on the host
-sim_insts 56164879 # Number of instructions simulated
-sim_ops 56164879 # Number of ops (including micro ops) simulated
+host_inst_rate 1092208 # Simulator instruction rate (inst/s)
+host_op_rate 1092208 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37180157619 # Simulator tick rate (ticks/s)
+host_mem_usage 321564 # Number of bytes of host memory used
+host_seconds 51.39 # Real time elapsed on the host
+sim_insts 56125446 # Number of instructions simulated
+sim_ops 56125446 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24860096 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28362752 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7404800 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7404800 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 7392192 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7392192 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388439 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 443168 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 115700 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 115700 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 444291 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12985700 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1385325 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14815316 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 444291 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 444291 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3867906 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3867906 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3867906 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 444291 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12985700 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1385325 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18683222 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 442975 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 115503 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 115503 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 445184 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13005193 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1388243 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14838619 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 445184 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 445184 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3869078 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3869078 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3869078 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 445184 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13005193 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1388243 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 18707698 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 442975 # Total number of read requests seen
+system.physmem.writeReqs 115503 # Total number of write requests seen
+system.physmem.cpureqs 559567 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28350400 # Total number of bytes read from memory
+system.physmem.bytesWritten 7392192 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28350400 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7392192 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 51 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28021 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 27576 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 27724 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 27399 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 28096 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27946 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27736 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27622 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 27577 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27238 # Track reads on a per bank basis
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system.iocache.replacements 41685 # number of replacements
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system.iocache.total_refs 0 # Total number of references to valid blocks.
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system.iocache.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
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system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
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system.cpu.dtb.read_accesses 728856 # DTB read accesses
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system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_accesses 291931 # DTB write accesses
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system.cpu.dtb.data_misses 11471 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020787 # DTB accesses
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system.cpu.itb.fetch_acv 184 # ITB acv
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system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3828841890 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_fp_insts 324393 # number of float instructions
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+system.cpu.num_int_register_reads 71242345 # number of times the integer registers were read
+system.cpu.num_int_register_writes 38476410 # number of times the integer registers were written
system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read
system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written
-system.cpu.num_mem_refs 15469580 # number of memory refs
-system.cpu.num_load_insts 9099291 # Number of load instructions
-system.cpu.num_store_insts 6370289 # Number of store instructions
-system.cpu.num_idle_cycles 3589214946.998125 # Number of idle cycles
-system.cpu.num_busy_cycles 239626943.001875 # Number of busy cycles
-system.cpu.not_idle_fraction 0.062585 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.937415 # Percentage of idle cycles
+system.cpu.num_mem_refs 15460271 # number of memory refs
+system.cpu.num_load_insts 9092827 # Number of load instructions
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+system.cpu.num_busy_cycles 233831871.001878 # Number of busy cycles
+system.cpu.not_idle_fraction 0.061194 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.938806 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211993 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74900 40.89% 40.89% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21 133 0.07% 40.96% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed
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+system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 106213 57.98% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73533 49.31% 49.31% # number of times we switched to this ipl from a different ipl
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+system.cpu.kern.ipl_count::31 106200 57.98% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 183153 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73534 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149130 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1856400078000 96.97% 96.97% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 92059500 0.00% 96.97% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 736279500 0.04% 97.01% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 57191794000 2.99% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1914420211000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
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+system.cpu.kern.ipl_ticks::0 1855918085500 97.14% 97.14% # number of cycles we spent at this ipl
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+system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl
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+system.cpu.kern.ipl_used::total 0.814134 # fraction of swpipl calls that actually changed the ipl
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system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
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-system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed
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system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
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-system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
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system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
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-system.cpu.kern.callpal::total 192901 # number of callpals executed
+system.cpu.kern.callpal::total 192878 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1910
-system.cpu.kern.mode_good::user 1740
+system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
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+system.cpu.kern.mode_good::kernel 1911
+system.cpu.kern.mode_good::user 1741
system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches
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system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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-system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 45169028500 2.36% 2.36% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5015931500 0.26% 2.62% # number of ticks spent at the given mode
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+system.cpu.kern.mode_ticks::idle 1859918392000 97.35% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 927876 # number of replacements
-system.cpu.icache.tagsinuse 508.762321 # Cycle average of tags in use
-system.cpu.icache.total_refs 55248171 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 928387 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 59.509850 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 35489468000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 508.762321 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.993676 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.993676 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 55248171 # number of ReadReq hits
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-system.cpu.icache.overall_misses::total 928547 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 12629515000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 12629515000 # number of demand (read+write) miss cycles
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-system.cpu.icache.ReadReq_accesses::cpu.inst 56176718 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 56176718 # number of demand (read+write) accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13601.373975 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13601.373975 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency::total 13601.373975 # average overall miss latency
+system.cpu.icache.replacements 927460 # number of replacements
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+system.cpu.icache.total_refs 55209154 # Total number of references to valid blocks.
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+system.cpu.icache.avg_refs 59.494482 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 32120759000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 509.121498 # Average occupied blocks per requestor
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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+system.cpu.icache.demand_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1390620 # number of replacements
-system.cpu.dcache.tagsinuse 511.980059 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14044869 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1391132 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 10.096000 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 99394000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.980059 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999961 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7812084 # number of ReadReq hits
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.writebacks::total 835360 # number of writebacks
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 336256 # number of replacements
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+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223220000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383925 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383925 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.173353 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.173353 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40021.369451 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.355018 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.355018 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383643 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383643 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279528 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.173360 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279528 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.173360 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42232.737321 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 29437.969642 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30034.166374 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36795.652729 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36795.652729 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42232.737321 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31647.554013 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31997.564926 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42232.737321 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31647.554013 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31997.564926 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
sim_ticks 912096763500 # Number of ticks simulated
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1783031 # Simulator instruction rate (inst/s)
-host_op_rate 2295648 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26389770183 # Simulator tick rate (ticks/s)
-host_mem_usage 380112 # Number of bytes of host memory used
-host_seconds 34.56 # Real time elapsed on the host
+host_inst_rate 1752000 # Simulator instruction rate (inst/s)
+host_op_rate 2255696 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 25930494646 # Simulator tick rate (ticks/s)
+host_mem_usage 382232 # Number of bytes of host memory used
+host_seconds 35.17 # Real time elapsed on the host
sim_insts 61625970 # Number of instructions simulated
sim_ops 79343340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 0 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 0 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 0 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 0 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 0 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
+system.physmem.totBusLat 0 # Total cycles spent in databus access
+system.physmem.totBankLat 0 # Total cycles spent in bank access
+system.physmem.avgQLat nan # Average queueing delay per request
+system.physmem.avgBankLat nan # Average bank access latency per request
+system.physmem.avgBusLat nan # Average bus latency per request
+system.physmem.avgMemAccLat nan # Average memory access latency
+system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.00 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 0 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate nan # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap nan # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
sim_ticks 2332810264000 # Number of ticks simulated
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1681370 # Simulator instruction rate (inst/s)
-host_op_rate 2162138 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64929680145 # Simulator tick rate (ticks/s)
-host_mem_usage 380112 # Number of bytes of host memory used
-host_seconds 35.93 # Real time elapsed on the host
+host_inst_rate 1184768 # Simulator instruction rate (inst/s)
+host_op_rate 1523538 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 45752340761 # Simulator tick rate (ticks/s)
+host_mem_usage 382236 # Number of bytes of host memory used
+host_seconds 50.99 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 0 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 0 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 0 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 0 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
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system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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+system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
+system.cpu.l2cache.writebacks::total 57863 # number of writebacks
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
---------- Begin Simulation Statistics ----------
-sim_seconds 1.203606 # Number of seconds simulated
-sim_ticks 1203606499000 # Number of ticks simulated
-final_tick 1203606499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.182883 # Number of seconds simulated
+sim_ticks 1182883077500 # Number of ticks simulated
+final_tick 1182883077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 418240 # Simulator instruction rate (inst/s)
-host_op_rate 532998 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8191230777 # Simulator tick rate (ticks/s)
-host_mem_usage 386340 # Number of bytes of host memory used
-host_seconds 146.94 # Real time elapsed on the host
-sim_insts 61455549 # Number of instructions simulated
-sim_ops 78317886 # Number of ops (including micro ops) simulated
+host_inst_rate 330156 # Simulator instruction rate (inst/s)
+host_op_rate 420694 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6355289452 # Simulator tick rate (ticks/s)
+host_mem_usage 400808 # Number of bytes of host memory used
+host_seconds 186.13 # Real time elapsed on the host
+sim_insts 61450599 # Number of instructions simulated
+sim_ops 78301940 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 354084 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 364956 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5307824 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62191076 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 354084 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 364956 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4163904 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4712308 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4776304 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62110116 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4085952 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7191248 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7113296 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 11751 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 5784 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 82961 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6655190 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 65061 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 73702 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 74656 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6653925 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 63843 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 821897 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43124154 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 294186 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3538741 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 303219 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4409933 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51670605 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 294186 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 303219 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 597405 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3459523 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 14124 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2501103 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 5974750 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3459523 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43124154 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 294186 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3552865 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 303219 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 6911036 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 57645355 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::total 820679 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43879664 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3983748 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4037850 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 52507401 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3454232 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6013524 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3454232 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43879664 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3998120 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 6582771 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 58520925 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6653925 # Total number of read requests seen
+system.physmem.writeReqs 820679 # Total number of write requests seen
+system.physmem.cpureqs 271820 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 425851200 # Total number of bytes read from memory
+system.physmem.bytesWritten 52523456 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 62110116 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7113296 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 11750 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 415465 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50651 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1182878628500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 6825 # Categorize read packet sizes
+system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 159036 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 756836 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 63843 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 11750 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 6597380 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 40502 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 11414 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1777 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 643 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 481 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 367 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 201 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 155 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 139 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 117 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 109 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 69 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 44 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036694 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024611 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.017540 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801371 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848843 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.821333 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724005 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830123 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.768889 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540897 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577062 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.559043 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.106353 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.106353 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38590.549561 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45826.746479 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 39478.424022 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.671086 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.762382 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.276179 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.812057 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.204641 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.887283 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32165.809682 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34622.318054 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 33438.062745 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 4800569 # DTB read hits
-system.cpu0.dtb.read_misses 2116 # DTB read misses
-system.cpu0.dtb.write_hits 4101188 # DTB write hits
-system.cpu0.dtb.write_misses 405 # DTB write misses
+system.cpu0.dtb.read_hits 7072899 # DTB read hits
+system.cpu0.dtb.read_misses 3762 # DTB read misses
+system.cpu0.dtb.write_hits 5658444 # DTB write hits
+system.cpu0.dtb.write_misses 809 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 4802685 # DTB read accesses
-system.cpu0.dtb.write_accesses 4101593 # DTB write accesses
+system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 7076661 # DTB read accesses
+system.cpu0.dtb.write_accesses 5659253 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 8901757 # DTB hits
-system.cpu0.dtb.misses 2521 # DTB misses
-system.cpu0.dtb.accesses 8904278 # DTB accesses
-system.cpu0.itb.inst_hits 19425317 # ITB inst hits
-system.cpu0.itb.inst_misses 1350 # ITB inst misses
+system.cpu0.dtb.hits 12731343 # DTB hits
+system.cpu0.dtb.misses 4571 # DTB misses
+system.cpu0.dtb.accesses 12735914 # DTB accesses
+system.cpu0.itb.inst_hits 29570664 # ITB inst hits
+system.cpu0.itb.inst_misses 2205 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 19426667 # ITB inst accesses
-system.cpu0.itb.hits 19425317 # DTB hits
-system.cpu0.itb.misses 1350 # DTB misses
-system.cpu0.itb.accesses 19426667 # DTB accesses
-system.cpu0.numCycles 2405785466 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 29572869 # ITB inst accesses
+system.cpu0.itb.hits 29570664 # DTB hits
+system.cpu0.itb.misses 2205 # DTB misses
+system.cpu0.itb.accesses 29572869 # DTB accesses
+system.cpu0.numCycles 2365766155 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 19048205 # Number of instructions committed
-system.cpu0.committedOps 25051835 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 22684157 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses
-system.cpu0.num_func_calls 868672 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 2620308 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 22684157 # number of integer instructions
-system.cpu0.num_fp_insts 4364 # number of float instructions
-system.cpu0.num_int_register_reads 128951400 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 23731440 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written
-system.cpu0.num_mem_refs 9388218 # number of memory refs
-system.cpu0.num_load_insts 5047895 # Number of load instructions
-system.cpu0.num_store_insts 4340323 # Number of store instructions
-system.cpu0.num_idle_cycles 2301327262.807119 # Number of idle cycles
-system.cpu0.num_busy_cycles 104458203.192881 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.043420 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.956580 # Percentage of idle cycles
+system.cpu0.committedInsts 28872728 # Number of instructions committed
+system.cpu0.committedOps 37219681 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 33106320 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
+system.cpu0.num_func_calls 1241688 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4373344 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 33106320 # number of integer instructions
+system.cpu0.num_fp_insts 3860 # number of float instructions
+system.cpu0.num_int_register_reads 190095843 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 36231130 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
+system.cpu0.num_mem_refs 13399483 # number of memory refs
+system.cpu0.num_load_insts 7410404 # Number of load instructions
+system.cpu0.num_store_insts 5989079 # Number of store instructions
+system.cpu0.num_idle_cycles 2224921697.356119 # Number of idle cycles
+system.cpu0.num_busy_cycles 140844457.643881 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.059534 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.940466 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 34019 # number of quiesce instructions executed
-system.cpu0.icache.replacements 283204 # number of replacements
-system.cpu0.icache.tagsinuse 509.502445 # Cycle average of tags in use
-system.cpu0.icache.total_refs 19141584 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 283716 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 67.467411 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.502445 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 19141584 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 19141584 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 19141584 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 19141584 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 19141584 # number of overall hits
-system.cpu0.icache.overall_hits::total 19141584 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 283716 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 283716 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 283716 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 283716 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 283716 # number of overall misses
-system.cpu0.icache.overall_misses::total 283716 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929859500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 3929859500 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 3929859500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 3929859500 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 3929859500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 3929859500 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425300 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 19425300 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 19425300 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 19425300 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 19425300 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 19425300 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014605 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.014605 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014605 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.014605 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014605 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.014605 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13851.384836 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13851.384836 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13851.384836 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13851.384836 # average overall miss latency
+system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed
+system.cpu0.icache.replacements 425421 # number of replacements
+system.cpu0.icache.tagsinuse 509.627794 # Cycle average of tags in use
+system.cpu0.icache.total_refs 29144714 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 425933 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 68.425583 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 509.627794 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.995367 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.995367 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 29144714 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 29144714 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 29144714 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 29144714 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 29144714 # number of overall hits
+system.cpu0.icache.overall_hits::total 29144714 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 425933 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 425933 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 425933 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 425933 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 425933 # number of overall misses
+system.cpu0.icache.overall_misses::total 425933 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794506500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5794506500 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 5794506500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5794506500 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5794506500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5794506500 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570647 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 29570647 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 29570647 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 29570647 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 29570647 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 29570647 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014404 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.014404 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014404 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.014404 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014404 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.014404 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.267573 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.267573 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13604.267573 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13604.267573 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu0.dcache.demand_mshr_misses::total 263418 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 263418 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 263418 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698225500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698225500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965521500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965521500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54497000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54497000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50753000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50753000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.writebacks::writebacks 306622 # number of writebacks
+system.cpu0.dcache.writebacks::total 306622 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228156 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 228156 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141693 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 141693 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9329 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9329 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7493 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7493 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 369849 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 369849 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 369849 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 369849 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678104000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678104000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3847941000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3847941000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69654000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69654000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29513000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29513000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5663747000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 5663747000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5663747000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 5663747000 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130745000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130745000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193494500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193494500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324239500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324239500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031846 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029465 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029465 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062741 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062741 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061252 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061252 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11595.386359 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11595.386359 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33904.647703 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33904.647703 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6914.985408 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6914.985408 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6599.869961 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6599.869961 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6526045000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6526045000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6526045000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6526045000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559793500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559793500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128518500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128518500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688312000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688312000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033402 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025786 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025786 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059319 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059319 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047671 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047671 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.030007 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.030007 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11738.038886 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11738.038886 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27156.888484 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27156.888484 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7466.395112 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7466.395112 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3938.742827 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3938.742827 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 10589201 # DTB read hits
-system.cpu1.dtb.read_misses 5231 # DTB read misses
-system.cpu1.dtb.write_hits 7383574 # DTB write hits
-system.cpu1.dtb.write_misses 1834 # DTB write misses
+system.cpu1.dtb.read_hits 8308478 # DTB read hits
+system.cpu1.dtb.read_misses 3644 # DTB read misses
+system.cpu1.dtb.write_hits 5825596 # DTB write hits
+system.cpu1.dtb.write_misses 1434 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 193 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 10594432 # DTB read accesses
-system.cpu1.dtb.write_accesses 7385408 # DTB write accesses
+system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 8312122 # DTB read accesses
+system.cpu1.dtb.write_accesses 5827030 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 17972775 # DTB hits
-system.cpu1.dtb.misses 7065 # DTB misses
-system.cpu1.dtb.accesses 17979840 # DTB accesses
-system.cpu1.itb.inst_hits 43338256 # ITB inst hits
-system.cpu1.itb.inst_misses 3017 # ITB inst misses
+system.cpu1.dtb.hits 14134074 # DTB hits
+system.cpu1.dtb.misses 5078 # DTB misses
+system.cpu1.dtb.accesses 14139152 # DTB accesses
+system.cpu1.itb.inst_hits 33188345 # ITB inst hits
+system.cpu1.itb.inst_misses 2171 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 43341273 # ITB inst accesses
-system.cpu1.itb.hits 43338256 # DTB hits
-system.cpu1.itb.misses 3017 # DTB misses
-system.cpu1.itb.accesses 43341273 # DTB accesses
-system.cpu1.numCycles 2407212998 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 33190516 # ITB inst accesses
+system.cpu1.itb.hits 33188345 # DTB hits
+system.cpu1.itb.misses 2171 # DTB misses
+system.cpu1.itb.accesses 33190516 # DTB accesses
+system.cpu1.numCycles 2364324255 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 42407344 # Number of instructions committed
-system.cpu1.committedOps 53266051 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 47734651 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses
-system.cpu1.num_func_calls 1334953 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 5482869 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 47734651 # number of integer instructions
-system.cpu1.num_fp_insts 5457 # number of float instructions
-system.cpu1.num_int_register_reads 274813771 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 51971016 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written
-system.cpu1.num_mem_refs 18681443 # number of memory refs
-system.cpu1.num_load_insts 10999206 # Number of load instructions
-system.cpu1.num_store_insts 7682237 # Number of store instructions
-system.cpu1.num_idle_cycles 1827286039.250482 # Number of idle cycles
-system.cpu1.num_busy_cycles 579926958.749518 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.240912 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.759088 # Percentage of idle cycles
+system.cpu1.committedInsts 32577871 # Number of instructions committed
+system.cpu1.committedOps 41082259 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 37307050 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
+system.cpu1.num_func_calls 961975 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3732476 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 37307050 # number of integer instructions
+system.cpu1.num_fp_insts 6793 # number of float instructions
+system.cpu1.num_int_register_reads 213626787 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 39450306 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
+system.cpu1.num_mem_refs 14671800 # number of memory refs
+system.cpu1.num_load_insts 8630367 # Number of load instructions
+system.cpu1.num_store_insts 6041433 # Number of store instructions
+system.cpu1.num_idle_cycles 1868325738.966939 # Number of idle cycles
+system.cpu1.num_busy_cycles 495998516.033061 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.209784 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.790216 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 56704 # number of quiesce instructions executed
-system.cpu1.icache.replacements 582576 # number of replacements
-system.cpu1.icache.tagsinuse 479.066528 # Cycle average of tags in use
-system.cpu1.icache.total_refs 42755164 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 583088 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 73.325405 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 479.066528 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.935677 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.935677 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 42755164 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 42755164 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 42755164 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 42755164 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 42755164 # number of overall hits
-system.cpu1.icache.overall_hits::total 42755164 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 583088 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 583088 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 583088 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 583088 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 583088 # number of overall misses
-system.cpu1.icache.overall_misses::total 583088 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7852005500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 7852005500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 7852005500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 7852005500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 7852005500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 7852005500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 43338252 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 43338252 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 43338252 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 43338252 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 43338252 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 43338252 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013454 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.013454 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013454 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.013454 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013454 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.013454 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13466.244375 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13466.244375 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13466.244375 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13466.244375 # average overall miss latency
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+system.cpu1.dcache.LoadLockedReq_accesses::total 92813 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.StoreCondReq_accesses::total 92738 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 12089856 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 12089856 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 12089856 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 12089856 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023933 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030102 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.030102 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119164 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119164 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108240 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108240 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026472 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.026472 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026472 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.026472 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12639.483529 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12639.483529 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30099.294237 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 30099.294237 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8307.685353 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8307.685353 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5156.355848 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5156.355848 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20810.086615 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20810.086615 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 366504 # number of writebacks
-system.cpu1.dcache.writebacks::total 366504 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253127 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 253127 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178055 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 178055 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13099 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13099 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10394 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10394 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 431182 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 431182 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 431182 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 431182 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2770994500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2770994500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5292766500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5292766500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89595500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89595500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42224000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42224000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8063761000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 8063761000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8063761000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 8063761000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170066366500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170066366500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40314514000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40314514000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210380880500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210380880500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027062 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027390 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027390 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104844 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104844 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083244 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083244 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.027196 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.027196 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.052270 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.052270 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29725.458426 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29725.458426 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6839.873273 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6839.873273 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4062.343660 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4062.343660 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 265110 # number of writebacks
+system.cpu1.dcache.writebacks::total 265110 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170271 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 170271 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149767 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 149767 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11060 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11060 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10034 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10034 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 320038 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 320038 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 320038 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 320038 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1811595500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1811595500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4208347000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4208347000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69763000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69763000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31693500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31693500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6019942500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 6019942500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6019942500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 6019942500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168625975500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168625975500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666930000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666930000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186292905500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186292905500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023933 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023933 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030102 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030102 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119164 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119164 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108197 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108197 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026472 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.026472 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10639.483529 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10639.483529 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28099.294237 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28099.294237 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6307.685353 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6307.685353 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3158.610724 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3158.610724 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 522347967555 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 522347967555 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 522347967555 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 522347967555 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446709885400 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 446709885400 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446709885400 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 446709885400 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.624627 # Number of seconds simulated
-sim_ticks 2624627401000 # Number of ticks simulated
-final_tick 2624627401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.603636 # Number of seconds simulated
+sim_ticks 2603636076000 # Number of ticks simulated
+final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 463403 # Simulator instruction rate (inst/s)
-host_op_rate 589674 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 20203281292 # Simulator tick rate (ticks/s)
-host_mem_usage 381220 # Number of bytes of host memory used
-host_seconds 129.91 # Real time elapsed on the host
-sim_insts 60201162 # Number of instructions simulated
-sim_ops 76605148 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 123834568 # Number of bytes read from this memory
+host_inst_rate 485506 # Simulator instruction rate (inst/s)
+host_op_rate 617798 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20998999798 # Simulator tick rate (ticks/s)
+host_mem_usage 395692 # Number of bytes of host memory used
+host_seconds 123.99 # Real time elapsed on the host
+sim_insts 60197128 # Number of instructions simulated
+sim_ops 76599899 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9049808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 133590712 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3677120 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6693192 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15479321 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141437 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15637997 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57455 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811473 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47181771 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 268924 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3448035 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50898925 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 268924 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 268924 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1401006 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1149143 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2550149 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1401006 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47181771 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 268924 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4597178 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53449074 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15494089 # Total number of read requests seen
+system.physmem.writeReqs 811479 # Total number of write requests seen
+system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 991621696 # Total number of bytes read from memory
+system.physmem.bytesWritten 51934656 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2603631716000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 6652 # Categorize read packet sizes
+system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 152013 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 754018 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 57461 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 15419651 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 56393 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 11796 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2238 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1067 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 810 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 393 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 217 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 134 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 89 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 74 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 49 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 3755940486 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 281915228486 # Sum of mem lat for all requests
+system.physmem.totBusLat 61975012000 # Total cycles spent in databus access
+system.physmem.totBankLat 216184276000 # Total cycles spent in bank access
+system.physmem.avgQLat 242.42 # Average queueing delay per request
+system.physmem.avgBankLat 13953.00 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 18195.41 # Average memory access latency
+system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 2.51 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.11 # Average read queue length over time
+system.physmem.avgWrQLen 12.38 # Average write queue length over time
+system.physmem.readRowHits 15449465 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784611 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes
+system.physmem.avgGap 159677.46 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14996727 # DTB read hits
-system.cpu.dtb.read_misses 7361 # DTB read misses
-system.cpu.dtb.write_hits 11231610 # DTB write hits
-system.cpu.dtb.write_misses 2211 # DTB write misses
+system.cpu.dtb.read_hits 14995523 # DTB read hits
+system.cpu.dtb.read_misses 7332 # DTB read misses
+system.cpu.dtb.write_hits 11230789 # DTB write hits
+system.cpu.dtb.write_misses 2203 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 15004088 # DTB read accesses
-system.cpu.dtb.write_accesses 11233821 # DTB write accesses
+system.cpu.dtb.read_accesses 15002855 # DTB read accesses
+system.cpu.dtb.write_accesses 11232992 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26228337 # DTB hits
-system.cpu.dtb.misses 9572 # DTB misses
-system.cpu.dtb.accesses 26237909 # DTB accesses
-system.cpu.itb.inst_hits 61495131 # ITB inst hits
+system.cpu.dtb.hits 26226312 # DTB hits
+system.cpu.dtb.misses 9535 # DTB misses
+system.cpu.dtb.accesses 26235847 # DTB accesses
+system.cpu.itb.inst_hits 61491068 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 61499602 # ITB inst accesses
-system.cpu.itb.hits 61495131 # DTB hits
+system.cpu.itb.inst_accesses 61495539 # ITB inst accesses
+system.cpu.itb.hits 61491068 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 61499602 # DTB accesses
-system.cpu.numCycles 5249254802 # number of cpu cycles simulated
+system.cpu.itb.accesses 61495539 # DTB accesses
+system.cpu.numCycles 5207272152 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60201162 # Number of instructions committed
-system.cpu.committedOps 76605148 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 68872531 # Number of integer alu accesses
+system.cpu.committedInsts 60197128 # Number of instructions committed
+system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
-system.cpu.num_func_calls 2139915 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7948068 # number of instructions that are conditional controls
-system.cpu.num_int_insts 68872531 # number of integer instructions
+system.cpu.num_func_calls 2139710 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls
+system.cpu.num_int_insts 68867725 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 394780405 # number of times the integer registers were read
-system.cpu.num_int_register_writes 74180740 # number of times the integer registers were written
+system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read
+system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_mem_refs 27395680 # number of memory refs
-system.cpu.num_load_insts 15660706 # Number of load instructions
-system.cpu.num_store_insts 11734974 # Number of store instructions
-system.cpu.num_idle_cycles 4573851223.612257 # Number of idle cycles
-system.cpu.num_busy_cycles 675403578.387743 # Number of busy cycles
-system.cpu.not_idle_fraction 0.128667 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.871333 # Percentage of idle cycles
+system.cpu.num_mem_refs 27393681 # number of memory refs
+system.cpu.num_load_insts 15659530 # Number of load instructions
+system.cpu.num_store_insts 11734151 # Number of store instructions
+system.cpu.num_idle_cycles 4579082960.576241 # Number of idle cycles
+system.cpu.num_busy_cycles 628189191.423759 # Number of busy cycles
+system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.879363 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed
-system.cpu.icache.replacements 855895 # number of replacements
-system.cpu.icache.tagsinuse 510.920698 # Cycle average of tags in use
-system.cpu.icache.total_refs 60638724 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 856407 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 70.805965 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.920698 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 60638724 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 60638724 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 60638724 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 60638724 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 60638724 # number of overall hits
-system.cpu.icache.overall_hits::total 60638724 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 856407 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 856407 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 856407 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 856407 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 856407 # number of overall misses
-system.cpu.icache.overall_misses::total 856407 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 11564476500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 11564476500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 11564476500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 11564476500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 11564476500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 11564476500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 61495131 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 61495131 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 61495131 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 61495131 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 61495131 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 61495131 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.481989 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13503.481989 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13503.481989 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13503.481989 # average overall miss latency
+system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed
+system.cpu.icache.replacements 855498 # number of replacements
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537899 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537899 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.102794 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.102817 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.102794 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.203015 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.521452 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.392344 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40004.872955 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40004.872955 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40002.162503 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40002.162503 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37489.063025 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39492.807466 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38455.347716 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.142758 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.142758 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32825.399929 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32825.399929 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1246144703911 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1246144703911 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1052670853165 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1052670853165 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
sim_ticks 5112040968500 # Number of ticks simulated
final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 923075 # Simulator instruction rate (inst/s)
-host_op_rate 1890063 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 23616389220 # Simulator tick rate (ticks/s)
-host_mem_usage 353316 # Number of bytes of host memory used
-host_seconds 216.46 # Real time elapsed on the host
+host_inst_rate 468346 # Simulator instruction rate (inst/s)
+host_op_rate 958973 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11982395829 # Simulator tick rate (ticks/s)
+host_mem_usage 354180 # Number of bytes of host memory used
+host_seconds 426.63 # Real time elapsed on the host
sim_insts 199810236 # Number of instructions simulated
-sim_ops 409125915 # Number of ops (including micro ops) simulated
+sim_ops 409125920 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 0 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 0 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 0 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 0 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 0 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
+system.physmem.totBusLat 0 # Total cycles spent in databus access
+system.physmem.totBankLat 0 # Total cycles spent in bank access
+system.physmem.avgQLat nan # Average queueing delay per request
+system.physmem.avgBankLat nan # Average bank access latency per request
+system.physmem.avgBusLat nan # Average bus latency per request
+system.physmem.avgMemAccLat nan # Average memory access latency
+system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.00 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 0 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate nan # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap nan # Average gap between requests
system.iocache.replacements 47569 # number of replacements
system.iocache.tagsinuse 0.042402 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 199810236 # Number of instructions committed
-system.cpu.committedOps 409125915 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 374289906 # Number of integer alu accesses
+system.cpu.committedOps 409125920 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 374289911 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls
-system.cpu.num_int_insts 374289906 # number of integer instructions
+system.cpu.num_conditional_control_insts 39954536 # number of instructions that are conditional controls
+system.cpu.num_int_insts 374289911 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 915450684 # number of times the integer registers were read
-system.cpu.num_int_register_writes 480322735 # number of times the integer registers were written
+system.cpu.num_int_register_reads 915450709 # number of times the integer registers were read
+system.cpu.num_int_register_writes 480322748 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 35624588 # number of memory refs
system.cpu.num_load_insts 27216588 # Number of load instructions
system.cpu.num_store_insts 8408000 # Number of store instructions
-system.cpu.num_idle_cycles 9770609605.299961 # Number of idle cycles
-system.cpu.num_busy_cycles 453472354.700038 # Number of busy cycles
+system.cpu.num_idle_cycles 9770609595.971962 # Number of idle cycles
+system.cpu.num_busy_cycles 453472364.028039 # Number of busy cycles
system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5102019603000 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.warmup_cycle 5102019608500 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5101206381500 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.warmup_cycle 5101206384000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy
system.cpu.dcache.writebacks::total 1534848 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 106558 # number of replacements
-system.cpu.l2cache.tagsinuse 64822.149249 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 64822.149247 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks.
system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 2434.994085 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 10405.564956 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 10405.564957 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
---------- Begin Simulation Statistics ----------
-sim_seconds 5.187896 # Number of seconds simulated
-sim_ticks 5187896410000 # Number of ticks simulated
-final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.191113 # Number of seconds simulated
+sim_ticks 5191112864000 # Number of ticks simulated
+final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 812782 # Simulator instruction rate (inst/s)
-host_op_rate 1566838 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32873266023 # Simulator tick rate (ticks/s)
-host_mem_usage 347504 # Number of bytes of host memory used
-host_seconds 157.82 # Real time elapsed on the host
-sim_insts 128269216 # Number of instructions simulated
-sim_ops 247270559 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory
+host_inst_rate 414932 # Simulator instruction rate (inst/s)
+host_op_rate 799857 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16795720800 # Simulator tick rate (ticks/s)
+host_mem_usage 384032 # Number of bytes of host memory used
+host_seconds 309.07 # Real time elapsed on the host
+sim_insts 128244614 # Number of instructions simulated
+sim_ops 247214605 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 826944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 8996288 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12690880 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 826944 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 826944 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8107200 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8107200 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 44802 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9026368 # Number of bytes read from this memory
+system.physmem.bytes_read::total 12705024 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 825984 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 825984 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8129280 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8129280 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 44568 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12921 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 140567 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 198295 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 126675 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 126675 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 552696 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 12906 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 141037 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 198516 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 127020 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 127020 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 549468 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 159399 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1734092 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2446248 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 159399 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 159399 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1562714 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1562714 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1562714 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 552696 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 159115 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1738812 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2447457 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 159115 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 159115 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1565999 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1565999 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1565999 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 549468 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 159399 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1734092 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4008962 # Total bandwidth to/from this memory (bytes/s)
-system.iocache.replacements 47503 # number of replacements
-system.iocache.tagsinuse 0.106662 # Cycle average of tags in use
+system.physmem.bw_total::cpu.inst 159115 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1738812 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4013456 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 198516 # Total number of read requests seen
+system.physmem.writeReqs 127020 # Total number of write requests seen
+system.physmem.cpureqs 331314 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 12705024 # Total number of bytes read from memory
+system.physmem.bytesWritten 8129280 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 12705024 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 8129280 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 1599 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 12028 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 12411 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 11776 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 12503 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 12483 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 12755 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 12240 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 12788 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 12663 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 12687 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 12141 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 12548 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 12236 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 12474 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 11907 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 12788 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7431 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7966 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7373 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 8083 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7981 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 8219 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7719 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 8332 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 8225 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 8161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7712 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 8125 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7893 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7991 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7528 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 8281 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5191112800500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 198516 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 127020 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 1599 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 158090 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 11440 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::21 5522 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5522 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 898 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 2876260269 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 6438486269 # Sum of mem lat for all requests
+system.physmem.totBusLat 793712000 # Total cycles spent in databus access
+system.physmem.totBankLat 2768514000 # Total cycles spent in bank access
+system.physmem.avgQLat 14495.23 # Average queueing delay per request
+system.physmem.avgBankLat 13952.23 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 32447.47 # Average memory access latency
+system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
+system.physmem.avgWrQLen 9.06 # Average write queue length over time
+system.physmem.readRowHits 179831 # Number of row buffer hits during reads
+system.physmem.writeRowHits 78085 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 90.63 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 61.47 # Row buffer hit rate for writes
+system.physmem.avgGap 15946355.55 # Average gap between requests
+system.iocache.replacements 47506 # number of replacements
+system.iocache.tagsinuse 0.117830 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47519 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47522 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 5044925516000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.106662 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.006666 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.006666 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 838 # number of ReadReq misses
+system.iocache.warmup_cycle 5044498925000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.117830 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.007364 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.007364 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 841 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 841 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47558 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47558 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses
-system.iocache.overall_misses::total 47558 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130086932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 130086932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10826250092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10826250092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10826250092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10826250092 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47561 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47561 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47561 # number of overall misses
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system.iocache.writebacks::total 46667 # number of writebacks
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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---------- Begin Simulation Statistics ----------
sim_seconds 0.200392 # Number of seconds simulated
sim_ticks 200392337000 # Number of ticks simulated
-final_tick 4320161594000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick 4320161528000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 246693534 # Simulator instruction rate (inst/s)
-host_op_rate 246690485 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 182041258854 # Simulator tick rate (ticks/s)
-host_mem_usage 459700 # Number of bytes of host memory used
-host_seconds 1.10 # Real time elapsed on the host
-sim_insts 271555592 # Number of instructions simulated
-sim_ops 271555592 # Number of ops (including micro ops) simulated
-testsys.physmem.bytes_read::cpu.inst 13229896 # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data 4514804 # Number of bytes read from this memory
+host_inst_rate 90899186 # Simulator instruction rate (inst/s)
+host_op_rate 90898450 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 67078334403 # Simulator tick rate (ticks/s)
+host_mem_usage 463260 # Number of bytes of host memory used
+host_seconds 2.99 # Real time elapsed on the host
+sim_insts 271551386 # Number of instructions simulated
+sim_ops 271551386 # Number of ops (including micro ops) simulated
+testsys.physmem.bytes_read::cpu.inst 13230208 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data 4514888 # Number of bytes read from this memory
testsys.physmem.bytes_read::tsunami.ethernet 1464 # Number of bytes read from this memory
-testsys.physmem.bytes_read::total 17746164 # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst 13229896 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total 13229896 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data 3697636 # Number of bytes written to this memory
+testsys.physmem.bytes_read::total 17746560 # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst 13230208 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total 13230208 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data 3697656 # Number of bytes written to this memory
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
-testsys.physmem.bytes_written::total 3698538 # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst 3307474 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data 615757 # Number of read requests responded to by this memory
+testsys.physmem.bytes_written::total 3698558 # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst 3307552 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data 615769 # Number of read requests responded to by this memory
testsys.physmem.num_reads::tsunami.ethernet 43 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total 3923274 # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data 478509 # Number of write requests responded to by this memory
+testsys.physmem.num_reads::total 3923364 # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data 478513 # Number of write requests responded to by this memory
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total 478540 # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst 66019970 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data 22529824 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.num_writes::total 478544 # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst 66021527 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data 22530243 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::tsunami.ethernet 7306 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total 88557099 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst 66019970 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total 66019970 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data 18451983 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total 88559075 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst 66021527 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total 66021527 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data 18452083 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total 18456484 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst 66019970 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data 40981807 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_write::total 18456584 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst 66021527 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data 40982326 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::tsunami.ethernet 11807 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total 107013583 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total 107015659 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.readReqs 0 # Total number of read requests seen
+testsys.physmem.writeReqs 0 # Total number of write requests seen
+testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+testsys.physmem.bytesRead 0 # Total number of bytes read from memory
+testsys.physmem.bytesWritten 0 # Total number of bytes written to memory
+testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
+testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
+testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+testsys.physmem.totGap 0 # Total gap between requests
+testsys.physmem.readPktSize::0 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::1 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::2 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::3 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::7 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::8 0 # Categorize read packet sizes
+testsys.physmem.writePktSize::0 0 # categorize write packet sizes
+testsys.physmem.writePktSize::1 0 # categorize write packet sizes
+testsys.physmem.writePktSize::2 0 # categorize write packet sizes
+testsys.physmem.writePktSize::3 0 # categorize write packet sizes
+testsys.physmem.writePktSize::4 0 # categorize write packet sizes
+testsys.physmem.writePktSize::5 0 # categorize write packet sizes
+testsys.physmem.writePktSize::6 0 # categorize write packet sizes
+testsys.physmem.writePktSize::7 0 # categorize write packet sizes
+testsys.physmem.writePktSize::8 0 # categorize write packet sizes
+testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
+testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
+testsys.physmem.totBusLat 0 # Total cycles spent in databus access
+testsys.physmem.totBankLat 0 # Total cycles spent in bank access
+testsys.physmem.avgQLat nan # Average queueing delay per request
+testsys.physmem.avgBankLat nan # Average bank access latency per request
+testsys.physmem.avgBusLat nan # Average bus latency per request
+testsys.physmem.avgMemAccLat nan # Average memory access latency
+testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
+testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
+testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
+testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
+testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
+testsys.physmem.readRowHits 0 # Number of row buffer hits during reads
+testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes
+testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads
+testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+testsys.physmem.avgGap nan # Average gap between requests
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
-testsys.cpu.dtb.read_hits 611875 # DTB read hits
+testsys.cpu.dtb.read_hits 611887 # DTB read hits
testsys.cpu.dtb.read_misses 3287 # DTB read misses
testsys.cpu.dtb.read_acv 80 # DTB read access violations
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
-testsys.cpu.dtb.write_hits 478325 # DTB write hits
+testsys.cpu.dtb.write_hits 478329 # DTB write hits
testsys.cpu.dtb.write_misses 528 # DTB write misses
testsys.cpu.dtb.write_acv 81 # DTB write access violations
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
-testsys.cpu.dtb.data_hits 1090200 # DTB hits
+testsys.cpu.dtb.data_hits 1090216 # DTB hits
testsys.cpu.dtb.data_misses 3815 # DTB misses
testsys.cpu.dtb.data_acv 161 # DTB access violations
testsys.cpu.dtb.data_accesses 335402 # DTB accesses
-testsys.cpu.itb.fetch_hits 1215641 # ITB hits
+testsys.cpu.itb.fetch_hits 1215659 # ITB hits
testsys.cpu.itb.fetch_misses 1497 # ITB misses
testsys.cpu.itb.fetch_acv 69 # ITB acv
-testsys.cpu.itb.fetch_accesses 1217138 # ITB accesses
+testsys.cpu.itb.fetch_accesses 1217156 # ITB accesses
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 399134827 # number of cpu cycles simulated
+testsys.cpu.numCycles 399134959 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.committedInsts 3303498 # Number of instructions committed
-testsys.cpu.committedOps 3303498 # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses 3114409 # Number of integer alu accesses
+testsys.cpu.committedInsts 3303576 # Number of instructions committed
+testsys.cpu.committedOps 3303576 # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses 3114478 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
-testsys.cpu.num_func_calls 87506 # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts 347031 # number of instructions that are conditional controls
-testsys.cpu.num_int_insts 3114409 # number of integer instructions
+testsys.cpu.num_func_calls 87508 # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts 347037 # number of instructions that are conditional controls
+testsys.cpu.num_int_insts 3114478 # number of integer instructions
testsys.cpu.num_fp_insts 17380 # number of float instructions
-testsys.cpu.num_int_register_reads 4292439 # number of times the integer registers were read
-testsys.cpu.num_int_register_writes 2256595 # number of times the integer registers were written
+testsys.cpu.num_int_register_reads 4292532 # number of times the integer registers were read
+testsys.cpu.num_int_register_writes 2256656 # number of times the integer registers were written
testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
-testsys.cpu.num_mem_refs 1099884 # number of memory refs
-testsys.cpu.num_load_insts 619431 # Number of load instructions
-testsys.cpu.num_store_insts 480453 # Number of store instructions
-testsys.cpu.num_idle_cycles 395839404.829048 # Number of idle cycles
-testsys.cpu.num_busy_cycles 3295422.170952 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.008256 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.991744 # Percentage of idle cycles
+testsys.cpu.num_mem_refs 1099900 # number of memory refs
+testsys.cpu.num_load_insts 619443 # Number of load instructions
+testsys.cpu.num_store_insts 480457 # Number of store instructions
+testsys.cpu.num_idle_cycles 395839458.060266 # Number of idle cycles
+testsys.cpu.num_busy_cycles 3295500.939734 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.008257 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.991743 # Percentage of idle cycles
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
testsys.cpu.kern.inst.quiesce 213 # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei 16709 # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0 4122 40.57% 40.57% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21 54 0.53% 41.10% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22 205 2.02% 43.12% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31 5779 56.88% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total 10160 # number of times we switched to this ipl
+testsys.cpu.kern.inst.hwrei 16711 # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0 4122 40.56% 40.56% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21 54 0.53% 41.09% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::22 205 2.02% 43.11% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::31 5781 56.89% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total 10162 # number of times we switched to this ipl
testsys.cpu.kern.ipl_good::0 4116 48.47% 48.47% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::21 54 0.64% 49.11% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::22 205 2.41% 51.53% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::31 4116 48.47% 100.00% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::total 8491 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0 199321085500 99.88% 99.88% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::0 199321108000 99.88% 99.88% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::21 4521000 0.00% 99.88% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 99.88% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31 233213000 0.12% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total 199567634500 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31 233256500 0.12% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total 199567700500 # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_used::0 0.998544 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31 0.712234 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total 0.835728 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::31 0.711988 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total 0.835564 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
-testsys.cpu.kern.callpal::swpctx 438 4.02% 4.02% # number of callpals executed
+testsys.cpu.kern.callpal::swpctx 438 4.01% 4.01% # number of callpals executed
testsys.cpu.kern.callpal::tbi 20 0.18% 4.20% # number of callpals executed
-testsys.cpu.kern.callpal::swpipl 8990 82.42% 86.62% # number of callpals executed
+testsys.cpu.kern.callpal::swpipl 8992 82.42% 86.62% # number of callpals executed
testsys.cpu.kern.callpal::rdps 359 3.29% 89.91% # number of callpals executed
-testsys.cpu.kern.callpal::wrusp 3 0.03% 89.93% # number of callpals executed
+testsys.cpu.kern.callpal::wrusp 3 0.03% 89.94% # number of callpals executed
testsys.cpu.kern.callpal::rdusp 3 0.03% 89.96% # number of callpals executed
testsys.cpu.kern.callpal::rti 911 8.35% 98.31% # number of callpals executed
testsys.cpu.kern.callpal::callsys 140 1.28% 99.60% # number of callpals executed
testsys.cpu.kern.callpal::imb 44 0.40% 100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total 10908 # number of callpals executed
+testsys.cpu.kern.callpal::total 10910 # number of callpals executed
testsys.cpu.kern.mode_switch::kernel 1133 # number of protection mode switches
testsys.cpu.kern.mode_switch::user 647 # number of protection mode switches
testsys.cpu.kern.mode_switch::idle 217 # number of protection mode switches
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::idle 0.023041 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::total 0.652979 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel 931595000 57.07% 57.07% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user 532793000 32.64% 89.71% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle 168009000 10.29% 100.00% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::kernel 931596000 57.08% 57.08% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::user 532793000 32.64% 89.72% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::idle 167721000 10.28% 100.00% # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
drivesys.physmem.bw_total::cpu.data 21904410 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 11448 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 60986094 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.readReqs 0 # Total number of read requests seen
+drivesys.physmem.writeReqs 0 # Total number of write requests seen
+drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+drivesys.physmem.bytesRead 0 # Total number of bytes read from memory
+drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory
+drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
+drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
+drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+drivesys.physmem.totGap 0 # Total gap between requests
+drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes
+drivesys.physmem.writePktSize::0 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::1 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::2 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::3 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::4 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::5 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::6 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::7 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::8 0 # categorize write packet sizes
+drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
+drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
+drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
+drivesys.physmem.totBankLat 0 # Total cycles spent in bank access
+drivesys.physmem.avgQLat nan # Average queueing delay per request
+drivesys.physmem.avgBankLat nan # Average bank access latency per request
+drivesys.physmem.avgBusLat nan # Average bus latency per request
+drivesys.physmem.avgMemAccLat nan # Average memory access latency
+drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
+drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
+drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
+drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
+drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
+drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads
+drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes
+drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads
+drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+drivesys.physmem.avgGap nan # Average gap between requests
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.cpu.kern.mode_switch_good::total 0.441352 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_ticks::kernel 66889000 2.31% 2.31% # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::user 319585750 11.03% 13.34% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle 2511439250 86.66% 100.00% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::idle 2511080250 86.66% 100.00% # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
---------- Begin Simulation Statistics ----------
sim_seconds 0.000390 # Number of seconds simulated
sim_ticks 390393500 # Number of ticks simulated
-final_tick 4320551987500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick 4320551921500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 309018358448 # Simulator instruction rate (inst/s)
-host_op_rate 304755215914 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 428792748186 # Simulator tick rate (ticks/s)
-host_mem_usage 459700 # Number of bytes of host memory used
+host_inst_rate 123937139701 # Simulator instruction rate (inst/s)
+host_op_rate 122659857960 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 174562814371 # Simulator tick rate (ticks/s)
+host_mem_usage 463260 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
-sim_insts 271558535 # Number of instructions simulated
-sim_ops 271558535 # Number of ops (including micro ops) simulated
+sim_insts 271554329 # Number of instructions simulated
+sim_ops 271554329 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read::cpu.inst 5888 # Number of bytes read from this memory
testsys.physmem.bytes_read::cpu.data 2272 # Number of bytes read from this memory
testsys.physmem.bytes_read::total 8160 # Number of bytes read from this memory
testsys.physmem.bw_total::cpu.inst 15082218 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::total 24201223 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.readReqs 0 # Total number of read requests seen
+testsys.physmem.writeReqs 0 # Total number of write requests seen
+testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+testsys.physmem.bytesRead 0 # Total number of bytes read from memory
+testsys.physmem.bytesWritten 0 # Total number of bytes written to memory
+testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
+testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
+testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+testsys.physmem.totGap 0 # Total gap between requests
+testsys.physmem.readPktSize::0 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::1 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::2 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::3 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::7 0 # Categorize read packet sizes
+testsys.physmem.readPktSize::8 0 # Categorize read packet sizes
+testsys.physmem.writePktSize::0 0 # categorize write packet sizes
+testsys.physmem.writePktSize::1 0 # categorize write packet sizes
+testsys.physmem.writePktSize::2 0 # categorize write packet sizes
+testsys.physmem.writePktSize::3 0 # categorize write packet sizes
+testsys.physmem.writePktSize::4 0 # categorize write packet sizes
+testsys.physmem.writePktSize::5 0 # categorize write packet sizes
+testsys.physmem.writePktSize::6 0 # categorize write packet sizes
+testsys.physmem.writePktSize::7 0 # categorize write packet sizes
+testsys.physmem.writePktSize::8 0 # categorize write packet sizes
+testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
+testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
+testsys.physmem.totBusLat 0 # Total cycles spent in databus access
+testsys.physmem.totBankLat 0 # Total cycles spent in bank access
+testsys.physmem.avgQLat nan # Average queueing delay per request
+testsys.physmem.avgBankLat nan # Average bank access latency per request
+testsys.physmem.avgBusLat nan # Average bus latency per request
+testsys.physmem.avgMemAccLat nan # Average memory access latency
+testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
+testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
+testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
+testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
+testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
+testsys.physmem.readRowHits 0 # Number of row buffer hits during reads
+testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes
+testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads
+testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+testsys.physmem.avgGap nan # Average gap between requests
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.physmem.bw_total::cpu.inst 15071972 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 24190977 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.readReqs 0 # Total number of read requests seen
+drivesys.physmem.writeReqs 0 # Total number of write requests seen
+drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
+drivesys.physmem.bytesRead 0 # Total number of bytes read from memory
+drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory
+drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
+drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
+drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+drivesys.physmem.totGap 0 # Total gap between requests
+drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes
+drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes
+drivesys.physmem.writePktSize::0 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::1 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::2 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::3 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::4 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::5 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::6 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::7 0 # categorize write packet sizes
+drivesys.physmem.writePktSize::8 0 # categorize write packet sizes
+drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
+drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
+drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
+drivesys.physmem.totBankLat 0 # Total cycles spent in bank access
+drivesys.physmem.avgQLat nan # Average queueing delay per request
+drivesys.physmem.avgBankLat nan # Average bank access latency per request
+drivesys.physmem.avgBusLat nan # Average bus latency per request
+drivesys.physmem.avgMemAccLat nan # Average memory access latency
+drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
+drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
+drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
+drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
+drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
+drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads
+drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes
+drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads
+drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+drivesys.physmem.avgGap nan # Average gap between requests
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 21628500 # Number of ticks simulated
-final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000020 # Number of seconds simulated
+sim_ticks 19841500 # Number of ticks simulated
+final_tick 19841500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 34038 # Simulator instruction rate (inst/s)
-host_op_rate 34033 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 115179622 # Simulator tick rate (ticks/s)
-host_mem_usage 212112 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 31060 # Simulator instruction rate (inst/s)
+host_op_rate 31057 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 96425663 # Simulator tick rate (ticks/s)
+host_mem_usage 216044 # Number of bytes of host memory used
+host_seconds 0.21 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 29952 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 19200 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 19200 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 890676653 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 497121853 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1387798507 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 890676653 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 890676653 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 890676653 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 497121853 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1387798507 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 967668775 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 541894514 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1509563289 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 967668775 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 967668775 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 967668775 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 541894514 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1509563289 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 469 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 29952 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 26 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 69 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 66 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 45 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 19827000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 469 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
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+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 1719468 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11463468 # Sum of mem lat for all requests
+system.physmem.totBusLat 1876000 # Total cycles spent in databus access
+system.physmem.totBankLat 7868000 # Total cycles spent in bank access
+system.physmem.avgQLat 3666.24 # Average queueing delay per request
+system.physmem.avgBankLat 16776.12 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 24442.36 # Average memory access latency
+system.physmem.avgRdBW 1509.56 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1509.56 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 9.43 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.58 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 401 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 42275.05 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 43258 # number of cpu cycles simulated
+system.cpu.numCycles 39684 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1606 # Number of BP lookups
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 11927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 11913 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 526 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 35855 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 7403 # Number of cycles cpu stages are processed.
-system.cpu.activity 17.113597 # Percentage of cycles cpu is active
+system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 32282 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 7402 # Number of cycles cpu stages are processed.
+system.cpu.activity 18.652354 # Percentage of cycles cpu is active
system.cpu.comLoads 1183 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1050 # Number of Branches instructions committed
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
-system.cpu.cpi 6.769640 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 6.210329 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.769640 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.147718 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 6.210329 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.161022 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.147718 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 38346 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 0.161022 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 34772 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 11.355125 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 39380 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization 12.377784 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 35806 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 8.964816 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 39087 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 9.642147 # Percentage of cycles stage was utilized (processing insts).
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+system.cpu.stage1.utilization 9.772200 # Percentage of cycles stage was utilized (processing insts).
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+system.cpu.stage2.runCycles 4172 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 10.513053 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 38344 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 3.097693 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 38800 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.utilization 3.376676 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 10.305608 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization 11.233747 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 138.677886 # Cycle average of tags in use
-system.cpu.icache.total_refs 557 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 142.150123 # Cycle average of tags in use
+system.cpu.icache.total_refs 558 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 138.677886 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits
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-system.cpu.icache.demand_hits::total 557 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 557 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 351 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 351 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses
-system.cpu.icache.overall_misses::total 351 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 19444500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 19444500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 19444500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 19444500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 19444500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 19444500 # number of overall miss cycles
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+system.cpu.icache.occ_percent::cpu.inst 0.069409 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.069409 # Average percentage of cache occupancy
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+system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 558 # number of overall hits
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+system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::total 350 # number of overall misses
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+system.cpu.icache.ReadReq_miss_latency::total 17305000 # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total 17305000 # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total 17305000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386564 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.386564 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55397.435897 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55397.435897 # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses
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+system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses
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+system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49442.857143 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 49442.857143 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 49442.857143 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 49442.857143 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 49 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 49 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 49 # number of overall MSHR hits
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+system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
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+system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16495000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 16495000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16495000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 16495000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16495000 # number of overall MSHR miss cycles
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35509.963455 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39911.789474 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36565.957071 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33528.712329 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33528.712329 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 12394500 # Number of ticks simulated
-final_tick 12394500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 11568000 # Number of ticks simulated
+final_tick 11568000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 52290 # Simulator instruction rate (inst/s)
-host_op_rate 52282 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 101684511 # Simulator tick rate (ticks/s)
-host_mem_usage 219660 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
+host_inst_rate 27765 # Simulator instruction rate (inst/s)
+host_op_rate 27764 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50400871 # Simulator tick rate (ticks/s)
+host_mem_usage 217072 # Number of bytes of host memory used
+host_seconds 0.23 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 11328 # Number of bytes read from this memory
-system.physmem.bytes_read::total 31296 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 177 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 489 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1611037154 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 913953770 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2524990923 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1611037154 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1611037154 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1611037154 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 913953770 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2524990923 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory
+system.physmem.bytes_read::total 31104 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 486 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1731673582 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 957123098 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2688796680 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1731673582 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1731673582 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1731673582 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 957123098 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2688796680 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 486 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 31104 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 19 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 11441000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 486 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 3089486 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12593486 # Sum of mem lat for all requests
+system.physmem.totBusLat 1944000 # Total cycles spent in databus access
+system.physmem.totBankLat 7560000 # Total cycles spent in bank access
+system.physmem.avgQLat 6356.97 # Average queueing delay per request
+system.physmem.avgBankLat 15555.56 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 25912.52 # Average memory access latency
+system.physmem.avgRdBW 2688.80 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2688.80 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 16.80 # Data bus utilization in percentage
+system.physmem.avgRdQLen 1.09 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 416 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 85.60 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 23541.15 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1990 # DTB read hits
-system.cpu.dtb.read_misses 56 # DTB read misses
+system.cpu.dtb.read_hits 1960 # DTB read hits
+system.cpu.dtb.read_misses 58 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 2046 # DTB read accesses
-system.cpu.dtb.write_hits 1084 # DTB write hits
-system.cpu.dtb.write_misses 30 # DTB write misses
+system.cpu.dtb.read_accesses 2018 # DTB read accesses
+system.cpu.dtb.write_hits 1076 # DTB write hits
+system.cpu.dtb.write_misses 32 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 1114 # DTB write accesses
-system.cpu.dtb.data_hits 3074 # DTB hits
-system.cpu.dtb.data_misses 86 # DTB misses
+system.cpu.dtb.write_accesses 1108 # DTB write accesses
+system.cpu.dtb.data_hits 3036 # DTB hits
+system.cpu.dtb.data_misses 90 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 3160 # DTB accesses
-system.cpu.itb.fetch_hits 2336 # ITB hits
+system.cpu.dtb.data_accesses 3126 # DTB accesses
+system.cpu.itb.fetch_hits 2261 # ITB hits
system.cpu.itb.fetch_misses 38 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2374 # ITB accesses
+system.cpu.itb.fetch_accesses 2299 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 24790 # number of cpu cycles simulated
+system.cpu.numCycles 23137 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2873 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 545 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2164 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2774 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1638 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 514 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 2124 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 769 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 8141 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 16442 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1200 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2939 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1838 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 885 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 405 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 7948 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 15915 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2774 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1174 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2854 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1765 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 730 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 739 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2336 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 367 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13982 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.175940 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.562615 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2261 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 13513 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.177755 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.562670 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11043 78.98% 78.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 296 2.12% 81.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 231 1.65% 82.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 234 1.67% 84.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 276 1.97% 86.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 200 1.43% 87.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 274 1.96% 89.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 190 1.36% 91.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1238 8.85% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10659 78.88% 78.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 293 2.17% 81.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 218 1.61% 82.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 238 1.76% 84.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 276 2.04% 86.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 191 1.41% 87.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 258 1.91% 89.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 175 1.30% 91.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1205 8.92% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13982 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.115894 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.663251 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 9096 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 904 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2739 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1171 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 257 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 89 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 15180 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1171 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9315 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 364 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2589 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 284 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 14415 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 250 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 10802 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 18056 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 18039 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 13513 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.119895 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.687859 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8886 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 751 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2667 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1129 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 236 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 88 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 14776 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1129 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9097 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 177 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2538 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 227 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 14039 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 10509 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 17564 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 17547 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6232 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 728 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2652 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 5939 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 34 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 671 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2611 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1355 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 12813 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 10578 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6130 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13982 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.756544 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.394074 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 12555 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 10392 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5880 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3411 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 13513 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.769037 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.410550 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9591 68.60% 68.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1568 11.21% 79.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1143 8.17% 87.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 728 5.21% 93.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 479 3.43% 96.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 273 1.95% 98.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 154 1.10% 99.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 33 0.24% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9295 68.79% 68.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1391 10.29% 79.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1141 8.44% 87.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 752 5.57% 93.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 466 3.45% 96.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 269 1.99% 98.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 153 1.13% 99.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 32 0.24% 99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 13982 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 13513 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 10 8.70% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 65 56.52% 65.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 40 34.78% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 11 9.57% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 65 56.52% 66.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 39 33.91% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7162 67.71% 67.73% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.73% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2248 21.25% 89.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1163 10.99% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7044 67.78% 67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.83% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2192 21.09% 88.92% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1151 11.08% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10578 # Type of FU issued
-system.cpu.iq.rate 0.426704 # Inst issue rate
+system.cpu.iq.FU_type_0::total 10392 # Type of FU issued
+system.cpu.iq.rate 0.449151 # Inst issue rate
system.cpu.iq.fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010872 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 35279 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 18978 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 9581 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.011066 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 34450 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 18472 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 9469 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 10680 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 10494 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1469 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 490 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1171 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 12931 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2652 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1129 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 30 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2611 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1355 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 151 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 403 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 554 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 9992 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2057 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 586 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 142 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 377 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 9865 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 88 # number of nop insts executed
-system.cpu.iew.exec_refs 3174 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1621 # Number of branches executed
-system.cpu.iew.exec_stores 1117 # Number of stores executed
-system.cpu.iew.exec_rate 0.403066 # Inst execution rate
-system.cpu.iew.wb_sent 9749 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 9591 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 5054 # num instructions producing a value
-system.cpu.iew.wb_consumers 6863 # num instructions consuming a value
+system.cpu.iew.exec_nop 86 # number of nop insts executed
+system.cpu.iew.exec_refs 3139 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1600 # Number of branches executed
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+system.cpu.iew.exec_rate 0.426373 # Inst execution rate
+system.cpu.iew.wb_sent 9638 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 9479 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 5022 # num instructions producing a value
+system.cpu.iew.wb_consumers 6814 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.386890 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.736413 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.409690 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.737012 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 6541 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 6282 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12811 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.498712 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.314684 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 432 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 0.515908 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.366435 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10031 78.30% 78.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1473 11.50% 89.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 525 4.10% 93.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 241 1.88% 95.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 164 1.28% 97.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 92 0.72% 97.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 108 0.84% 98.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 37 0.29% 98.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 140 1.09% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9732 78.59% 78.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1344 10.85% 89.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 509 4.11% 93.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 223 1.80% 95.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 188 1.52% 96.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 75 0.61% 97.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 105 0.85% 98.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 63 0.51% 98.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 145 1.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12811 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 12384 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6389 # Number of instructions committed
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
system.cpu.commit.function_calls 127 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 140 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 25250 # The number of ROB reads
-system.cpu.rob.rob_writes 27045 # The number of ROB writes
-system.cpu.timesIdled 255 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 10808 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 24559 # The number of ROB reads
+system.cpu.rob.rob_writes 26483 # The number of ROB writes
+system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 9624 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
-system.cpu.cpi 3.890458 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.890458 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.257039 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.257039 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12699 # number of integer regfile reads
-system.cpu.int_regfile_writes 7211 # number of integer regfile writes
+system.cpu.cpi 3.631042 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.631042 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.275403 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.275403 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12554 # number of integer regfile reads
+system.cpu.int_regfile_writes 7112 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 158.537993 # Cycle average of tags in use
-system.cpu.icache.total_refs 1881 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 6.009585 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 160.502909 # Cycle average of tags in use
+system.cpu.icache.total_refs 1827 # Total number of references to valid blocks.
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+system.cpu.icache.avg_refs 5.818471 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.occ_percent::cpu.inst 0.077411 # Average percentage of cache occupancy
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-system.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 455 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 15830500 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 15830500 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 15830500 # number of overall miss cycles
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34792.307692 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34792.307692 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34792.307692 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34792.307692 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_miss_latency::total 11526000 # number of overall MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_rate::total 0.133990 # mshr miss rate for demand accesses
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-system.cpu.icache.overall_mshr_miss_rate::total 0.133990 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36824.281150 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36824.281150 # average ReadReq mshr miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39748.587571 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3905000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37548.076923 # average ReadReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000007 # Number of seconds simulated
-sim_ticks 7079000 # Number of ticks simulated
-final_tick 7079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000006 # Number of seconds simulated
+sim_ticks 6408000 # Number of ticks simulated
+final_tick 6408000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 8209 # Simulator instruction rate (inst/s)
-host_op_rate 8209 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24342914 # Simulator tick rate (ticks/s)
-host_mem_usage 218360 # Number of bytes of host memory used
-host_seconds 0.29 # Real time elapsed on the host
+host_inst_rate 494 # Simulator instruction rate (inst/s)
+host_op_rate 494 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1327192 # Simulator tick rate (ticks/s)
+host_mem_usage 215760 # Number of bytes of host memory used
+host_seconds 4.83 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 273 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1699675095 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 768470123 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2468145218 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1699675095 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1699675095 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1699675095 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 768470123 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2468145218 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1877652934 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 848938826 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2726591760 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1877652934 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1877652934 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1877652934 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 848938826 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2726591760 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 273 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 17472 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 10 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 10 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 6357500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 273 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 137 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 90 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 1341773 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7053773 # Sum of mem lat for all requests
+system.physmem.totBusLat 1092000 # Total cycles spent in databus access
+system.physmem.totBankLat 4620000 # Total cycles spent in bank access
+system.physmem.avgQLat 4914.92 # Average queueing delay per request
+system.physmem.avgBankLat 16923.08 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 25838.00 # Average memory access latency
+system.physmem.avgRdBW 2726.59 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2726.59 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 17.04 # Data bus utilization in percentage
+system.physmem.avgRdQLen 1.10 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 229 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.88 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 23287.55 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 712 # DTB read hits
-system.cpu.dtb.read_misses 34 # DTB read misses
+system.cpu.dtb.read_hits 718 # DTB read hits
+system.cpu.dtb.read_misses 36 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 746 # DTB read accesses
-system.cpu.dtb.write_hits 367 # DTB write hits
-system.cpu.dtb.write_misses 20 # DTB write misses
+system.cpu.dtb.read_accesses 754 # DTB read accesses
+system.cpu.dtb.write_hits 382 # DTB write hits
+system.cpu.dtb.write_misses 24 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 387 # DTB write accesses
-system.cpu.dtb.data_hits 1079 # DTB hits
-system.cpu.dtb.data_misses 54 # DTB misses
+system.cpu.dtb.write_accesses 406 # DTB write accesses
+system.cpu.dtb.data_hits 1100 # DTB hits
+system.cpu.dtb.data_misses 60 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 1133 # DTB accesses
-system.cpu.itb.fetch_hits 1015 # ITB hits
+system.cpu.dtb.data_accesses 1160 # DTB accesses
+system.cpu.itb.fetch_hits 1042 # ITB hits
system.cpu.itb.fetch_misses 30 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 1045 # ITB accesses
+system.cpu.itb.fetch_accesses 1072 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.numCycles 14159 # number of cpu cycles simulated
+system.cpu.numCycles 12817 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 1131 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 255 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 792 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits
+system.cpu.BPredUnit.lookups 1162 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 576 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 259 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 820 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 228 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 213 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 4177 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 6936 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 432 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 862 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 243 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 224 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 4082 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 7077 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 1162 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1223 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 261 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 902 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1015 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 7112 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.975253 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.397370 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 857 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 1042 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 7043 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.004827 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.418564 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 5922 83.27% 83.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 52 0.73% 84.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 129 1.81% 85.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 100 1.41% 87.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 139 1.95% 89.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 63 0.89% 90.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 67 0.94% 91.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 67 0.94% 91.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 573 8.06% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 5820 82.64% 82.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 52 0.74% 83.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 133 1.89% 85.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 101 1.43% 86.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 157 2.23% 88.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 70 0.99% 89.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 69 0.98% 90.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 64 0.91% 91.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 577 8.19% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 7112 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.079879 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.489865 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 5180 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 1148 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 503 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 169 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 6175 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 503 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 5278 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 59 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 172 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 1058 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 42 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 5909 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 15 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 4299 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 6685 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 6673 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 7043 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.090661 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.552157 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 5035 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 297 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 1173 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 15 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 523 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 176 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 84 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 6290 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 301 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 523 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 5140 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 24 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 214 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 1083 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 59 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 6004 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 4336 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 6797 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 6785 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 2531 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 2568 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 136 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 5031 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 172 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 984 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 506 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 5173 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 4054 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 2424 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1475 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 4204 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 2615 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1486 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 7112 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.570022 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.279366 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 7043 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.596905 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.307061 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 5467 76.87% 76.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 597 8.39% 85.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 392 5.51% 90.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 263 3.70% 94.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 194 2.73% 97.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 122 1.72% 98.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 53 0.75% 99.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12 0.17% 99.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 5344 75.88% 75.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 621 8.82% 84.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 394 5.59% 90.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 268 3.81% 94.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 205 2.91% 97.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 132 1.87% 98.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 55 0.78% 99.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 11 0.16% 99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 7112 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 7043 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2 4.65% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 18 41.86% 46.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2 4.26% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 22 46.81% 51.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 23 48.94% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 2869 70.77% 70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 786 19.39% 90.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 398 9.82% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 2977 70.81% 70.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 808 19.22% 90.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 418 9.94% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 4054 # Type of FU issued
-system.cpu.iq.rate 0.286320 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 43 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010607 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 15329 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 7459 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 3702 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 4204 # Type of FU issued
+system.cpu.iq.rate 0.328002 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 47 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.011180 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 15542 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 7792 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 3821 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 4090 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 4244 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 569 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 182 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 212 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 503 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 46 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 5379 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 523 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 12 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 5532 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 63 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 984 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 506 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 154 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 211 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 3894 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 747 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 160 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 160 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 221 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 4011 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 193 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 342 # number of nop insts executed
-system.cpu.iew.exec_refs 1134 # number of memory reference insts executed
-system.cpu.iew.exec_branches 652 # Number of branches executed
-system.cpu.iew.exec_stores 387 # Number of stores executed
-system.cpu.iew.exec_rate 0.275019 # Inst execution rate
-system.cpu.iew.wb_sent 3793 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 3708 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1740 # num instructions producing a value
-system.cpu.iew.wb_consumers 2258 # num instructions consuming a value
+system.cpu.iew.exec_nop 353 # number of nop insts executed
+system.cpu.iew.exec_refs 1161 # number of memory reference insts executed
+system.cpu.iew.exec_branches 678 # Number of branches executed
+system.cpu.iew.exec_stores 406 # Number of stores executed
+system.cpu.iew.exec_rate 0.312944 # Inst execution rate
+system.cpu.iew.wb_sent 3922 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 3827 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1795 # num instructions producing a value
+system.cpu.iew.wb_consumers 2353 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.261883 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.770593 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.298588 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.762856 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 2798 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 2928 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 175 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 6609 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.389772 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.242894 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 6520 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.395092 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.243251 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 5727 86.65% 86.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 217 3.28% 89.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 312 4.72% 94.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 115 1.74% 96.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 67 1.01% 97.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 53 0.80% 98.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 34 0.51% 98.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 19 0.29% 99.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 65 0.98% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 5631 86.37% 86.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 221 3.39% 89.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 313 4.80% 94.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 120 1.84% 96.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 64 0.98% 97.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 55 0.84% 98.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 34 0.52% 98.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 22 0.34% 99.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 60 0.92% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 6609 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 6520 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
system.cpu.commit.function_calls 71 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 65 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 11671 # The number of ROB reads
-system.cpu.rob.rob_writes 11260 # The number of ROB writes
-system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7047 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 11717 # The number of ROB reads
+system.cpu.rob.rob_writes 11541 # The number of ROB writes
+system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5774 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
-system.cpu.cpi 5.931713 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.931713 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.168585 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.168585 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 4712 # number of integer regfile reads
-system.cpu.int_regfile_writes 2874 # number of integer regfile writes
+system.cpu.cpi 5.369501 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.369501 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.186237 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.186237 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 4858 # number of integer regfile reads
+system.cpu.int_regfile_writes 2964 # number of integer regfile writes
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 93.783034 # Cycle average of tags in use
-system.cpu.icache.total_refs 767 # Total number of references to valid blocks.
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 981500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 122.770960 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 120.198004 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 93.868144 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 28.902816 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.002865 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 10412000 # Number of ticks simulated
-final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 10062000 # Number of ticks simulated
+final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32172 # Simulator instruction rate (inst/s)
-host_op_rate 40134 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 72868464 # Simulator tick rate (ticks/s)
-host_mem_usage 233868 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_inst_rate 57856 # Simulator instruction rate (inst/s)
+host_op_rate 72170 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 126623534 # Simulator tick rate (ticks/s)
+host_mem_usage 231188 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
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-system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25600 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 400 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.readReqs 398 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 25472 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
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+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 10004500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 398 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 2567898 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests
+system.physmem.totBusLat 1592000 # Total cycles spent in databus access
+system.physmem.totBankLat 6552000 # Total cycles spent in bank access
+system.physmem.avgQLat 6452.01 # Average queueing delay per request
+system.physmem.avgBankLat 16462.31 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 26914.32 # Average memory access latency
+system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 15.82 # Data bus utilization in percentage
+system.physmem.avgRdQLen 1.06 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 323 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 25136.93 # Average gap between requests
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 20825 # number of cpu cycles simulated
+system.cpu.numCycles 20125 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2492 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2519 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2432 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2229 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2441 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2242 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 47 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 46 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8838 # Type of FU issued
-system.cpu.iq.rate 0.424394 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 221 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8888 # Type of FU issued
+system.cpu.iq.rate 0.441640 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3246 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1415 # Number of branches executed
-system.cpu.iew.exec_stores 1167 # Number of stores executed
-system.cpu.iew.exec_rate 0.404994 # Inst execution rate
-system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7997 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3850 # num instructions producing a value
-system.cpu.iew.wb_consumers 7766 # num instructions consuming a value
+system.cpu.iew.exec_refs 3261 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1428 # Number of branches executed
+system.cpu.iew.exec_stores 1173 # Number of stores executed
+system.cpu.iew.exec_rate 0.421615 # Inst execution rate
+system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8062 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3862 # num instructions producing a value
+system.cpu.iew.wb_consumers 7771 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 166 1.46% 98.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 56 0.49% 98.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 36 0.32% 99.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 114 1.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 11403 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4596 # Number of instructions committed
system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4980 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 22290 # The number of ROB reads
-system.cpu.rob.rob_writes 23328 # The number of ROB writes
-system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 22426 # The number of ROB reads
+system.cpu.rob.rob_writes 23541 # The number of ROB writes
+system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7781 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4596 # Number of Instructions Simulated
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
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-system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9207000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12243500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9207000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4564000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 13771000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9207000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4564000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 13771000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.771429 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892768 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7843874 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2768060 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10611934 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1736536 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1736536 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7843874 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4504596 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 12348470 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7843874 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4504596 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 12348470 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.769231 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892231 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.902494 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.902494 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28419.833333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34600.750000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29808.803371 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41346.095238 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41346.095238 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 10412000 # Number of ticks simulated
-final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 10062000 # Number of ticks simulated
+final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 40558 # Simulator instruction rate (inst/s)
-host_op_rate 50593 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 91854675 # Simulator tick rate (ticks/s)
-host_mem_usage 232720 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 70596 # Simulator instruction rate (inst/s)
+host_op_rate 88057 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 154493805 # Simulator tick rate (ticks/s)
+host_mem_usage 230168 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25600 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 400 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
+system.physmem.bytes_read::total 25472 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 398 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1755515802 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 775988869 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2531504671 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1755515802 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1755515802 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1755515802 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 775988869 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2531504671 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 398 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 25472 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 10004500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 398 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 2567898 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests
+system.physmem.totBusLat 1592000 # Total cycles spent in databus access
+system.physmem.totBankLat 6552000 # Total cycles spent in bank access
+system.physmem.avgQLat 6452.01 # Average queueing delay per request
+system.physmem.avgBankLat 16462.31 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 26914.32 # Average memory access latency
+system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 15.82 # Data bus utilization in percentage
+system.physmem.avgRdQLen 1.06 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 323 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 25136.93 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 20825 # number of cpu cycles simulated
+system.cpu.numCycles 20125 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2492 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2519 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2432 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2229 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2441 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2242 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 47 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 46 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8838 # Type of FU issued
-system.cpu.iq.rate 0.424394 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 221 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8888 # Type of FU issued
+system.cpu.iq.rate 0.441640 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions
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+system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3246 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1415 # Number of branches executed
-system.cpu.iew.exec_stores 1167 # Number of stores executed
-system.cpu.iew.exec_rate 0.404994 # Inst execution rate
-system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7997 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3850 # num instructions producing a value
-system.cpu.iew.wb_consumers 7766 # num instructions consuming a value
+system.cpu.iew.exec_refs 3261 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1428 # Number of branches executed
+system.cpu.iew.exec_stores 1173 # Number of stores executed
+system.cpu.iew.exec_rate 0.421615 # Inst execution rate
+system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8062 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3862 # num instructions producing a value
+system.cpu.iew.wb_consumers 7771 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 166 1.46% 98.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 56 0.49% 98.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 36 0.32% 99.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 114 1.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 11403 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4596 # Number of instructions committed
system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4980 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 22290 # The number of ROB reads
-system.cpu.rob.rob_writes 23328 # The number of ROB writes
-system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 22426 # The number of ROB reads
+system.cpu.rob.rob_writes 23541 # The number of ROB writes
+system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7781 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4596 # Number of Instructions Simulated
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
-system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 38756 # number of integer regfile reads
-system.cpu.int_regfile_writes 7886 # number of integer regfile writes
+system.cpu.cpi 4.378808 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 4.378808 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.228373 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.228373 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39006 # number of integer regfile reads
+system.cpu.int_regfile_writes 7962 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 15116 # number of misc regfile reads
+system.cpu.misc_regfile_reads 15230 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
-system.cpu.icache.replacements 3 # number of replacements
-system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use
-system.cpu.icache.total_refs 1564 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks.
+system.cpu.icache.replacements 4 # number of replacements
+system.cpu.icache.tagsinuse 152.520984 # Cycle average of tags in use
+system.cpu.icache.total_refs 1592 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 5.396610 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits
-system.cpu.icache.overall_hits::total 1564 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses
-system.cpu.icache.overall_misses::total 368 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 152.520984 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.074473 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.074473 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 1592 # number of overall hits
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+system.cpu.icache.demand_misses::total 358 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 358 # number of overall misses
+system.cpu.icache.overall_misses::total 358 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 11241000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 11241000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 11241000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 11241000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 11241000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 11241000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183590 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.183590 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.183590 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.183590 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.183590 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.183590 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31399.441341 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 31399.441341 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 31399.441341 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 31399.441341 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses
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-system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.103352 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 20184000 # Number of ticks simulated
-final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000019 # Number of seconds simulated
+sim_ticks 19373000 # Number of ticks simulated
+final_tick 19373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 91753 # Simulator instruction rate (inst/s)
-host_op_rate 91718 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 318298211 # Simulator tick rate (ticks/s)
-host_mem_usage 212944 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 54522 # Simulator instruction rate (inst/s)
+host_op_rate 54510 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 181593348 # Simulator tick rate (ticks/s)
+host_mem_usage 216696 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1005152596 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 437574316 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1442726912 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1005152596 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1005152596 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1005152596 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 437574316 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1442726912 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1047230682 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 455892221 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1503122903 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1047230682 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1047230682 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1047230682 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 455892221 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1503122903 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 455 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 29120 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 60 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 27 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 53 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 31 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 20 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 19298000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 455 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 311 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 2404453 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12694453 # Sum of mem lat for all requests
+system.physmem.totBusLat 1820000 # Total cycles spent in databus access
+system.physmem.totBankLat 8470000 # Total cycles spent in bank access
+system.physmem.avgQLat 5284.51 # Average queueing delay per request
+system.physmem.avgBankLat 18615.38 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 27899.90 # Average memory access latency
+system.physmem.avgRdBW 1503.12 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1503.12 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 9.39 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.66 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 357 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 42413.19 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
-system.cpu.numCycles 40369 # number of cpu cycles simulated
+system.cpu.numCycles 38747 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1146 # Number of BP lookups
system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 34984 # Number of cycles cpu's stages were not processed
+system.cpu.idleCycles 33362 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 5385 # Number of cycles cpu stages are processed.
-system.cpu.activity 13.339444 # Percentage of cycles cpu is active
+system.cpu.activity 13.897850 # Percentage of cycles cpu is active
system.cpu.comLoads 1163 # Number of Load instructions committed
system.cpu.comStores 925 # Number of Store instructions committed
system.cpu.comBranches 915 # Number of Branches instructions committed
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
-system.cpu.cpi 6.943412 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 6.664431 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.943412 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.144021 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 6.664431 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.150050 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.144021 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 36744 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 0.150050 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 35122 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 8.979663 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 37547 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization 9.355563 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 35925 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 6.990513 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 37585 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization 7.283145 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 35963 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 6.896381 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 39127 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization 7.185072 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 37505 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 3.076618 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 37465 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.utilization 3.205409 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 35843 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 7.193639 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization 7.494774 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 13 # number of replacements
-system.cpu.icache.tagsinuse 147.108411 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 148.105671 # Cycle average of tags in use
system.cpu.icache.total_refs 410 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 147.108411 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.071830 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.071830 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 148.105671 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.072317 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.072317 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits
system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses
system.cpu.icache.overall_misses::total 344 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 19298000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 19298000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 19298000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 19298000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 19298000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 19298000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 18000000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 18000000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 18000000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 18000000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 18000000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 18000000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56098.837209 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56098.837209 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56098.837209 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52325.581395 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 52325.581395 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 52325.581395 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 52325.581395 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 58 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 34 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17456000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 17456000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17456000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 17456000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17456000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 17456000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16448000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 16448000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16448000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 16448000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16448000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 16448000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 12603500 # Number of ticks simulated
-final_tick 12603500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000012 # Number of seconds simulated
+sim_ticks 12097500 # Number of ticks simulated
+final_tick 12097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 49943 # Simulator instruction rate (inst/s)
-host_op_rate 49935 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 122043566 # Simulator tick rate (ticks/s)
-host_mem_usage 220512 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 46391 # Simulator instruction rate (inst/s)
+host_op_rate 46381 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 108798708 # Simulator tick rate (ticks/s)
+host_mem_usage 217720 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
system.physmem.num_reads::total 480 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1721426588 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 715991590 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2437418177 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1721426588 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1721426588 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1721426588 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 715991590 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2437418177 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1793428394 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 745939244 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2539367638 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1793428394 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1793428394 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1793428394 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 745939244 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2539367638 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 480 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30720 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 30720 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 39 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 52 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 30 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 12035000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 480 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 3039980 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13667980 # Sum of mem lat for all requests
+system.physmem.totBusLat 1920000 # Total cycles spent in databus access
+system.physmem.totBankLat 8708000 # Total cycles spent in bank access
+system.physmem.avgQLat 6333.29 # Average queueing delay per request
+system.physmem.avgBankLat 18141.67 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 28474.96 # Average memory access latency
+system.physmem.avgRdBW 2539.37 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2539.37 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 15.87 # Data bus utilization in percentage
+system.physmem.avgRdQLen 1.13 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 380 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 79.17 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 25072.92 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
-system.cpu.numCycles 25208 # number of cpu cycles simulated
+system.cpu.numCycles 24196 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2076 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1377 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1640 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 471 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2174 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1443 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 1705 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 494 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 262 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12782 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2076 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 733 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3147 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1298 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 705 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 283 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 8516 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 3260 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1345 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 699 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1923 # Number of cache lines fetched
+system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13341 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.958099 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.266693 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 13523 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.974414 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.279455 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10194 76.41% 76.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1306 9.79% 86.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 106 0.79% 86.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 141 1.06% 88.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 294 2.20% 90.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 100 0.75% 91.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 154 1.15% 92.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 127 0.95% 93.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 919 6.89% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10263 75.89% 75.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1359 10.05% 85.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 113 0.84% 86.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 150 1.11% 87.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 301 2.23% 90.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 101 0.75% 90.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 159 1.18% 92.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 137 1.01% 93.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 940 6.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13341 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.082355 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.507061 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8622 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 899 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2969 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 11860 # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total 13523 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.089850 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.544594 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8657 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 898 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3079 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 45 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 844 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 154 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 12246 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8807 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 544 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2833 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11360 # Number of instructions processed by rename
-system.cpu.rename.LSQFullEvents 96 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 13521 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13517 # Number of integer rename lookups
+system.cpu.rename.SquashCycles 844 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 8855 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 196 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 599 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2928 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 101 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11668 # Number of instructions processed by rename
+system.cpu.rename.LSQFullEvents 92 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 7112 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 13873 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13869 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 3542 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 17 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 277 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2388 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps 3714 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 18 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 271 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2456 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1189 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 8869 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8060 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3246 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1840 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13341 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.604153 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.265993 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 9092 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8231 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 3471 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1958 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 13523 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.608667 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.271089 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9853 73.86% 73.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1401 10.50% 84.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 847 6.35% 90.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 533 4.00% 94.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 353 2.65% 97.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 227 1.70% 99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 84 0.63% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 29 0.22% 99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9982 73.81% 73.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1399 10.35% 84.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 867 6.41% 90.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 551 4.07% 94.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 358 2.65% 97.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 239 1.77% 99.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 85 0.63% 99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 28 0.21% 99.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 13341 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 13523 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 97 63.82% 65.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 3 2.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 95 63.33% 65.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 52 34.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4766 59.13% 59.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.24% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2195 27.23% 86.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1090 13.52% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4866 59.12% 59.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2254 27.38% 86.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1102 13.39% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8060 # Type of FU issued
-system.cpu.iq.rate 0.319740 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 152 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.018859 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 29653 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 12136 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7261 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8231 # Type of FU issued
+system.cpu.iq.rate 0.340180 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 150 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.018224 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30186 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 12584 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7378 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8210 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8379 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1225 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1293 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 264 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 170 # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles 844 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10299 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2388 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2456 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1189 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 360 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7692 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2065 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 368 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 364 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 7823 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2103 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1417 # number of nop insts executed
-system.cpu.iew.exec_refs 3127 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1305 # Number of branches executed
-system.cpu.iew.exec_stores 1062 # Number of stores executed
-system.cpu.iew.exec_rate 0.305141 # Inst execution rate
-system.cpu.iew.wb_sent 7351 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7263 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2827 # num instructions producing a value
-system.cpu.iew.wb_consumers 4035 # num instructions consuming a value
+system.cpu.iew.exec_nop 1455 # number of nop insts executed
+system.cpu.iew.exec_refs 3177 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1335 # Number of branches executed
+system.cpu.iew.exec_stores 1074 # Number of stores executed
+system.cpu.iew.exec_rate 0.323318 # Inst execution rate
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system.cpu.commit.committedInsts 5813 # Number of instructions committed
system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
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system.cpu.commit.function_calls 87 # Number of function calls committed.
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system.cpu.committedInsts 5156 # Number of Instructions Simulated
system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
-system.cpu.cpi 4.889061 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 4.889061 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 0.204538 # IPC: Total IPC of All Threads
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system.cpu.fp_regfile_reads 3 # number of floating regfile reads
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system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks.
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-system.cpu.icache.overall_miss_latency::total 15633000 # number of overall miss cycles
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31913.934732 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32059.882353 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32059.882353 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000011 # Number of seconds simulated
-sim_ticks 11490500 # Number of ticks simulated
-final_tick 11490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000010 # Number of seconds simulated
+sim_ticks 10184500 # Number of ticks simulated
+final_tick 10184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46998 # Simulator instruction rate (inst/s)
-host_op_rate 46991 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 93211132 # Simulator tick rate (ticks/s)
-host_mem_usage 217464 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
+host_inst_rate 98086 # Simulator instruction rate (inst/s)
+host_op_rate 98064 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 172399568 # Simulator tick rate (ticks/s)
+host_mem_usage 213936 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28992 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 29056 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 453 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1955006310 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 568121492 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2523127801 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1955006310 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1955006310 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1955006310 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 568121492 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2523127801 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total 454 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2211988807 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 640974029 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2852962836 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2211988807 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2211988807 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2211988807 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 640974029 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2852962836 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 454 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 454 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 29056 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 29056 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 49 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 39 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 27 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 29 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 10067000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 454 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 157 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 2091454 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11313454 # Sum of mem lat for all requests
+system.physmem.totBusLat 1816000 # Total cycles spent in databus access
+system.physmem.totBankLat 7406000 # Total cycles spent in bank access
+system.physmem.avgQLat 4606.73 # Average queueing delay per request
+system.physmem.avgBankLat 16312.78 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 24919.50 # Average memory access latency
+system.physmem.avgRdBW 2852.96 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2852.96 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 17.83 # Data bus utilization in percentage
+system.physmem.avgRdQLen 1.11 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 377 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.04 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 22174.01 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
-system.cpu.numCycles 22982 # number of cpu cycles simulated
+system.cpu.numCycles 20370 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2481 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 2031 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2060 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 620 # Number of BTB hits
+system.cpu.BPredUnit.lookups 2504 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 2048 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 453 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 2080 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 624 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 7156 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 14473 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 780 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2399 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1409 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 837 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 7226 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 14617 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2504 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 786 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2424 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1424 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 732 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 1870 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 316 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 11344 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.275829 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.704070 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 11348 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.288068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.714156 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 8945 78.85% 78.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 173 1.53% 80.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 163 1.44% 81.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 136 1.20% 83.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 199 1.75% 84.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 148 1.30% 86.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 251 2.21% 88.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 108 0.95% 89.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1221 10.76% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 8924 78.64% 78.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 176 1.55% 80.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 165 1.45% 81.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 138 1.22% 82.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 200 1.76% 84.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 150 1.32% 85.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 252 2.22% 88.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 109 0.96% 89.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1234 10.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 11344 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.107954 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.629754 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 7303 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 957 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2216 # Number of cycles decode is running
+system.cpu.fetch.rateDist::total 11348 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.122926 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.717575 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 7362 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 868 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2237 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 791 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 355 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 12764 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 791 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7518 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 384 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2068 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 254 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12054 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 208 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 10357 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 19653 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 19598 # Number of integer rename lookups
+system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 358 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 12862 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 473 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7582 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 226 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2090 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 230 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12157 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 192 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 10431 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 19827 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 19772 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5359 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 5433 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 528 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2068 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1915 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 56 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 10860 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 524 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2089 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1950 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 35 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 10962 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 9235 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4823 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 4140 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 9314 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4943 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 4190 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 11344 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.814087 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.547249 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 11348 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.820761 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.558908 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 7932 69.92% 69.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1090 9.61% 79.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 771 6.80% 86.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 520 4.58% 90.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 472 4.16% 95.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 326 2.87% 97.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 145 1.28% 99.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 49 0.43% 99.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 39 0.34% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 7942 69.99% 69.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1067 9.40% 79.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 770 6.79% 86.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 514 4.53% 90.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 477 4.20% 94.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 338 2.98% 97.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 150 1.32% 99.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 53 0.47% 99.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 37 0.33% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 11344 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 11348 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4 2.29% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 76 43.43% 45.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 95 54.29% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 4 2.22% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 78 43.33% 45.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 98 54.44% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5682 61.53% 61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1849 20.02% 81.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1702 18.43% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5730 61.52% 61.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1859 19.96% 81.50% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1723 18.50% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 9235 # Type of FU issued
-system.cpu.iq.rate 0.401836 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 175 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.018950 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30091 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 15718 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8353 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 9314 # Type of FU issued
+system.cpu.iq.rate 0.457241 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 180 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.019326 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30270 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 15941 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8417 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9376 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9460 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 77 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1107 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1128 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 869 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 904 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 138 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10924 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2068 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1915 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11026 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2089 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1950 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
+system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 381 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8741 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1709 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8807 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3273 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1381 # Number of branches executed
-system.cpu.iew.exec_stores 1564 # Number of stores executed
-system.cpu.iew.exec_rate 0.380341 # Inst execution rate
-system.cpu.iew.wb_sent 8540 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8380 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 4334 # num instructions producing a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5141 # The number of squashed insts skipped by commit
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system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::0 8133 77.07% 77.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1033 9.79% 86.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 640 6.06% 92.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 254 2.41% 95.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 184 1.74% 97.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 109 1.03% 98.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 61 0.58% 98.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 42 0.40% 99.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 97 0.92% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 8175 77.53% 77.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 992 9.41% 86.94% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::4 176 1.67% 96.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 108 1.02% 97.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 67 0.64% 98.60% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 10553 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 10544 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
system.cpu.commit.function_calls 103 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 21389 # The number of ROB reads
-system.cpu.rob.rob_writes 22658 # The number of ROB writes
-system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 11638 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 21469 # The number of ROB reads
+system.cpu.rob.rob_writes 22869 # The number of ROB writes
+system.cpu.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 9022 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
-system.cpu.cpi 3.967887 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.967887 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.252023 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.252023 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 13882 # number of integer regfile reads
-system.cpu.int_regfile_writes 7254 # number of integer regfile writes
+system.cpu.cpi 3.516920 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.516920 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.284340 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.284340 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 13990 # number of integer regfile reads
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system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
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-system.cpu.icache.tagsinuse 173.017509 # Cycle average of tags in use
-system.cpu.icache.total_refs 1435 # Total number of references to valid blocks.
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-system.cpu.icache.avg_refs 4.030899 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 172.348292 # Cycle average of tags in use
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses
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-system.cpu.icache.ReadReq_miss_latency::total 15962500 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 15962500 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 15962500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1870 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1870 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 1870 # number of demand (read+write) accesses
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-system.cpu.icache.ReadReq_miss_rate::total 0.232620 # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 36695.402299 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 36695.402299 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 36695.402299 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 36695.402299 # average overall miss latency
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+system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 30809.859155 # average overall miss latency
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42989.361702 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42989.361702 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 29803.977273 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40196.078431 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 32138.766520 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 29803.977273 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40196.078431 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 32138.766520 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 352 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 406 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 407 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 352 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 453 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 352 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 453 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11632000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1980500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13612500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1853000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1853000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11632000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3833500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 15465500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11632000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3833500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 15465500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total 454 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9262482 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1897546 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11160028 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1863544 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1863544 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9262482 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3761090 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 13023572 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9262482 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3761090 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 13023572 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987835 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987864 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.989083 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.989107 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.989083 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33139.601140 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36009.090909 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33528.325123 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39425.531915 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39425.531915 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33139.601140 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37583.333333 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34140.176600 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33139.601140 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37583.333333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34140.176600 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.989107 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 26313.869318 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34500.836364 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 27420.216216 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39649.872340 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39649.872340 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 26313.869318 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36873.431373 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28686.281938 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 26313.869318 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36873.431373 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28686.281938 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000019 # Number of seconds simulated
-sim_ticks 18570500 # Number of ticks simulated
-final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000018 # Number of seconds simulated
+sim_ticks 17991500 # Number of ticks simulated
+final_tick 17991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 78205 # Simulator instruction rate (inst/s)
-host_op_rate 78177 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 272440141 # Simulator tick rate (ticks/s)
-host_mem_usage 214124 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 44971 # Simulator instruction rate (inst/s)
+host_op_rate 44961 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 151823718 # Simulator tick rate (ticks/s)
+host_mem_usage 222708 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 995988261 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 461807706 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1457795967 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 995988261 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 995988261 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 995988261 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 461807706 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1457795967 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1028041019 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 476669538 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1504710558 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1028041019 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1028041019 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1028041019 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 476669538 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1504710558 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 423 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 27072 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 35 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 2 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 9 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 5 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 59 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 62 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 54 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 17940000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 423 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 113 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 1964422 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11356422 # Sum of mem lat for all requests
+system.physmem.totBusLat 1692000 # Total cycles spent in databus access
+system.physmem.totBankLat 7700000 # Total cycles spent in bank access
+system.physmem.avgQLat 4644.02 # Average queueing delay per request
+system.physmem.avgBankLat 18203.31 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 26847.33 # Average memory access latency
+system.physmem.avgRdBW 1504.71 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1504.71 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 9.40 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.63 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 336 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 37.532134 # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHitPct 37.467921 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedNotTaken 1129 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.comLoads 715 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1115 # Number of Branches instructions committed
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
-system.cpu.cpi 6.972405 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.972405 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.143423 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 6.755022 # CPI: Total CPI of All Threads
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.143423 # IPC: Total IPC of All Threads
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system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed.
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3073000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 161.896728 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 163.809669 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 135.841585 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 26.055143 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004146 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.000795 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.004941 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 12215000 # Number of ticks simulated
-final_tick 12215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 12009000 # Number of ticks simulated
+final_tick 12009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 33465 # Simulator instruction rate (inst/s)
-host_op_rate 60609 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 75963972 # Simulator tick rate (ticks/s)
-host_mem_usage 227744 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 10920 # Simulator instruction rate (inst/s)
+host_op_rate 19780 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24373770 # Simulator tick rate (ticks/s)
+host_mem_usage 225464 # Number of bytes of host memory used
+host_seconds 0.49 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9745 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28928 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 452 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1598035203 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 770200573 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2368235776 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1598035203 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1598035203 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1598035203 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 770200573 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2368235776 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.num_reads::total 450 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1625447581 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::total 2398201349 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1625447581 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1625447581 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1625447581 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 772753768 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2398201349 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 451 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28800 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28800 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 40 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 11990500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 451 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 221 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 3096951 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13440951 # Sum of mem lat for all requests
+system.physmem.totBusLat 1804000 # Total cycles spent in databus access
+system.physmem.totBankLat 8540000 # Total cycles spent in bank access
+system.physmem.avgQLat 6866.85 # Average queueing delay per request
+system.physmem.avgBankLat 18935.70 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 29802.55 # Average memory access latency
+system.physmem.avgRdBW 2398.20 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2398.20 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 14.99 # Data bus utilization in percentage
+system.physmem.avgRdQLen 1.12 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 353 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 78.27 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 26586.47 # Average gap between requests
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 24431 # number of cpu cycles simulated
+system.cpu.numCycles 24019 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 3187 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3187 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 588 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2597 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits
+system.cpu.BPredUnit.lookups 3185 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 3185 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 589 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 2591 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 7858 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 15336 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 3187 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4160 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2551 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 3088 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 59 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 17124 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.595013 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.047737 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 8560 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 15317 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 3185 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 4169 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2596 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2320 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 1999 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 297 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 17196 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.587346 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.039622 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 13067 76.31% 76.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 184 1.07% 77.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 158 0.92% 78.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 198 1.16% 79.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 177 1.03% 80.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 181 1.06% 81.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 237 1.38% 82.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 192 1.12% 84.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2730 15.94% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 13133 76.37% 76.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 180 1.05% 77.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 163 0.95% 78.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 205 1.19% 79.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 179 1.04% 80.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 184 1.07% 81.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 242 1.41% 83.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 193 1.12% 84.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2717 15.80% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 17124 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.130449 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.627727 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8263 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 3049 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3749 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 116 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1947 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 26028 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1947 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8634 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1940 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 422 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 3487 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 694 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 24257 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 601 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 26511 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 58176 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 58160 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 17196 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.132603 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.637703 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 9044 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2277 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3768 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1981 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 26083 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1981 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9405 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1279 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 293 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 3524 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 714 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 24459 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 613 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 26793 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 58583 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 58567 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 15451 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2379 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1816 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 21504 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 18146 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 221 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10979 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14783 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 17124 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.059682 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.899800 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 15733 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 29 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 2012 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2439 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1809 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 21719 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 18260 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 229 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 11155 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 15144 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 17196 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.061875 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.899452 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 11674 68.17% 68.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1321 7.71% 75.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 996 5.82% 81.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 705 4.12% 85.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 752 4.39% 90.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 712 4.16% 94.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 641 3.74% 98.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 280 1.64% 99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 43 0.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 11700 68.04% 68.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1330 7.73% 75.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1020 5.93% 81.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 704 4.09% 85.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 773 4.50% 90.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 702 4.08% 94.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 638 3.71% 98.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 284 1.65% 99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 45 0.26% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 17124 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 17196 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 166 80.19% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 80.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 21 10.14% 90.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 20 9.66% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 154 78.97% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 22 11.28% 90.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 19 9.74% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 14557 80.22% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.24% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2050 11.30% 91.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1535 8.46% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 14636 80.15% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2090 11.45% 91.63% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1529 8.37% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 18146 # Type of FU issued
-system.cpu.iq.rate 0.742745 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 207 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011407 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 53836 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 32525 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 16639 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 18260 # Type of FU issued
+system.cpu.iq.rate 0.760231 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 195 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010679 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 54132 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 32913 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 16722 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 18345 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 18446 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 130 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 141 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1327 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 21 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1387 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 875 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1947 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1327 # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles 1981 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 687 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 21541 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 44 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2379 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1816 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispatchedInsts 21753 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 45 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2439 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1809 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 70 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 643 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 713 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 17109 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1898 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1037 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 723 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 17199 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1930 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3313 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1690 # Number of branches executed
-system.cpu.iew.exec_stores 1415 # Number of stores executed
-system.cpu.iew.exec_rate 0.700299 # Inst execution rate
-system.cpu.iew.wb_sent 16835 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 16643 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 10619 # num instructions producing a value
-system.cpu.iew.wb_consumers 16444 # num instructions consuming a value
+system.cpu.iew.exec_refs 3340 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1687 # Number of branches executed
+system.cpu.iew.exec_stores 1410 # Number of stores executed
+system.cpu.iew.exec_rate 0.716058 # Inst execution rate
+system.cpu.iew.wb_sent 16930 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 16726 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 10734 # num instructions producing a value
+system.cpu.iew.wb_consumers 16630 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.681225 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.645767 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.696365 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.645460 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 11795 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 12007 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 595 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 15177 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.642090 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.514380 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 606 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 15215 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.640486 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.512697 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11633 76.65% 76.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1329 8.76% 85.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 606 3.99% 89.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 700 4.61% 94.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 357 2.35% 96.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 136 0.90% 97.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 126 0.83% 98.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 80 0.53% 98.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 210 1.38% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 11677 76.75% 76.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1319 8.67% 85.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 603 3.96% 89.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 704 4.63% 94.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 365 2.40% 96.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 135 0.89% 97.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 125 0.82% 98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 73 0.48% 98.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 214 1.41% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 15177 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 15215 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 210 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 36507 # The number of ROB reads
-system.cpu.rob.rob_writes 45058 # The number of ROB writes
-system.cpu.timesIdled 145 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7307 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 36753 # The number of ROB reads
+system.cpu.rob.rob_writes 45519 # The number of ROB writes
+system.cpu.timesIdled 141 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 6823 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5380 # Number of Instructions Simulated
system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.995595 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993485 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.995595 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.639344 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35767.605634 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33442.819149 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33657.894737 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33657.894737 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.639344 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34676.870748 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33478.982301 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30293.213115 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42536.657143 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32578.656000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34580.342105 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34580.342105 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000015 # Number of seconds simulated
-sim_ticks 14818500 # Number of ticks simulated
-final_tick 14818500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000017 # Number of seconds simulated
+sim_ticks 16578000 # Number of ticks simulated
+final_tick 16578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95139 # Simulator instruction rate (inst/s)
-host_op_rate 95123 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 110579898 # Simulator tick rate (ticks/s)
-host_mem_usage 213740 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 76899 # Simulator instruction rate (inst/s)
+host_op_rate 76894 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 100012302 # Simulator tick rate (ticks/s)
+host_mem_usage 217664 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 22720 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 355 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 980 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2699328542 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1533218612 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4232547154 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2699328542 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2699328542 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2699328542 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1533218612 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4232547154 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 975 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2412836289 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1351188322 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3764024611 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2412836289 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2412836289 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2412836289 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1351188322 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3764024611 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 975 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 975 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 62400 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 62400 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 73 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 52 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 71 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 123 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 75 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 71 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 98 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 74 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 27 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 75 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 16446000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 975 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 326 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 237 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 124 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 16512475 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 38892475 # Sum of mem lat for all requests
+system.physmem.totBusLat 3900000 # Total cycles spent in databus access
+system.physmem.totBankLat 18480000 # Total cycles spent in bank access
+system.physmem.avgQLat 16935.87 # Average queueing delay per request
+system.physmem.avgBankLat 18953.85 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 39889.72 # Average memory access latency
+system.physmem.avgRdBW 3764.02 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 3764.02 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 23.53 # Data bus utilization in percentage
+system.physmem.avgRdQLen 2.35 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 738 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 16867.69 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4173 # DTB read hits
+system.cpu.dtb.read_hits 4074 # DTB read hits
system.cpu.dtb.read_misses 101 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4274 # DTB read accesses
-system.cpu.dtb.write_hits 2094 # DTB write hits
-system.cpu.dtb.write_misses 67 # DTB write misses
+system.cpu.dtb.read_accesses 4175 # DTB read accesses
+system.cpu.dtb.write_hits 2120 # DTB write hits
+system.cpu.dtb.write_misses 61 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2161 # DTB write accesses
-system.cpu.dtb.data_hits 6267 # DTB hits
-system.cpu.dtb.data_misses 168 # DTB misses
+system.cpu.dtb.write_accesses 2181 # DTB write accesses
+system.cpu.dtb.data_hits 6194 # DTB hits
+system.cpu.dtb.data_misses 162 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 6435 # DTB accesses
-system.cpu.itb.fetch_hits 5272 # ITB hits
-system.cpu.itb.fetch_misses 65 # ITB misses
+system.cpu.dtb.data_accesses 6356 # DTB accesses
+system.cpu.itb.fetch_hits 5134 # ITB hits
+system.cpu.itb.fetch_misses 54 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 5337 # ITB accesses
+system.cpu.itb.fetch_accesses 5188 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 29638 # number of cpu cycles simulated
+system.cpu.numCycles 33157 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6610 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3711 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1792 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 4939 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 751 # Number of BTB hits
+system.cpu.BPredUnit.lookups 6335 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 3524 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1643 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 4675 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 824 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 944 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 1602 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 36672 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6610 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1695 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 6124 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1868 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 5272 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 768 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 24286 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.510006 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.874831 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 962 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 181 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 1485 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 35462 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6335 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1786 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 5973 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1719 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 5134 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 754 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 24653 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.438446 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.812361 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 18162 74.78% 74.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 487 2.01% 76.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 349 1.44% 78.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 481 1.98% 80.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 433 1.78% 81.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 367 1.51% 83.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 502 2.07% 85.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 575 2.37% 87.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2930 12.06% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 18680 75.77% 75.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 457 1.85% 77.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 358 1.45% 79.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 502 2.04% 81.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 454 1.84% 82.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 361 1.46% 84.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 481 1.95% 86.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 604 2.45% 88.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2756 11.18% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 24286 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.223024 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.237330 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 34845 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5279 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 5199 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2549 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 678 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 456 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 31855 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 699 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2549 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 35545 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2460 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 852 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 4962 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2034 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 29496 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
-system.cpu.rename.LSQFullEvents 2078 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 22198 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 36809 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 36775 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 24653 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.191061 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.069518 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 34329 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 6707 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 5019 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 579 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2403 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 637 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 388 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 30928 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 701 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2403 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34978 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3976 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 854 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 4893 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1933 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 28789 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1945 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 21557 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 36008 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 35974 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 13058 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 56 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 5621 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2720 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1336 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 12417 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 55 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 5160 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2607 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1348 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2704 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1337 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.insertedLoads 2616 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1346 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep1.conflictingLoads 14 # Number of conflicting loads.
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 26000 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21936 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 12217 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 6791 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 24286 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.903236 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.464516 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 25414 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 21500 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 11650 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 6459 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 24653 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.872105 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.460410 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15163 62.44% 62.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3175 13.07% 75.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2422 9.97% 85.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1558 6.42% 91.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1052 4.33% 96.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 575 2.37% 98.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 252 1.04% 99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 64 0.26% 99.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 25 0.10% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 15812 64.14% 64.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3038 12.32% 76.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2340 9.49% 85.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1493 6.06% 92.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1014 4.11% 96.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 592 2.40% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 274 1.11% 99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 77 0.31% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 13 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 24286 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 24653 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 11 6.15% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 105 58.66% 64.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 63 35.20% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 26 13.83% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 101 53.72% 67.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 61 32.45% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7498 68.11% 68.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.14% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2352 21.36% 89.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1154 10.48% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7329 68.16% 68.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2278 21.19% 89.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1140 10.60% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 11009 # Type of FU issued
+system.cpu.iq.FU_type_0::total 10752 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 7399 67.71% 67.73% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.74% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.74% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
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-system.cpu.iq.FU_type_1::MemWrite 1154 10.56% 100.00% # Type of FU issued
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+system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.85% # Type of FU issued
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system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 10927 # Type of FU issued
+system.cpu.iq.FU_type_1::total 10748 # Type of FU issued
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type::IntAlu 14897 67.91% 67.93% # Type of FU issued
-system.cpu.iq.FU_type::IntMult 2 0.01% 67.94% # Type of FU issued
-system.cpu.iq.FU_type::IntDiv 0 0.00% 67.94% # Type of FU issued
-system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::FloatMult 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.96% # Type of FU issued
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-system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.96% # Type of FU issued
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-system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.96% # Type of FU issued
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-system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.96% # Type of FU issued
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-system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.96% # Type of FU issued
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-system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.96% # Type of FU issued
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-system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.96% # Type of FU issued
-system.cpu.iq.FU_type::MemRead 4721 21.52% 89.48% # Type of FU issued
-system.cpu.iq.FU_type::MemWrite 2308 10.52% 100.00% # Type of FU issued
+system.cpu.iq.FU_type::IntAlu 14616 67.98% 68.00% # Type of FU issued
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+system.cpu.iq.FU_type::FloatMult 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.03% # Type of FU issued
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+system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.03% # Type of FU issued
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+system.cpu.iq.FU_type::SimdMult 0 0.00% 68.03% # Type of FU issued
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+system.cpu.iq.FU_type::SimdShift 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.03% # Type of FU issued
+system.cpu.iq.FU_type::MemRead 4580 21.30% 89.33% # Type of FU issued
+system.cpu.iq.FU_type::MemWrite 2294 10.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type::total 21936 # Type of FU issued
-system.cpu.iq.rate 0.740131 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 90 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 179 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.004103 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.004057 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.008160 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 68413 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 38274 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19529 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type::total 21500 # Type of FU issued
+system.cpu.iq.rate 0.648430 # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0 92 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1 96 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total 188 # FU busy when requested
+system.cpu.iq.fu_busy_rate::0 0.004279 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.004465 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.008744 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 67911 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 37122 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19235 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 22089 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21662 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 56 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1537 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 471 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1424 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 483 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 69 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread1.forwLoads 72 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1521 # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 472 # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads 1433 # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores 481 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2549 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 597 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 26207 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 761 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5424 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2673 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 2403 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2077 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 25609 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 858 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 5223 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2694 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 269 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1293 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1562 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20406 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2135 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2153 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4288 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1530 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 261 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1201 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1462 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20081 # Number of executed instructions
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+system.cpu.iew.iewExecLoadInsts::1 2108 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total 4188 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1419 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
-system.cpu.iew.exec_nop::0 78 # number of nop insts executed
-system.cpu.iew.exec_nop::1 77 # number of nop insts executed
-system.cpu.iew.exec_nop::total 155 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3247 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3223 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 6470 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1671 # Number of branches executed
-system.cpu.iew.exec_branches::1 1692 # Number of branches executed
-system.cpu.iew.exec_branches::total 3363 # Number of branches executed
-system.cpu.iew.exec_stores::0 1112 # Number of stores executed
-system.cpu.iew.exec_stores::1 1070 # Number of stores executed
-system.cpu.iew.exec_stores::total 2182 # Number of stores executed
-system.cpu.iew.exec_rate 0.688508 # Inst execution rate
-system.cpu.iew.wb_sent::0 9974 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 9875 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 19849 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9831 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9718 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 19549 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 5093 # num instructions producing a value
-system.cpu.iew.wb_producers::1 5062 # num instructions producing a value
-system.cpu.iew.wb_producers::total 10155 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6638 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6585 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 13223 # num instructions consuming a value
+system.cpu.iew.exec_nop::0 75 # number of nop insts executed
+system.cpu.iew.exec_nop::1 69 # number of nop insts executed
+system.cpu.iew.exec_nop::total 144 # number of nop insts executed
+system.cpu.iew.exec_refs::0 3173 # number of memory reference insts executed
+system.cpu.iew.exec_refs::1 3212 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 6385 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1610 # Number of branches executed
+system.cpu.iew.exec_branches::1 1659 # Number of branches executed
+system.cpu.iew.exec_branches::total 3269 # Number of branches executed
+system.cpu.iew.exec_stores::0 1093 # Number of stores executed
+system.cpu.iew.exec_stores::1 1104 # Number of stores executed
+system.cpu.iew.exec_stores::total 2197 # Number of stores executed
+system.cpu.iew.exec_rate 0.605634 # Inst execution rate
+system.cpu.iew.wb_sent::0 9747 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1 9790 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total 19537 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0 9617 # cumulative count of insts written-back
+system.cpu.iew.wb_count::1 9638 # cumulative count of insts written-back
+system.cpu.iew.wb_count::total 19255 # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0 5071 # num instructions producing a value
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+system.cpu.iew.wb_producers::total 10121 # num instructions producing a value
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+system.cpu.iew.wb_consumers::total 13233 # num instructions consuming a value
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0 0.331703 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.327890 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.659592 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.767249 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.768717 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 0.767980 # average fanout of values written-back
+system.cpu.iew.wb_rate::0 0.290044 # insts written-back per cycle
+system.cpu.iew.wb_rate::1 0.290678 # insts written-back per cycle
+system.cpu.iew.wb_rate::total 0.580722 # insts written-back per cycle
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+system.cpu.iew.wb_fanout::1 0.768996 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.764830 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1351 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::mean 0.527295 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 18649 76.95% 76.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 2814 11.61% 88.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1163 4.80% 93.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 521 2.15% 95.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 359 1.48% 96.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 238 0.98% 97.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 198 0.82% 98.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 82 0.34% 99.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 211 0.87% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 19177 77.95% 77.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 2699 10.97% 88.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1115 4.53% 93.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 469 1.91% 95.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 340 1.38% 96.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 279 1.13% 97.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 190 0.77% 98.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 108 0.44% 99.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 224 0.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 24235 # Number of insts commited each cycle
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system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 224 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 119797 # The number of ROB reads
-system.cpu.rob.rob_writes 54926 # The number of ROB writes
-system.cpu.timesIdled 290 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 5352 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 119315 # The number of ROB reads
+system.cpu.rob.rob_writes 53622 # The number of ROB writes
+system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 8504 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
system.cpu.committedInsts::1 6373 # Number of Instructions Simulated
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
-system.cpu.cpi::0 4.651287 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 4.650557 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.325461 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.214994 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.215028 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.430022 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 25729 # number of integer regfile reads
-system.cpu.int_regfile_writes 14801 # number of integer regfile writes
+system.cpu.cpi::0 5.203547 # CPI: Cycles Per Instruction
+system.cpu.cpi::1 5.202730 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.601569 # CPI: Total CPI of All Threads
+system.cpu.ipc::0 0.192177 # IPC: Instructions Per Cycle
+system.cpu.ipc::1 0.192207 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.384383 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 25429 # number of integer regfile reads
+system.cpu.int_regfile_writes 14534 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.icache.replacements::0 6 # number of replacements
system.cpu.icache.replacements::1 0 # number of replacements
system.cpu.icache.replacements::total 6 # number of replacements
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-system.cpu.icache.total_refs 4394 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 313.964791 # Cycle average of tags in use
+system.cpu.icache.total_refs 4270 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks.
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+system.cpu.icache.avg_refs 6.810207 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.occ_percent::total 0.154462 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 4394 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 4394 # number of ReadReq hits
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-system.cpu.icache.overall_hits::total 4394 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 878 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 878 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 878 # number of overall misses
-system.cpu.icache.overall_misses::total 878 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 33797000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 33797000 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 33797000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5272 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5272 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 5272 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 5272 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.166540 # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38493.166287 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 38493.166287 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 38493.166287 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 38493.166287 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 38493.166287 # average overall miss latency
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+system.cpu.icache.occ_percent::total 0.153303 # Average percentage of cache occupancy
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+system.cpu.icache.ReadReq_accesses::cpu.inst 5134 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits
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+system.cpu.icache.ReadReq_mshr_hits::total 237 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39816.586922 # average overall mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::total 47070.175439 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47070.175439 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 47070.175439 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements::0 0 # number of replacements
system.cpu.dcache.replacements::1 0 # number of replacements
system.cpu.dcache.replacements::total 0 # number of replacements
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38918.400000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45361.244019 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 40532.973621 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42191.780822 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42191.780822 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 40780.102041 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 40780.102041 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
+system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46196 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68142.156863 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51596.501809 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45469.178082 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45469.178082 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46196 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58684.285714 # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58684.285714 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 50678.974359 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8.166667 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 16 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 209 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 834 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8845500 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5705500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5705500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22361500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14551000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22361500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14551000 # number of overall MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19394254 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997608 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35778.400000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42322.966507 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37418.465228 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39078.767123 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40988.732394 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37665.816327 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35778.400000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40988.732394 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37665.816327 # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42891.974400 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64873.264706 # average ReadReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55412.154286 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55412.154286 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 47386.397949 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000025 # Number of seconds simulated
-sim_ticks 25317500 # Number of ticks simulated
-final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000024 # Number of seconds simulated
+sim_ticks 24110500 # Number of ticks simulated
+final_tick 24110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 84248 # Simulator instruction rate (inst/s)
-host_op_rate 84237 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 140641450 # Simulator tick rate (ticks/s)
-host_mem_usage 214032 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
+host_inst_rate 94813 # Simulator instruction rate (inst/s)
+host_op_rate 94805 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 150747979 # Simulator tick rate (ticks/s)
+host_mem_usage 222632 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 753312926 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 348849610 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1102162536 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 753312926 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 753312926 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 753312926 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 348849610 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1102162536 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 791024657 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::total 1157338089 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 791024657 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 791024657 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 791024657 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 366313432 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1157338089 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 436 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 27904 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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+system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::8 37 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 11 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 76 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 43 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 22 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 24077000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 436 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 305 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 1670434 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11016434 # Sum of mem lat for all requests
+system.physmem.totBusLat 1744000 # Total cycles spent in databus access
+system.physmem.totBankLat 7602000 # Total cycles spent in bank access
+system.physmem.avgQLat 3831.27 # Average queueing delay per request
+system.physmem.avgBankLat 17435.78 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 25267.05 # Average memory access latency
+system.physmem.avgRdBW 1157.34 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1157.34 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 7.23 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.46 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
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+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 55222.48 # Average gap between requests
system.cpu.workload.num_syscalls 18 # Number of system calls
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 5020 # Number of BP lookups
+system.cpu.branch_predictor.lookups 5021 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 3412 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect
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-system.cpu.branch_predictor.BTBHits 2141 # Number of BTB hits
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+system.cpu.branch_predictor.BTBHits 2142 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 60.875746 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 2317 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.BTBHitPct 60.886868 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 2318 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 2703 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 14367 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 22132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 22133 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 33281 # Number of cycles cpu's stages were not processed
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-system.cpu.activity 34.274034 # Percentage of cycles cpu is active
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+system.cpu.activity 35.991871 # Percentage of cycles cpu is active
system.cpu.comLoads 2225 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3358 # Number of Branches instructions committed
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
-system.cpu.cpi 3.339665 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 3.180451 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 3.339665 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.299431 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 3.180451 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.314421 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.299431 # IPC: Total IPC of All Threads
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system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 25.934118 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 41449 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 9187 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 18.143218 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 41821 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 8815 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 17.408563 # Percentage of cycles stage was utilized (processing insts).
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+system.cpu.stage0.utilization 27.232384 # Percentage of cycles stage was utilized (processing insts).
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+system.cpu.stage2.utilization 18.282112 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 5.695553 # Percentage of cycles stage was utilized (processing insts).
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+system.cpu.stage3.utilization 5.980673 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 18.401927 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization 19.323131 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.total_refs 2586 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.occ_percent::total 0.080421 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits
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-system.cpu.icache.ReadReq_miss_latency::total 20235000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 54837.398374 # average ReadReq miss latency
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks.
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56500 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56500 # average ReadReq mshr miss latency
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-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55682.352941 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 195.229432 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 196.769171 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 164.095749 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 31.133683 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.005008 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.000950 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.005958 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55471.698113 # average ReadReq miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3614500 # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41458.193980 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43367.924528 # average ReadReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
-sim_ticks 19879000 # Number of ticks simulated
-final_tick 19879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 19778500 # Number of ticks simulated
+final_tick 19778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 39676 # Simulator instruction rate (inst/s)
-host_op_rate 39674 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 54630622 # Simulator tick rate (ticks/s)
-host_mem_usage 221392 # Number of bytes of host memory used
-host_seconds 0.36 # Real time elapsed on the host
+host_inst_rate 52882 # Simulator instruction rate (inst/s)
+host_op_rate 52877 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 72439157 # Simulator tick rate (ticks/s)
+host_mem_usage 223656 # Number of bytes of host memory used
+host_seconds 0.27 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30784 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
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+system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 481 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1078525077 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 470043765 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1548568841 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1078525077 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1078525077 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1078525077 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 470043765 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1548568841 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_read::cpu.inst 1090477033 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::cpu.inst 1090477033 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1090477033 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1090477033 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 472432186 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1562909220 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 483 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30912 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 6 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 43 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 80 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 19726000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
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+system.physmem.readPktSize::6 483 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 271 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 3361480 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13231480 # Sum of mem lat for all requests
+system.physmem.totBusLat 1932000 # Total cycles spent in databus access
+system.physmem.totBankLat 7938000 # Total cycles spent in bank access
+system.physmem.avgQLat 6959.59 # Average queueing delay per request
+system.physmem.avgBankLat 16434.78 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 27394.37 # Average memory access latency
+system.physmem.avgRdBW 1562.91 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1562.91 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 9.77 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.67 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 394 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 40840.58 # Average gap between requests
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 39759 # number of cpu cycles simulated
+system.cpu.numCycles 39558 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6854 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 4554 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1112 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 4710 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 2490 # Number of BTB hits
+system.cpu.BPredUnit.lookups 6961 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 4635 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 5126 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 2626 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 477 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS 443 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 12088 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 31936 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6854 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 2967 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 9404 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3148 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7222 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 11957 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 32537 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6961 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 3069 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 9617 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3192 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 7429 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 741 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 5545 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 478 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 31399 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.017102 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.199996 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 5561 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 468 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 31813 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.022758 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.197280 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 21995 70.05% 70.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4682 14.91% 84.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 472 1.50% 86.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 410 1.31% 87.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 687 2.19% 89.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 719 2.29% 92.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 235 0.75% 93.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 265 0.84% 93.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1934 6.16% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 22196 69.77% 69.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4753 14.94% 84.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 498 1.57% 86.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 475 1.49% 87.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 708 2.23% 89.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 718 2.26% 92.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 247 0.78% 93.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 285 0.90% 93.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1933 6.08% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 31399 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.172389 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.803240 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 12738 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 7939 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 8587 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 195 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1940 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 29749 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1940 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13426 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7130 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 8156 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 488 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 27133 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 140 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 24210 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 50486 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 50486 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 31813 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.175969 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.822514 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 12679 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8183 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 8793 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 186 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1972 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 30371 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1972 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13365 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 199 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 7520 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 8338 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 419 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 27570 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 24556 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 51144 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 51144 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 10391 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 723 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2887 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 3597 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 2432 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps 10737 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 696 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 697 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 2824 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 3648 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 2459 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 22935 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 673 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21597 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 91 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8291 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 5610 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 198 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 31399 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.687824 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.304127 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 23227 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 659 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 21740 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 8509 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 6060 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 184 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 31813 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.683368 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.298612 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 22002 70.07% 70.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3599 11.46% 81.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2373 7.56% 89.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1680 5.35% 94.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 925 2.95% 97.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 497 1.58% 98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 251 0.80% 99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 55 0.18% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 22340 70.22% 70.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3583 11.26% 81.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2473 7.77% 89.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1697 5.33% 94.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 903 2.84% 97.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 492 1.55% 98.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 244 0.77% 99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 64 0.20% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 31399 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 31813 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 47 27.33% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 27 15.70% 43.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 98 56.98% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 50 28.09% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 26 14.61% 42.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 102 57.30% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 15947 73.84% 73.84% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 16052 73.84% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 3395 15.72% 89.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 2255 10.44% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 3424 15.75% 89.59% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 2264 10.41% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 21597 # Type of FU issued
-system.cpu.iq.rate 0.543198 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 172 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007964 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 74856 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 31925 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19878 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 21740 # Type of FU issued
+system.cpu.iq.rate 0.549573 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 178 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.008188 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 75584 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 32421 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19938 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21769 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21918 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1372 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1423 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 984 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 1011 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1940 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 24765 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 456 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 3597 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2432 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 673 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1972 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 25068 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 512 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 3648 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2459 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 659 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 268 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 979 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1247 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20456 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 3252 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1141 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 961 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1257 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20524 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 3260 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1216 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1157 # number of nop insts executed
-system.cpu.iew.exec_refs 5386 # number of memory reference insts executed
-system.cpu.iew.exec_branches 4298 # Number of branches executed
-system.cpu.iew.exec_stores 2134 # Number of stores executed
-system.cpu.iew.exec_rate 0.514500 # Inst execution rate
-system.cpu.iew.wb_sent 20129 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 19878 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 9203 # num instructions producing a value
-system.cpu.iew.wb_consumers 11321 # num instructions consuming a value
+system.cpu.iew.exec_nop 1182 # number of nop insts executed
+system.cpu.iew.exec_refs 5396 # number of memory reference insts executed
+system.cpu.iew.exec_branches 4297 # Number of branches executed
+system.cpu.iew.exec_stores 2136 # Number of stores executed
+system.cpu.iew.exec_rate 0.518833 # Inst execution rate
+system.cpu.iew.wb_sent 20197 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 19938 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 9248 # num instructions producing a value
+system.cpu.iew.wb_consumers 11357 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.499962 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.812914 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.504019 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.814300 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 9531 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9816 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1112 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 29476 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.514385 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.202047 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1124 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 29858 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.507804 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.195478 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 22110 75.01% 75.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 4076 13.83% 88.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1418 4.81% 93.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 772 2.62% 96.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 337 1.14% 97.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 264 0.90% 98.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 327 1.11% 99.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 72 0.24% 99.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 100 0.34% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 22523 75.43% 75.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 3989 13.36% 88.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1473 4.93% 93.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 787 2.64% 96.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 343 1.15% 97.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 245 0.82% 98.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 323 1.08% 99.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 69 0.23% 99.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106 0.36% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 29476 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 29858 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 100 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 53246 # The number of ROB reads
-system.cpu.rob.rob_writes 51332 # The number of ROB writes
-system.cpu.timesIdled 190 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 8360 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 53907 # The number of ROB reads
+system.cpu.rob.rob_writes 51935 # The number of ROB writes
+system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7745 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
-system.cpu.cpi 2.754156 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.754156 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.363088 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.363088 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 32578 # number of integer regfile reads
-system.cpu.int_regfile_writes 18091 # number of integer regfile writes
-system.cpu.misc_regfile_reads 7032 # number of misc regfile reads
+system.cpu.cpi 2.740233 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.740233 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.364933 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.364933 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 32646 # number of integer regfile reads
+system.cpu.int_regfile_writes 18155 # number of integer regfile writes
+system.cpu.misc_regfile_reads 7050 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 199.192019 # Cycle average of tags in use
-system.cpu.icache.total_refs 5061 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 15.017804 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 200.987114 # Cycle average of tags in use
+system.cpu.icache.total_refs 5096 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 15.032448 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 199.192019 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.097262 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.097262 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 5061 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 5061 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 5061 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 5061 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 5061 # number of overall hits
-system.cpu.icache.overall_hits::total 5061 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 484 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 484 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 484 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 484 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 484 # number of overall misses
-system.cpu.icache.overall_misses::total 484 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 16465500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 16465500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 16465500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 16465500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 16465500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 16465500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5545 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5545 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5545 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5545 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5545 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5545 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087286 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.087286 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.087286 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.087286 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.087286 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.087286 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34019.628099 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34019.628099 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34019.628099 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34019.628099 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34019.628099 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 200.987114 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.098138 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.098138 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 5096 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 5096 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 5096 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 5096 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 5096 # number of overall hits
+system.cpu.icache.overall_hits::total 5096 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 465 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 465 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 465 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 465 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 465 # number of overall misses
+system.cpu.icache.overall_misses::total 465 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14626000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14626000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14626000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14626000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14626000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14626000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5561 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5561 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5561 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5561 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5561 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5561 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.083618 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.083618 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.083618 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.083618 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.083618 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.083618 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31453.763441 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 31453.763441 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 31453.763441 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 31453.763441 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 31453.763441 # average overall miss latency
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38690.476190 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 35783.919598 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39012.048193 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39012.048193 # average ReadExReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38873.287671 # average overall miss latency
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000110 # Number of seconds simulated
-sim_ticks 109894000 # Number of ticks simulated
-final_tick 109894000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000109 # Number of seconds simulated
+sim_ticks 108678000 # Number of ticks simulated
+final_tick 108678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 161995 # Simulator instruction rate (inst/s)
-host_op_rate 161994 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16590549 # Simulator tick rate (ticks/s)
-host_mem_usage 228988 # Number of bytes of host memory used
-host_seconds 6.62 # Real time elapsed on the host
-sim_insts 1073027 # Number of instructions simulated
-sim_ops 1073027 # Number of ops (including micro ops) simulated
+host_inst_rate 97735 # Simulator instruction rate (inst/s)
+host_op_rate 97735 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9914053 # Simulator tick rate (ticks/s)
+host_mem_usage 237564 # Number of bytes of host memory used
+host_seconds 10.96 # Real time elapsed on the host
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+sim_ops 1071369 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
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-system.physmem.bw_read::cpu0.inst 209656578 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 97839736 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::cpu1.data 11647588 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 2329518 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 7570932 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 2329518 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7570932 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 390194187 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 209656578 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 51249386 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 2329518 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 2329518 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 265564999 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 209656578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 97839736 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 51249386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 11647588 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 2329518 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 7570932 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 2329518 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7570932 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 390194187 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total 668 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 212002429 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 98934467 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 50645025 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 11777913 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 3533374 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 7655643 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 1177791 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7655643 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 393382285 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 212002429 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 50645025 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 3533374 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 1177791 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 267358619 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 212002429 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 98934467 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 50645025 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 11777913 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 3533374 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 7655643 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 1177791 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7655643 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 393382285 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 669 # Total number of read requests seen
+system.physmem.writeReqs 0 # Total number of write requests seen
+system.physmem.cpureqs 993 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 42752 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 42752 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 71 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 36 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 29 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 56 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 61 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 5 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 79 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 44 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 108650000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 669 # Categorize read packet sizes
+system.physmem.readPktSize::7 0 # Categorize read packet sizes
+system.physmem.readPktSize::8 0 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # categorize write packet sizes
+system.physmem.writePktSize::1 0 # categorize write packet sizes
+system.physmem.writePktSize::2 0 # categorize write packet sizes
+system.physmem.writePktSize::3 0 # categorize write packet sizes
+system.physmem.writePktSize::4 0 # categorize write packet sizes
+system.physmem.writePktSize::5 0 # categorize write packet sizes
+system.physmem.writePktSize::6 0 # categorize write packet sizes
+system.physmem.writePktSize::7 0 # categorize write packet sizes
+system.physmem.writePktSize::8 0 # categorize write packet sizes
+system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 76 # categorize neither packet sizes
+system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
+system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
+system.physmem.rdQLenPdf::0 401 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.totQLat 3390669 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 18414669 # Sum of mem lat for all requests
+system.physmem.totBusLat 2676000 # Total cycles spent in databus access
+system.physmem.totBankLat 12348000 # Total cycles spent in bank access
+system.physmem.avgQLat 5068.26 # Average queueing delay per request
+system.physmem.avgBankLat 18457.40 # Average bank access latency per request
+system.physmem.avgBusLat 4000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 27525.66 # Average memory access latency
+system.physmem.avgRdBW 393.38 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 393.38 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 2.46 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.17 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 513 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 162406.58 # Average gap between requests
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 219789 # number of cpu cycles simulated
+system.cpu0.numCycles 217357 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 85747 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 83485 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 1265 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 83551 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 81101 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 85486 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 83146 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 1297 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 83094 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 80730 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 507 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.usedRAS 510 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 17217 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 509162 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 85747 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 81608 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 167267 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 3854 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 13783 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.icacheStallCycles 17254 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 507547 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 85486 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 81240 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 166653 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3954 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 12694 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines 6029 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 502 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 202015 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.520417 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.209670 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.PendingTrapStallCycles 1571 # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines 6105 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 500 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 200686 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.529060 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.210670 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 34748 17.20% 17.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 82895 41.03% 58.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 589 0.29% 58.53% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 956 0.47% 59.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 519 0.26% 59.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 78871 39.04% 98.30% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 675 0.33% 98.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 356 0.18% 98.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2406 1.19% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 34033 16.96% 16.96% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 82572 41.14% 58.10% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 593 0.30% 58.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 970 0.48% 58.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 529 0.26% 59.15% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 78464 39.10% 98.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 697 0.35% 98.59% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 363 0.18% 98.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2465 1.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 202015 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.390133 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.316595 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 17805 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 15234 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 166234 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 301 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 2441 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 506087 # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles 2441 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 18480 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 1523 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 13039 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 165885 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 647 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 502881 # Number of instructions processed by rename
-system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 343651 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 1003098 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 1003098 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 330631 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 13020 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 904 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 932 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 3938 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 161147 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 81377 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 78673 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 78441 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 420405 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 949 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 417702 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10651 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 9804 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 390 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 202015 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.067678 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.086169 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 200686 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.393298 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.335085 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 18097 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 14161 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 165636 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 283 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 2509 # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts 504485 # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles 2509 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 18775 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 695 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 12879 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 165279 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 549 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 501228 # Number of instructions processed by rename
+system.cpu0.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 342771 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 999720 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 999720 # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps 329211 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 13560 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 922 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 944 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 3899 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 160553 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 81037 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 78269 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 78067 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 419118 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 416267 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 155 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 11107 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 10171 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 200686 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.074220 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.084012 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 33785 16.72% 16.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5274 2.61% 19.33% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 80485 39.84% 59.18% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 79928 39.57% 98.74% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1527 0.76% 99.50% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 645 0.32% 99.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 270 0.13% 99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 14 0.01% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 33200 16.54% 16.54% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5091 2.54% 19.08% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 80178 39.95% 59.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 79595 39.66% 98.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1563 0.78% 99.47% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 681 0.34% 99.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 279 0.14% 99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 88 0.04% 99.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 11 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 202015 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 200686 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 46 19.74% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 73 31.33% 51.07% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 114 48.93% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 45 20.36% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 20.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 64 28.96% 49.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 176241 42.19% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 160662 38.46% 80.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 80799 19.34% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 175769 42.23% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 160047 38.45% 80.67% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 80451 19.33% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 417702 # Type of FU issued
-system.cpu0.iq.rate 1.900468 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 233 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000558 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 1037774 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 432063 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 415867 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total 416267 # Type of FU issued
+system.cpu0.iq.rate 1.915130 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.000531 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 1033596 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 431231 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 414361 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 417935 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 416488 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 78173 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads 77814 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2242 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2358 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1433 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 1114 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 500579 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 311 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 161147 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 81377 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 838 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles 2509 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 439 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 498940 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 337 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 160553 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 81037 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 840 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 383 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 1472 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 416616 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 160343 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1086 # Number of squashed instructions skipped in execute
+system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 377 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 1128 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 415155 # Number of executed instructions
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system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 79225 # number of nop insts executed
-system.cpu0.iew.exec_refs 241004 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 82800 # Number of branches executed
-system.cpu0.iew.exec_stores 80661 # Number of stores executed
-system.cpu0.iew.exec_rate 1.895527 # Inst execution rate
-system.cpu0.iew.wb_sent 416200 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 415867 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 246464 # num instructions producing a value
-system.cpu0.iew.wb_consumers 248856 # num instructions consuming a value
+system.cpu0.iew.exec_nop 78871 # number of nop insts executed
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+system.cpu0.iew.wb_count 414361 # cumulative count of insts written-back
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system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 1.892119 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.990388 # average fanout of values written-back
+system.cpu0.iew.wb_rate 1.906361 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.990033 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 12251 # The number of squashed insts skipped by commit
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system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 1265 # The number of times a branch was mispredicted
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system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 34293 17.18% 17.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 82677 41.42% 58.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2432 1.22% 59.82% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 705 0.35% 60.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 565 0.28% 60.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 77961 39.06% 99.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 418 0.21% 99.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 251 0.13% 99.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 289 0.14% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 33728 17.02% 17.02% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 82160 41.45% 58.47% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2430 1.23% 59.70% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 731 0.37% 60.07% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 570 0.29% 60.35% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 77594 39.15% 99.51% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 452 0.23% 99.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 239 0.12% 99.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 290 0.15% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 199591 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 488298 # Number of instructions committed
-system.cpu0.commit.committedOps 488298 # Number of ops (including micro ops) committed
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system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu0.commit.membars 84 # Number of memory barriers committed
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system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 328962 # Number of committed integer instructions.
+system.cpu0.commit.int_insts 327542 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 289 # number cycles where commit BW limit reached
+system.cpu0.commit.bw_lim_events 290 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 698690 # The number of ROB reads
-system.cpu0.rob.rob_writes 1003556 # The number of ROB writes
-system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 17774 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts 409636 # Number of Instructions Simulated
-system.cpu0.committedOps 409636 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 409636 # Number of Instructions Simulated
-system.cpu0.cpi 0.536547 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.536547 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.863769 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.863769 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 745424 # number of integer regfile reads
-system.cpu0.int_regfile_writes 335847 # number of integer regfile writes
+system.cpu0.rob.rob_reads 695660 # The number of ROB reads
+system.cpu0.rob.rob_writes 1000360 # The number of ROB writes
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+system.cpu0.idleCycles 16671 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts 407861 # Number of Instructions Simulated
+system.cpu0.committedOps 407861 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 407861 # Number of Instructions Simulated
+system.cpu0.cpi 0.532919 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.532919 # CPI: Total CPI of All Threads
+system.cpu0.ipc 1.876457 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.876457 # IPC: Total IPC of All Threads
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system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
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+system.cpu0.misc_regfile_reads 241901 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
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-system.cpu0.icache.avg_refs 8.942470 # Average number of references to valid blocks.
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system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28841.160221 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28841.160221 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28841.160221 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28841.160221 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 184127 # number of cpu cycles simulated
+system.cpu1.numCycles 181799 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 48566 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 45425 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 41634 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 40784 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 59567 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 56529 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 1500 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 52860 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 52019 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.usedRAS 823 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 32363 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 265611 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 48566 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 41641 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 96301 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 4375 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 40077 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles 6455 # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles 1055 # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines 23564 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 345 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 179027 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.483637 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.076927 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 25837 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 338154 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 59567 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 52842 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 115388 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 4298 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 25769 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.NoActiveThreadStallCycles 6220 # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.PendingTrapStallCycles 1046 # Number of stall cycles due to pending traps
+system.cpu1.fetch.CacheLines 17180 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 322 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 176992 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.910561 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.213171 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 82726 46.21% 46.21% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 49826 27.83% 74.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 7772 4.34% 78.38% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3158 1.76% 80.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 709 0.40% 80.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 29207 16.31% 96.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1125 0.63% 97.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 886 0.49% 97.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3618 2.02% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 61604 34.81% 34.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 57789 32.65% 67.46% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 4656 2.63% 70.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3206 1.81% 71.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 672 0.38% 72.28% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 43499 24.58% 96.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1205 0.68% 97.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 866 0.49% 98.03% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3495 1.97% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 179027 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.263764 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.442542 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 39330 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 35122 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 88807 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 6541 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2772 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 261671 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 2772 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 40116 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 20114 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 14157 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 82544 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 12869 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 259082 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 180494 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 488461 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 488461 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 165372 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 15122 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1240 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 15783 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 71004 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 32715 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 34344 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 27479 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 212625 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 7991 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 216005 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 69 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 12464 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 11017 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 179027 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.206550 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.298788 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 176992 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.327653 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.860043 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 29997 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 23620 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 110723 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 3705 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2727 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 334194 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 2727 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 30767 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 10715 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 12086 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 107285 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 7192 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 331783 # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 53 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 234003 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 646246 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 646246 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 218850 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 15153 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1340 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 9848 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 96301 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 46898 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 45474 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 41683 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 277198 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 277583 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 147 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 12330 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 11288 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 176992 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.568336 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.306945 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 80193 44.79% 44.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 27393 15.30% 60.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 32961 18.41% 78.51% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 33539 18.73% 97.24% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3241 1.81% 99.05% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1264 0.71% 99.76% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 324 0.18% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 58949 33.31% 33.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 18466 10.43% 43.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 46965 26.54% 70.27% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 47589 26.89% 97.16% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3312 1.87% 99.03% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1274 0.72% 99.75% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 318 0.18% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 58 0.03% 99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 179027 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 176992 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 20 6.78% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 65 22.03% 28.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 20 6.43% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 81 26.05% 32.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 210 67.52% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 107139 49.60% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 76812 35.56% 85.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 32054 14.84% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 132190 47.62% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 99212 35.74% 83.36% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 46181 16.64% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 216005 # Type of FU issued
-system.cpu1.iq.rate 1.173131 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001366 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 611401 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 233118 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 214044 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 277583 # Type of FU issued
+system.cpu1.iq.rate 1.526868 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 311 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001120 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 732616 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 294445 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 275571 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 216300 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 277894 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 27354 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 41481 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2609 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1525 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1604 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2772 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 1710 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 255983 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 380 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 71004 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 32715 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 2727 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 837 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 328541 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 96301 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 46898 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 60 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 1213 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 214708 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 69981 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1297 # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 494 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 1175 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 276246 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 95320 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1337 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 35367 # number of nop insts executed
-system.cpu1.iew.exec_refs 101954 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 44806 # Number of branches executed
-system.cpu1.iew.exec_stores 31973 # Number of stores executed
-system.cpu1.iew.exec_rate 1.166086 # Inst execution rate
-system.cpu1.iew.wb_sent 214321 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 214044 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 118861 # num instructions producing a value
-system.cpu1.iew.wb_consumers 123754 # num instructions consuming a value
+system.cpu1.iew.exec_nop 46466 # number of nop insts executed
+system.cpu1.iew.exec_refs 141403 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 55896 # Number of branches executed
+system.cpu1.iew.exec_stores 46083 # Number of stores executed
+system.cpu1.iew.exec_rate 1.519513 # Inst execution rate
+system.cpu1.iew.wb_sent 275857 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 275571 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 158251 # num instructions producing a value
+system.cpu1.iew.wb_consumers 163120 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.162480 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.960462 # average fanout of values written-back
+system.cpu1.iew.wb_rate 1.515800 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.970151 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 14492 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 7251 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 1525 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 169801 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.422188 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.937267 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 14237 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 4286 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 1500 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 168046 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.870327 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 2.085151 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 80979 47.69% 47.69% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 42780 25.19% 72.88% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6215 3.66% 76.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 8147 4.80% 81.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1520 0.90% 82.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 27830 16.39% 98.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 515 0.30% 98.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 1002 0.59% 99.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 57008 33.92% 33.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 53849 32.04% 65.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6186 3.68% 69.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 5193 3.09% 72.74% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1537 0.91% 73.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 41906 24.94% 98.59% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 558 0.33% 98.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 997 0.59% 99.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 812 0.48% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 169801 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 241489 # Number of instructions committed
-system.cpu1.commit.committedOps 241489 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 168046 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 314301 # Number of instructions committed
+system.cpu1.commit.committedOps 314301 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 99585 # Number of memory references committed
-system.cpu1.commit.loads 68395 # Number of loads committed
-system.cpu1.commit.membars 6536 # Number of memory barriers committed
-system.cpu1.commit.branches 43685 # Number of branches committed
+system.cpu1.commit.refs 138950 # Number of memory references committed
+system.cpu1.commit.loads 93656 # Number of loads committed
+system.cpu1.commit.membars 3574 # Number of memory barriers committed
+system.cpu1.commit.branches 54833 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 165393 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 215906 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 813 # number cycles where commit BW limit reached
+system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 424382 # The number of ROB reads
-system.cpu1.rob.rob_writes 514748 # The number of ROB writes
-system.cpu1.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 5100 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 35660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 200479 # Number of Instructions Simulated
-system.cpu1.committedOps 200479 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 200479 # Number of Instructions Simulated
-system.cpu1.cpi 0.918435 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.918435 # CPI: Total CPI of All Threads
-system.cpu1.ipc 1.088808 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.088808 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 365766 # number of integer regfile reads
-system.cpu1.int_regfile_writes 171568 # number of integer regfile writes
+system.cpu1.rob.rob_reads 495185 # The number of ROB reads
+system.cpu1.rob.rob_writes 659817 # The number of ROB writes
+system.cpu1.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 4807 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 35556 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 265102 # Number of Instructions Simulated
+system.cpu1.committedOps 265102 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 265102 # Number of Instructions Simulated
+system.cpu1.cpi 0.685770 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.685770 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.458215 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.458215 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 483798 # number of integer regfile reads
+system.cpu1.int_regfile_writes 224930 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 103658 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 143054 # number of misc regfile reads
system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
system.cpu1.icache.replacements 321 # number of replacements
-system.cpu1.icache.tagsinuse 92.890627 # Cycle average of tags in use
-system.cpu1.icache.total_refs 23041 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 438 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 52.605023 # Average number of references to valid blocks.
+system.cpu1.icache.tagsinuse 91.372145 # Cycle average of tags in use
+system.cpu1.icache.total_refs 16670 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 38.233945 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 92.890627 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.181427 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.181427 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 23041 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 23041 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 23041 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 23041 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 23041 # number of overall hits
-system.cpu1.icache.overall_hits::total 23041 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 523 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 523 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 523 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 523 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 523 # number of overall misses
-system.cpu1.icache.overall_misses::total 523 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10934000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 10934000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 10934000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 10934000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 10934000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 10934000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 23564 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 23564 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 23564 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 23564 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 23564 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 23564 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022195 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.022195 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022195 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.022195 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022195 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.022195 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20906.309751 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 20906.309751 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 20906.309751 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 20906.309751 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 66 # number of cycles access was blocked
+system.cpu1.icache.occ_blocks::cpu1.inst 91.372145 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.178461 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.178461 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 16670 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 16670 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 16670 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 16670 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 16670 # number of overall hits
+system.cpu1.icache.overall_hits::total 16670 # number of overall hits
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+system.cpu1.icache.overall_misses::total 510 # number of overall misses
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+system.cpu1.icache.ReadReq_avg_miss_latency::total 21140.196078 # average ReadReq miss latency
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+system.cpu1.icache.demand_avg_miss_latency::total 21140.196078 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21140.196078 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 21140.196078 # average overall miss latency
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system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
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-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits
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-system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits
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-system.cpu1.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses
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-system.cpu1.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses
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-system.cpu1.icache.overall_mshr_misses::total 438 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 8718000 # number of ReadReq MSHR miss cycles
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-system.cpu1.icache.demand_mshr_miss_latency::total 8718000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8718000 # number of overall MSHR miss cycles
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-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19904.109589 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_miss_latency::total 20201.834862 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.dcache.total_refs 37345 # Total number of references to valid blocks.
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system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 275 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2446500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2446500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1653500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1653500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 904000 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total 904000 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4100000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4100000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4100000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4100000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003755 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003755 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003310 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003310 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.753623 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.753623 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15290.625000 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15290.625000 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16053.398058 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16053.398058 # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17384.615385 # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17384.615385 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 294 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 294 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 294 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 294 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1540500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1540500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1377000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1377000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 447500 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 447500 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2917500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2917500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2917500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2917500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002936 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002936 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002388 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002388 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.818182 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.818182 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002686 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.002686 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002686 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.002686 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9750 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9750 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12750 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12750 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8287.037037 # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8287.037037 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10968.045113 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10968.045113 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10968.045113 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10968.045113 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.numCycles 183836 # number of cpu cycles simulated
+system.cpu2.numCycles 181474 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups 53962 # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted 50907 # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect 1502 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups 47302 # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits 46374 # Number of BTB hits
+system.cpu2.BPredUnit.lookups 55930 # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted 52799 # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect 1548 # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups 49143 # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits 48122 # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS 814 # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu2.fetch.icacheStallCycles 29545 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 300535 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 53962 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 47188 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 106111 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 4305 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 35885 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.icacheStallCycles 28647 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 313051 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 55930 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 48979 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 109339 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 4440 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 31939 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles 6446 # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles 1035 # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines 21240 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 181756 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.653508 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.139245 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.NoActiveThreadStallCycles 6238 # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles 1022 # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines 20302 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 180005 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.739124 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.167787 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 75645 41.62% 41.62% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 54116 29.77% 71.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 6682 3.68% 75.07% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3224 1.77% 76.84% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 665 0.37% 77.21% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 35775 19.68% 96.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1232 0.68% 97.57% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 880 0.48% 98.05% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3537 1.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 70666 39.26% 39.26% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 55453 30.81% 70.06% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 6160 3.42% 73.49% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3207 1.78% 75.27% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 684 0.38% 75.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 38160 21.20% 96.85% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1206 0.67% 97.52% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 867 0.48% 98.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3602 2.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 181756 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.293533 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.634799 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 35633 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 31817 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 99530 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 5601 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 2729 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 296271 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 2729 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 36405 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 17349 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 13658 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 94174 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 10995 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 293755 # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 37 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 205188 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 562117 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 562117 # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps 190142 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 15046 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1228 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 13734 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 82915 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 39246 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 39773 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 34011 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 242760 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 6943 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 245051 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 12414 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 11373 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 664 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 181756 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.348242 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.310708 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 180005 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.308198 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.725046 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 34354 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 28279 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 103112 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 5207 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 2815 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 308841 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 2815 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 35130 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 15148 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 12314 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 98150 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 10210 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 306064 # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 214486 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 588858 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 588858 # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps 198873 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 15613 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1249 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1373 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 13264 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 87101 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 41559 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 41593 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 36327 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 253620 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 6426 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 255375 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 12537 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 11608 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 180005 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.418711 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.312032 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 73115 40.23% 40.23% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 24368 13.41% 53.63% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 39333 21.64% 75.27% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 39995 22.00% 97.28% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3268 1.80% 99.08% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1268 0.70% 99.77% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 298 0.16% 99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 68069 37.82% 37.82% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 23048 12.80% 50.62% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 41620 23.12% 73.74% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 42277 23.49% 97.23% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3294 1.83% 99.06% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1277 0.71% 99.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 306 0.17% 99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 181756 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 180005 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 20 6.83% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 63 21.50% 28.33% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 118754 48.46% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 87780 35.82% 84.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 38517 15.72% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 123049 48.18% 48.18% # Type of FU issued
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+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 91506 35.83% 84.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 40820 15.98% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 245051 # Type of FU issued
-system.cpu2.iq.rate 1.332987 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 293 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 672224 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 262158 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 243059 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total 255375 # Type of FU issued
+system.cpu2.iq.rate 1.407226 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 299 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001171 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 691125 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 272626 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 253322 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 245344 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 255674 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 33799 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads 36105 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2624 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 2679 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 1636 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 2729 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 1758 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 290501 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 82915 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 39246 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles 2815 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 752 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 302670 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 87101 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 41559 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 1158 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1671 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 243729 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 81914 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1322 # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 1214 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 1723 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 254008 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 86102 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 1367 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 40798 # number of nop insts executed
-system.cpu2.iew.exec_refs 120340 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 50195 # Number of branches executed
-system.cpu2.iew.exec_stores 38426 # Number of stores executed
-system.cpu2.iew.exec_rate 1.325796 # Inst execution rate
-system.cpu2.iew.wb_sent 243343 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 243059 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 137174 # num instructions producing a value
-system.cpu2.iew.wb_consumers 142058 # num instructions consuming a value
+system.cpu2.iew.exec_nop 42624 # number of nop insts executed
+system.cpu2.iew.exec_refs 126828 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 52054 # Number of branches executed
+system.cpu2.iew.exec_stores 40726 # Number of stores executed
+system.cpu2.iew.exec_rate 1.399694 # Inst execution rate
+system.cpu2.iew.wb_sent 253605 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 253322 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 143679 # num instructions producing a value
+system.cpu2.iew.wb_consumers 148564 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.322151 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.965620 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.395913 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.967119 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 14265 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 6279 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 1502 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 172582 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.600480 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.009191 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 14523 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 5804 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 1548 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 170953 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.685416 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.035354 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 72897 42.24% 42.24% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 48196 27.93% 70.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 6187 3.58% 73.75% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 7136 4.13% 77.89% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1545 0.90% 78.78% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 34295 19.87% 98.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 518 0.30% 98.95% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 991 0.57% 99.53% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 817 0.47% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 67602 39.54% 39.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 50009 29.25% 68.80% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 6225 3.64% 72.44% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 6684 3.91% 76.35% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1541 0.90% 77.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 36526 21.37% 98.62% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 553 0.32% 98.94% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 1000 0.58% 99.52% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 172582 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 276214 # Number of instructions committed
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-system.cpu2.committedInsts_total 230713 # Number of Instructions Simulated
-system.cpu2.cpi 0.796817 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.796817 # CPI: Total CPI of All Threads
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-system.cpu2.ipc_total 1.254994 # IPC: Total IPC of All Threads
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-system.cpu2.icache.ReadReq_avg_miss_latency::total 13130.566802 # average ReadReq miss latency
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-system.cpu2.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses
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-system.cpu2.icache.ReadReq_mshr_miss_latency::total 5217500 # number of ReadReq MSHR miss cycles
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-system.cpu2.icache.demand_mshr_miss_latency::total 5217500 # number of demand (read+write) MSHR miss cycles
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-system.cpu2.dcache.demand_miss_rate::total 0.006375 # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006375 # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total 0.006375 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22976.543210 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 22976.543210 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20056.737589 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 20056.737589 # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 16923.728814 # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 16923.728814 # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 22222.527473 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22222.527473 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 22222.527473 # average overall miss latency
+system.cpu2.dcache.occ_blocks::cpu2.data 24.743159 # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data 0.048326 # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total 0.048326 # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits::cpu2.data 49553 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total 49553 # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data 39712 # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total 39712 # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data 89265 # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total 89265 # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data 89265 # number of overall hits
+system.cpu2.dcache.overall_hits::total 89265 # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data 426 # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total 426 # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data 142 # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total 142 # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data 568 # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total 568 # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data 568 # number of overall misses
+system.cpu2.dcache.overall_misses::total 568 # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5684000 # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total 5684000 # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2389500 # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total 2389500 # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 598500 # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total 598500 # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data 8073500 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total 8073500 # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data 8073500 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total 8073500 # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data 49979 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total 49979 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data 39854 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total 39854 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data 89833 # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total 89833 # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data 89833 # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total 89833 # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008524 # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total 0.008524 # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003563 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total 0.003563 # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.840580 # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total 0.840580 # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006323 # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total 0.006323 # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006323 # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total 0.006323 # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13342.723005 # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 13342.723005 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 16827.464789 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 16827.464789 # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10318.965517 # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 10318.965517 # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14213.908451 # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 14213.908451 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14213.908451 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 14213.908451 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 239 # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data 273 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total 273 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data 273 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total 273 # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 266 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data 301 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data 301 # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 160 # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 107 # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data 273 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data 273 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2062000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2062000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1458000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 880500 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total 880500 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 3520000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 3520000 # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003451 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003451 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002849 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002849 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.830986 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total 0.003187 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total 0.003187 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12421.686747 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12421.686747 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13626.168224 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13626.168224 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14923.728814 # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14923.728814 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1316000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1316000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1150500 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1150500 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 482500 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total 482500 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2466500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 2466500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2466500 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 2466500 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003201 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003201 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002685 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002685 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.840580 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.840580 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002972 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total 0.002972 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002972 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total 0.002972 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8225 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8225 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 10752.336449 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 10752.336449 # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8318.965517 # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8318.965517 # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9237.827715 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9237.827715 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9237.827715 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9237.827715 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.numCycles 183564 # number of cpu cycles simulated
+system.cpu3.numCycles 181164 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.BPredUnit.lookups 54292 # Number of BP lookups
-system.cpu3.BPredUnit.condPredicted 51137 # Number of conditional branches predicted
-system.cpu3.BPredUnit.condIncorrect 1552 # Number of conditional branches incorrect
-system.cpu3.BPredUnit.BTBLookups 47375 # Number of BTB lookups
-system.cpu3.BPredUnit.BTBHits 46456 # Number of BTB hits
+system.cpu3.BPredUnit.lookups 41552 # Number of BP lookups
+system.cpu3.BPredUnit.condPredicted 38392 # Number of conditional branches predicted
+system.cpu3.BPredUnit.condIncorrect 1515 # Number of conditional branches incorrect
+system.cpu3.BPredUnit.BTBLookups 34829 # Number of BTB lookups
+system.cpu3.BPredUnit.BTBHits 33780 # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.BPredUnit.usedRAS 865 # Number of times the RAS was used to get a target.
+system.cpu3.BPredUnit.usedRAS 860 # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu3.fetch.icacheStallCycles 29332 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 302436 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 54292 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 47321 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 106466 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 4424 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles 35508 # Number of cycles fetch has spent blocked
+system.cpu3.fetch.icacheStallCycles 36927 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 218203 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 41552 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 34640 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 84802 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 4380 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles 47727 # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles 6464 # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles 1083 # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines 21183 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 181653 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.664911 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.146175 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.NoActiveThreadStallCycles 6229 # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.PendingTrapStallCycles 974 # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines 28719 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 179453 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.215934 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 1.926514 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 75187 41.39% 41.39% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 54224 29.85% 71.24% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 6571 3.62% 74.86% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3185 1.75% 76.61% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 729 0.40% 77.01% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 36075 19.86% 96.87% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1175 0.65% 97.52% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 882 0.49% 98.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 3625 2.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 94651 52.74% 52.74% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 45326 25.26% 78.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 10365 5.78% 83.78% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3238 1.80% 85.58% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 710 0.40% 85.98% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 19490 10.86% 96.84% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1177 0.66% 97.49% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 887 0.49% 97.99% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 3609 2.01% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 181653 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.295766 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 1.647578 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 35528 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 31409 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 99893 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 5564 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 2795 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 298258 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 2795 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 36311 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 17134 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 13439 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 94588 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 10922 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 295479 # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands 206753 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 566043 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 566043 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 191392 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 15361 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1256 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1388 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 13950 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 83468 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 39555 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 39943 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 34309 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 244369 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 6827 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 246724 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 12382 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 11033 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 652 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 181653 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.358216 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.312562 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 179453 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.229361 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.204450 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 46454 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 40187 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 74815 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 8979 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 2789 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 213927 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 2789 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 47212 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 26606 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 12751 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 66126 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 17740 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 211407 # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands 144414 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 382760 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 382760 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 129180 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 15234 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1257 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1396 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 20650 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 54196 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 23010 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 27226 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 17768 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 169289 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 10641 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 175038 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 12721 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 11252 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 865 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 179453 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 0.975397 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.233089 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 72528 39.93% 39.93% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 24126 13.28% 53.21% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 39707 21.86% 75.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 40305 22.19% 97.25% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 3272 1.80% 99.06% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1282 0.71% 99.76% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 320 0.18% 99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 60 0.03% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 92486 51.54% 51.54% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 34868 19.43% 70.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 23272 12.97% 83.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 23945 13.34% 97.28% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 3213 1.79% 99.07% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1245 0.69% 99.76% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 315 0.18% 99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 181653 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 179453 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 22 7.41% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 65 21.89% 29.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 210 70.71% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 20 6.92% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 59 20.42% 27.34% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 210 72.66% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 119576 48.47% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.47% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 88284 35.78% 84.25% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 38864 15.75% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 90201 51.53% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 62467 35.69% 87.22% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 22370 12.78% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 246724 # Type of FU issued
-system.cpu3.iq.rate 1.344076 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 297 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 675462 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 263617 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 244690 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total 175038 # Type of FU issued
+system.cpu3.iq.rate 0.966185 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 289 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.001651 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 529859 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 192688 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 173081 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 247021 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 175327 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 34138 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 17671 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 2601 # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 1592 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 1490 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 2795 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 292203 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 375 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 83468 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 39555 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles 2789 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 857 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 208183 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 54196 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 23010 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1178 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 1226 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 1724 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 245374 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 82515 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 501 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 1172 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 1673 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 173760 # Number of executed instructions
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system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 41007 # number of nop insts executed
-system.cpu3.iew.exec_refs 121290 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 50490 # Number of branches executed
-system.cpu3.iew.exec_stores 38775 # Number of stores executed
-system.cpu3.iew.exec_rate 1.336722 # Inst execution rate
-system.cpu3.iew.wb_sent 244974 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 244690 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 138171 # num instructions producing a value
-system.cpu3.iew.wb_consumers 143054 # num instructions consuming a value
+system.cpu3.iew.exec_nop 28253 # number of nop insts executed
+system.cpu3.iew.exec_refs 75420 # number of memory reference insts executed
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+system.cpu3.iew.exec_rate 0.959131 # Inst execution rate
+system.cpu3.iew.wb_sent 173368 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 173081 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 92251 # num instructions producing a value
+system.cpu3.iew.wb_consumers 97140 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.332996 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.965866 # average fanout of values written-back
+system.cpu3.iew.wb_rate 0.955383 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.949671 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 14351 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 6175 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 1552 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 172395 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.611613 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 2.012919 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 14656 # The number of squashed insts skipped by commit
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+system.cpu3.commit.branchMispredicts 1515 # The number of times a branch was mispredicted
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+system.cpu3.commit.committed_per_cycle::mean 1.135365 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.770418 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 72191 41.88% 41.88% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 48466 28.11% 69.99% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 6229 3.61% 73.60% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 7040 4.08% 77.69% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1522 0.88% 78.57% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 34600 20.07% 98.64% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 541 0.31% 98.95% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 992 0.58% 99.53% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 95921 56.28% 56.28% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 35624 20.90% 77.18% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 6200 3.64% 80.82% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 10664 6.26% 87.08% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1534 0.90% 87.98% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 18221 10.69% 98.67% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 461 0.27% 98.94% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 1004 0.59% 99.53% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 807 0.47% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 172395 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 277834 # Number of instructions committed
-system.cpu3.commit.committedOps 277834 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 170436 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 193507 # Number of instructions committed
+system.cpu3.commit.committedOps 193507 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 118830 # Number of memory references committed
-system.cpu3.commit.loads 80867 # Number of loads committed
-system.cpu3.commit.membars 5460 # Number of memory barriers committed
-system.cpu3.commit.branches 49386 # Number of branches committed
+system.cpu3.commit.refs 73074 # Number of memory references committed
+system.cpu3.commit.loads 51554 # Number of loads committed
+system.cpu3.commit.membars 9056 # Number of memory barriers committed
+system.cpu3.commit.branches 36531 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 190336 # Number of committed integer instructions.
+system.cpu3.commit.int_insts 131724 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
-system.cpu3.commit.bw_lim_events 814 # number cycles where commit BW limit reached
+system.cpu3.commit.bw_lim_events 807 # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads 463179 # The number of ROB reads
-system.cpu3.rob.rob_writes 587180 # The number of ROB writes
-system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 1911 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 36223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 232199 # Number of Instructions Simulated
-system.cpu3.committedOps 232199 # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total 232199 # Number of Instructions Simulated
-system.cpu3.cpi 0.790546 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.790546 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.264948 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.264948 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 423588 # number of integer regfile reads
-system.cpu3.int_regfile_writes 197545 # number of integer regfile writes
+system.cpu3.rob.rob_reads 377205 # The number of ROB reads
+system.cpu3.rob.rob_writes 419128 # The number of ROB writes
+system.cpu3.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1711 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 36191 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 157136 # Number of Instructions Simulated
+system.cpu3.committedOps 157136 # Number of Ops (including micro ops) Simulated
+system.cpu3.committedInsts_total 157136 # Number of Instructions Simulated
+system.cpu3.cpi 1.152912 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 1.152912 # CPI: Total CPI of All Threads
+system.cpu3.ipc 0.867369 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.867369 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 286066 # number of integer regfile reads
+system.cpu3.int_regfile_writes 135262 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu3.misc_regfile_reads 122942 # number of misc regfile reads
+system.cpu3.misc_regfile_reads 77098 # number of misc regfile reads
system.cpu3.misc_regfile_writes 646 # number of misc regfile writes
-system.cpu3.icache.replacements 321 # number of replacements
-system.cpu3.icache.tagsinuse 83.581511 # Cycle average of tags in use
-system.cpu3.icache.total_refs 20679 # Total number of references to valid blocks.
+system.cpu3.icache.replacements 322 # number of replacements
+system.cpu3.icache.tagsinuse 86.042865 # Cycle average of tags in use
+system.cpu3.icache.total_refs 28227 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs 47.428899 # Average number of references to valid blocks.
+system.cpu3.icache.avg_refs 64.740826 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst 83.581511 # Average occupied blocks per requestor
-system.cpu3.icache.occ_percent::cpu3.inst 0.163245 # Average percentage of cache occupancy
-system.cpu3.icache.occ_percent::total 0.163245 # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst 20679 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 20679 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 20679 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 20679 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 20679 # number of overall hits
-system.cpu3.icache.overall_hits::total 20679 # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst 504 # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total 504 # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst 504 # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total 504 # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst 504 # number of overall misses
-system.cpu3.icache.overall_misses::total 504 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6381500 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total 6381500 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst 6381500 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total 6381500 # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst 6381500 # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total 6381500 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 21183 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 21183 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 21183 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 21183 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 21183 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 21183 # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023793 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total 0.023793 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023793 # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total 0.023793 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023793 # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total 0.023793 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12661.706349 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 12661.706349 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 12661.706349 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12661.706349 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 12661.706349 # average overall miss latency
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+system.cpu3.icache.overall_hits::total 28227 # number of overall hits
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+system.cpu3.icache.ReadReq_miss_latency::total 6235000 # number of ReadReq miss cycles
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+system.cpu3.icache.overall_miss_latency::total 6235000 # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst 28719 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total 28719 # number of ReadReq accesses(hits+misses)
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+system.cpu3.icache.overall_accesses::total 28719 # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.017132 # miss rate for ReadReq accesses
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+system.cpu3.icache.overall_miss_rate::total 0.017132 # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 12672.764228 # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 12672.764228 # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 12672.764228 # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 12672.764228 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12672.764228 # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 12672.764228 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
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-system.cpu3.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
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-system.cpu3.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
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-system.cpu3.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
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+system.cpu3.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits
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+system.cpu3.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits
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+system.cpu3.icache.overall_mshr_hits::total 56 # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 436 # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst 436 # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 436 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total 436 # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5023500 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total 5023500 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5023500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total 5023500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5023500 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total 5023500 # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020583 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total 0.020583 # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020583 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total 0.020583 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11521.788991 # average ReadReq mshr miss latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff