Make power-on delay signal synchronous

diff --git a/examples/crg.py b/examples/crg.py
index 092c31953f33e98761108ef870c5af9511850324..117503e53c11695e55447d73b6fd57e3db40fc87 100644 (file)
--- a/examples/crg.py
+++ b/examples/crg.py
@@ -109,7 +109,7 @@ class ECPIX5CRG(Elaboratable):
         pod_done = Signal()
         with m.If(podcnt != 0):
             m.d.rawclk += podcnt.eq(podcnt-1)
-        m.d.comb += pod_done.eq(podcnt == 0)
+        m.d.rawclk += pod_done.eq(podcnt == 0)
 
         # Generating sync2x (200Mhz) and init (25Mhz) from clk100
         cd_sync2x = ClockDomain("sync2x", local=False)