fhdl/verilog: fix signed constant conversion

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index e68071aece9b807c0bfde033f49c214d74ba34e4..854da372d46a944fea51c53b4cece028ef3b04a3 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -21,7 +21,7 @@ def _printexpr(ns, node):
                if node.n >= 0:
                        return str(node.bv) + str(node.n)
                else:
-                       return "-" + str(node.bv) + str(-self.n)
+                       return "-" + str(node.bv) + str(-node.n)
        elif isinstance(node, Signal):
                return ns.get_name(node)
        elif isinstance(node, _Operator):