applied Eric Anholt's patch for Athlon SSE

diff --git a/src/mesa/x86/common_x86.c b/src/mesa/x86/common_x86.c
index bcffb6a01be91d1891e2d6fc200b7b1da5013097..aaef4f8349e8ee949d9e7b5872a9f5bc0d31058b 100644 (file)
--- a/src/mesa/x86/common_x86.c
+++ b/src/mesa/x86/common_x86.c
@@ -1,4 +1,4 @@
-/* $Id: common_x86.c,v 1.18 2002/06/29 19:48:17 brianp Exp $ */
+/* $Id: common_x86.c,v 1.19 2002/07/11 15:33:02 brianp Exp $ */
 
 /*
  * Mesa 3-D graphics library
@@ -38,6 +38,10 @@
 #if defined(USE_SSE_ASM) && defined(__linux__)
 #include <signal.h>
 #endif
+#if defined(USE_SSE_ASM) && defined(__FreeBSD__)
+#include <sys/types.h>
+#include <sys/sysctl.h>
+#endif
 
 #include "context.h"
 #include "common_x86_asm.h"
@@ -213,8 +217,16 @@ static void check_os_sse_support( void )
    message( "Cannot test OS support for SSE, disabling to be safe.\n" );
    _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
+#elif defined(__FreeBSD__)
+   {
+      int ret, len, enabled;
+      len = sizeof(enabled);
+      ret = sysctlbyname("hw.instruction_sse", &enabled, &len, NULL, 0);
+      if (ret || !enabled)
+         _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
+   }
 #else
-   /* Do nothing on non-Linux platforms for now.
+   /* Do nothing on other platforms for now.
     */
    message( "Not testing OS support for SSE, leaving enabled.\n" );
 #endif /* __linux__ */

diff --git a/src/mesa/x86/common_x86_asm.S b/src/mesa/x86/common_x86_asm.S
index f877fd57c2885c0902ff03200721428af4f1ae26..6fe7443c814e4d6b9f41d85b1fe3fadd2076dff4 100644 (file)
--- a/src/mesa/x86/common_x86_asm.S
+++ b/src/mesa/x86/common_x86_asm.S
@@ -1,4 +1,4 @@
-/* $Id: common_x86_asm.S,v 1.10 2002/06/11 01:26:58 brianp Exp $ */
+/* $Id: common_x86_asm.S,v 1.11 2002/07/11 15:33:02 brianp Exp $ */
 
 /*
  * Mesa 3-D graphics library
@@ -129,6 +129,15 @@ LLBL(cpuid_amd):
         * information after we verify that the extended functions are
         * supported.
         */
+       /* The features we need are almost all in the extended set.  The
+        * exception is SSE enable, which is in the standard set (0x1).
+        */
+       MOV_L   ( CONST(0x1), EAX )
+       CPUID
+       TEST_L  ( EAX, EAX )
+       JZ      ( LLBL (cpuid_failed) )
+       MOV_L   ( EDX, ESI )
+
        MOV_L   ( CONST(0x80000000), EAX )
        CPUID
        TEST_L  ( EAX, EAX )
@@ -137,6 +146,10 @@ LLBL(cpuid_amd):
        MOV_L   ( CONST(0x80000001), EAX )
        CPUID
        MOV_L   ( EDX, EAX )
+       
+       AND_L   ( CONST(0x02000000), ESI )      /* OR in the SSE bit */
+       OR_L    ( ESI, EAX )
+       
        JMP     ( LLBL (cpuid_done) )
 
 LLBL(cpuid_other):