gallium: add AMD-specific compute TGSI enums
authorMarek Olšák <marek.olsak@amd.com>
Thu, 1 Aug 2019 01:28:40 +0000 (21:28 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 12 Aug 2019 18:52:17 +0000 (14:52 -0400)
for tgsi_to_nir

src/gallium/auxiliary/tgsi/tgsi_strings.c
src/gallium/drivers/radeonsi/si_compute.c
src/gallium/drivers/radeonsi/si_shader.c
src/gallium/drivers/radeonsi/si_shader.h
src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c
src/gallium/include/pipe/p_shader_tokens.h

index b997b53fa6e79f387f9c3916234d36a4e1db5813..558c33e5f89c01aaf1f23d6d64facf4a440d32e2 100644 (file)
@@ -108,6 +108,7 @@ const char *tgsi_semantic_names[TGSI_SEMANTIC_COUNT] =
    "SUBGROUP_GT_MASK",
    "SUBGROUP_LE_MASK",
    "SUBGROUP_LT_MASK",
+   "CS_USER_DATA_AMD",
 };
 
 const char *tgsi_texture_names[TGSI_TEXTURE_COUNT] =
@@ -160,6 +161,7 @@ const char *tgsi_property_names[TGSI_PROPERTY_COUNT] =
    "CS_FIXED_BLOCK_DEPTH",
    "MUL_ZERO_WINS",
    "VS_BLIT_SGPRS_AMD",
+   "CS_USER_DATA_COMPONENTS_AMD",
 };
 
 const char *tgsi_return_type_names[TGSI_RETURN_TYPE_COUNT] =
index 360b5a1b5108cda24e15e6fc08fc2feb2c5dc90b..22975069c999be515daf341c9d3031e9c8910a78 100644 (file)
@@ -145,7 +145,7 @@ static void si_create_compute_state_async(void *job, int thread_index)
                sel->info.uses_block_size &&
                sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
        program->num_cs_user_data_dwords =
-               sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
+               sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
 
        void *ir_binary = si_get_ir_binary(sel);
 
index e191a4a9631dd3a5537cc10a56e568d86c4fd9d4..032b6c24965549e981c527a3cd5b6469070dd590 100644 (file)
@@ -2215,7 +2215,7 @@ void si_load_system_value(struct si_shader_context *ctx,
                break;
        }
 
-       case TGSI_SEMANTIC_CS_USER_DATA:
+       case TGSI_SEMANTIC_CS_USER_DATA_AMD:
                value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
                break;
 
@@ -4978,7 +4978,7 @@ static void create_function(struct si_shader_context *ctx)
                        ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
 
                unsigned cs_user_data_dwords =
-                       shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
+                       shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
                if (cs_user_data_dwords) {
                        ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
                                                          LLVMVectorType(ctx->i32, cs_user_data_dwords));
index c942bd20ee7e8fee95db91b536a2c4a8866cc7ee..0054a48ac15e83469279a499da4d0a05fabf2d03 100644 (file)
@@ -261,18 +261,12 @@ enum {
        /* Values from set_tess_state. */
        TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT,
        TGSI_SEMANTIC_DEFAULT_TESSINNER_SI,
-
-       /* Up to 4 dwords in user SGPRs for compute shaders. */
-       TGSI_SEMANTIC_CS_USER_DATA,
 };
 
 enum {
        /* Use a property enum that CS wouldn't use. */
        TGSI_PROPERTY_CS_LOCAL_SIZE = TGSI_PROPERTY_FS_COORD_ORIGIN,
 
-       /* The number of used user data dwords in the range [1, 4]. */
-       TGSI_PROPERTY_CS_USER_DATA_DWORDS = TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
-
        /* These represent the number of SGPRs the shader uses. */
        SI_VS_BLIT_SGPRS_POS = 3,
        SI_VS_BLIT_SGPRS_POS_COLOR = 7,
index fcd885c080f278cfa5aea6c46d3c9fb10666b3a8..57f8aec550c7dff25beb1f0b8f1690ffa68bdfd6 100644 (file)
@@ -152,8 +152,8 @@ void *si_create_dma_compute_shader(struct pipe_context *ctx,
 
        struct ureg_src value;
        if (!is_copy) {
-               ureg_property(ureg, TGSI_PROPERTY_CS_USER_DATA_DWORDS, inst_dwords[0]);
-               value = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_CS_USER_DATA, 0);
+               ureg_property(ureg, TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD, inst_dwords[0]);
+               value = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_CS_USER_DATA_AMD, 0);
        }
 
        struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0);
index 0c5ee580fb0b0c7958e965930cfc08d267b43ff7..bff3b78ab24f56752dae2b2f3ba7030a71359075 100644 (file)
@@ -208,6 +208,7 @@ enum tgsi_semantic {
    TGSI_SEMANTIC_SUBGROUP_GT_MASK,
    TGSI_SEMANTIC_SUBGROUP_LE_MASK,
    TGSI_SEMANTIC_SUBGROUP_LT_MASK,
+   TGSI_SEMANTIC_CS_USER_DATA_AMD,
    TGSI_SEMANTIC_COUNT,       /**< number of semantic values */
 };
 
@@ -302,6 +303,7 @@ enum tgsi_property_name {
    TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
    TGSI_PROPERTY_MUL_ZERO_WINS,
    TGSI_PROPERTY_VS_BLIT_SGPRS_AMD,
+   TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD,
    TGSI_PROPERTY_COUNT,
 };